JP2005310956A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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Abstract
【解決手段】はんだ付け用電極が形成された半導体素子10を基材20にはんだ付けする半導体装置100の製造方法において、半導体素子10におけるはんだ付け面11を研削した後、この研削面をエッチングによって当該研削面よりも滑らかな平滑面とし、次に、前記平滑面にはんだ付け用電極を含む電極部12を形成し、しかる後、半導体素子10と基材20との間に、はんだ30を介在設定し、続いて、はんだ30の固相線温度以上に加熱してはんだ30をリフローさせることにより、はんだ付けを行う。
【選択図】図2
Description
図1(a)は、本発明の第1実施形態に係る半導体装置100の概略的な断面構成を示す図であり、図1(b)は、(a)中の半導体素子10におけるはんだ付け前の電極部112の拡大断面構成を示す図である。
本発明の第2実施形態は、半導体素子10のはんだ付け面11に付着する上記付着成分に起因するガスを、はんだ付け用電極11を透過しにくくさせることに着目してなされたものである。
本発明の第3実施形態は、半導体素子のはんだ付け面に付着する上記付着成分に起因するガスの発生を抑えるために、はんだのリフロー温度を低くすることに着目してなされたものである。
なお、上記実施形態では、はんだ付けは、水素などの還元雰囲気にて行っていたが、はんだ30が酸化しないような雰囲気であれば良く、たとえば窒素などの不活性雰囲気であってもよい。
12b…はんだ付け用電極としてのNi層、20…基材、30…はんだ。
Claims (14)
- はんだ付け用電極(12b)が形成された半導体素子(10)を基材(20)にはんだ付けする半導体装置の製造方法において、
前記半導体素子(10)におけるはんだ付け面(11)を研削した後、この研削面をエッチングによって前記研削面よりも滑らかな平滑面とし、
次に、前記平滑面に前記はんだ付け用電極(12b)を形成し、
しかる後、前記半導体素子(10)と前記基材(20)との間に、はんだ(30)を介在設定し、
続いて、前記はんだ(30)の固相線温度以上に加熱して前記はんだ(30)をリフローさせることにより、はんだ付けを行うことを特徴とする半導体装置の製造方法。 - 前記はんだ(30)として、Sn量が60%以上のものを用いることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記はんだ(30)として、Sn−Ag、Sn−Ag−Cu、Sn−Cu、Sn−Cu−Niのいずれかであって、Sn量が95%以上であるPbフリーはんだを用いることを特徴とする請求項2に記載の半導体装置の製造方法。
- 前記はんだ(30)のリフローのピーク温度は、290℃以上であることを特徴とする請求項2または3に記載の半導体装置の製造方法。
- 前記平滑面は、ウエットエッチングにて形成された鏡面であることを特徴とする請求項1ないし4のいずれか1つに記載の半導体装置の製造方法。
- はんだ付け用電極(12b)が形成された半導体素子(10)を基材(20)にはんだ付けする半導体装置の製造方法において、
前記半導体素子(10)におけるはんだ付け面(11)を研削したのみ、または、研削後この研削面をエッチングによって荒し、
次に、前記荒らされた面に前記はんだ付け用電極(12b)を形成し、
しかる後、前記半導体素子(10)と前記基材(20)との間に、はんだ(30)を介在設定し、
続いて、前記はんだ(30)の固相線温度以上であって300℃以下の温度に加熱して前記はんだ(30)をリフローさせることにより、はんだ付けを行うことを特徴とする半導体装置の製造方法。 - 前記はんだ(30)の固相線温度以上であって290℃以下の温度に加熱して前記はんだ(30)をリフローさせることを特徴とする請求項6に記載の半導体装置の製造方法。
- 前記はんだ付け用電極(12b)として、Niからなり且つはんだ付け前の膜厚が800nm未満のものを用いることを特徴とする請求項6または7に記載の半導体装置の製造方法。
- はんだ付け用電極(12b)が形成された半導体素子(10)を基材(20)にはんだ付けする半導体装置の製造方法において、
前記半導体素子(10)におけるはんだ付け面(11)を研削したのみ、または、研削後この研削面をエッチングによって荒し、
次に、前記荒らされた面に前記はんだ付け用電極(12b)を形成し、
しかる後、前記半導体素子(10)と前記基材(20)との間に、はんだ(30)を介在設定し、
続いて、前記はんだ(30)の固相線温度以上に加熱して前記はんだ(30)をリフローさせることにより、はんだ付けを行い、
前記半導体素子(10)における前記はんだ付け用電極(12b)を、はんだ付けの後に残存するようにしたことを特徴とする半導体装置の製造方法。 - 前記はんだ付け用電極(12b)として、Niからなり且つはんだ付け前の膜厚が800nm以上のものを用いることを特徴とする請求項9に記載の半導体装置の製造方法。
- 前記はんだ付けの温度は290℃以上であることを特徴とする請求項9または10に記載の半導体装置の製造方法。
- 前記はんだ(30)として、Sn−Ag、Sn−Ag−Cu、Sn−Cu、Sn−Cu−Niのいずれかであって、Sn量が95%以上であるPbフリーはんだを用いることを特徴とする請求項11に記載の半導体装置の製造方法。
- 前記はんだ(30)として、はんだペレットを用いることを特徴とする請求項1ないし12のいずれか1つに記載の半導体装置の製造方法。
- 前記はんだ(30)として、はんだペーストを用いることを特徴とする請求項1ないし12のいずれか1つに記載の半導体装置の製造方法。
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US9070387B1 (en) | 2013-08-23 | 2015-06-30 | Western Digital Technologies, Inc. | Integrated heat-assisted magnetic recording head/laser assembly |
US9042048B1 (en) | 2014-09-30 | 2015-05-26 | Western Digital (Fremont), Llc | Laser-ignited reactive HAMR bonding |
US9202478B1 (en) | 2015-02-10 | 2015-12-01 | Western Digital (Fremont), Llc | Method and structure for soldering a laser submount to a mounting face of a slider |
US10388627B1 (en) * | 2018-07-23 | 2019-08-20 | Mikro Mesa Technology Co., Ltd. | Micro-bonding structure and method of forming the same |
US10347602B1 (en) * | 2018-07-23 | 2019-07-09 | Mikro Mesa Technology Co., Ltd. | Micro-bonding structure |
EP3633717A1 (en) * | 2018-10-05 | 2020-04-08 | Infineon Technologies Austria AG | Semiconductor device, semiconductor component and method of fabricating a semiconductor device |
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JP2007294899A (ja) * | 2006-03-31 | 2007-11-08 | Dowa Electronics Materials Co Ltd | 半田層及びそれを用いた電子デバイス接合用基板並びに電子デバイス接合用サブマウント |
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JP2010118432A (ja) * | 2008-11-12 | 2010-05-27 | Denso Corp | 電子装置およびその製造方法 |
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US7601625B2 (en) | 2009-10-13 |
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