JP2005277114A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2005277114A JP2005277114A JP2004088266A JP2004088266A JP2005277114A JP 2005277114 A JP2005277114 A JP 2005277114A JP 2004088266 A JP2004088266 A JP 2004088266A JP 2004088266 A JP2004088266 A JP 2004088266A JP 2005277114 A JP2005277114 A JP 2005277114A
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- Prior art keywords
- electrode
- semiconductor device
- semiconductor chip
- lead frame
- protruding
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 136
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 230000006866 deterioration Effects 0.000 abstract description 4
- 239000010949 copper Substances 0.000 description 14
- 230000004888 barrier function Effects 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 238000007747 plating Methods 0.000 description 7
- 239000003566 sealing material Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- 230000020169 heat generation Effects 0.000 description 4
- 238000004080 punching Methods 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
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Abstract
【解決手段】 本発明の半導体装置は、半導体チップ10Aと、複数のリード端子21を有したリードフレーム20とを具備し、以下の特徴を有する。即ち、半導体チップ10Aは、その表面に形成された複数のパッド電極11と、当該半導体チップ10Aを貫通する少なくとも1つのビアホール12と、ビアホール12を通してパッド電極11と電気的に接続された柱状電極13と、柱状電極13と電気的に接続された突起電極15と、を有する。また、リードフレーム20の複数のリード端子21のうち少なくとも1つは、突起電極15と接続可能な位置に至るまで延在するようにして形成され、突起電極15と接続されていることを特徴とする。
【選択図】 図1
Description
Claims (12)
- 半導体チップと、複数の接続部を有した外部接続媒体とを具備する半導体装置であって、
前記半導体チップは、その第1の主面に形成された複数のパッド電極と、当該半導体チップを貫通する少なくとも1つのビアホールと、前記ビアホールを通して前記パッド電極と電気的に接続された柱状電極と、前記柱状電極と電気的に接続された突起電極と、を有し、
前記複数の接続部のうち少なくとも1つは、前記突起電極と接続可能な位置に至るまで延在するようにして形成され、前記突起電極と接続されていることを特徴とする半導体装置。 - 前記半導体チップの第2の主面上に、前記柱状電極と接続された配線層が形成され、
前記配線層上に前記突起電極が形成されていることを特徴とする請求項1に記載の半導体装置。 - 前記突起電極は、前記柱状電極の直上から離れて形成されていることを特徴とする請求項2記載の半導体装置。
- 前記柱状電極上に前記突起電極が形成されていることを特徴とする請求項1記載の半導体装置。
- 前記複数の接続部のうち少なくとも1つが、前記複数のパッド電極のうち少なくとも1つと、ワイヤを介して接続されていることを特徴とする請求項1,2,3,4のうちいずれか1項に記載の半導体装置。
- 半導体チップと、複数の接続部を有した外部接続媒体とを具備する半導体装置であって、
前記半導体チップの裏面に設けられた電極部を有し、
前記複数の接続部のうち少なくとも1つは、前記電極部と接続可能な位置に至るまで延在するように形成され、前記電極部と接続されていることを特徴とする半導体装置。 - 前記半導体チップの裏面上に、前記電極部と接続された配線層が形成され、
前記配線層上に突起電極が形成されていることを特徴とする請求項6に記載の半導体装置。 - 前記突起電極は、前記電極部の直上から離れて形成されていることを特徴とする請求項7記載の半導体装置。
- 前記電極部上に突起電極が形成されていることを特徴とする請求項6記載の半導体装置。
- 前記半導体チップは、その表面に形成された複数のパッド電極を有し、
前記複数の接続部のうち少なくとも1つが、前記複数のパッド電極のうち少なくとも1つと、ワイヤを介して接続されていることを特徴とする請求項6,7,8,9のうちいずれか1項に記載の半導体装置。 - 前記外部接続媒体はリードフレームであり、前記接続部はリード端子であることを特徴とする請求項1,2,3,4,5,6,7,8,9,10のうちいずれか1項に記載の半導体装置。
- 前記外部接続媒体は、導電パターンを有したフレキシブル電極シートであり、前記接続部は当該導電パターンにより当該フレキシブル電極シートに形成されていることを特徴とする請求項1,2,3,4,5,6,7,8,9,10のうちいずれか1項に記載の半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004088266A JP2005277114A (ja) | 2004-03-25 | 2004-03-25 | 半導体装置 |
TW94108300A TWI323932B (en) | 2004-03-25 | 2005-03-18 | Semiconductor device |
US11/086,990 US7605475B2 (en) | 2004-03-25 | 2005-03-23 | Semiconductor device |
CNA2005100591360A CN1681116A (zh) | 2004-03-25 | 2005-03-24 | 半导体装置 |
KR20050024408A KR100682004B1 (ko) | 2004-03-25 | 2005-03-24 | 반도체 장치 |
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JP2004088266A JP2005277114A (ja) | 2004-03-25 | 2004-03-25 | 半導体装置 |
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JP2005277114A true JP2005277114A (ja) | 2005-10-06 |
JP2005277114A5 JP2005277114A5 (ja) | 2007-05-17 |
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JP2004088266A Pending JP2005277114A (ja) | 2004-03-25 | 2004-03-25 | 半導体装置 |
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US (1) | US7605475B2 (ja) |
JP (1) | JP2005277114A (ja) |
KR (1) | KR100682004B1 (ja) |
CN (1) | CN1681116A (ja) |
TW (1) | TWI323932B (ja) |
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JP2010040862A (ja) * | 2008-08-06 | 2010-02-18 | Fujikura Ltd | 半導体装置 |
KR101014941B1 (ko) * | 2008-10-29 | 2011-02-15 | 주식회사 케이이씨 | 반도체 장치 및 그 제조 방법 |
JP5529494B2 (ja) * | 2009-10-26 | 2014-06-25 | 株式会社三井ハイテック | リードフレーム |
WO2018096826A1 (ja) * | 2016-11-28 | 2018-05-31 | 京セラ株式会社 | 半導体パッケージおよび半導体装置 |
Family Cites Families (14)
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US5095402A (en) * | 1990-10-02 | 1992-03-10 | Rogers Corporation | Internally decoupled integrated circuit package |
JPH0851179A (ja) | 1994-08-08 | 1996-02-20 | Sanyo Electric Co Ltd | 集積回路装置およびリードフレーム |
US5973396A (en) * | 1996-02-16 | 1999-10-26 | Micron Technology, Inc. | Surface mount IC using silicon vias in an area array format or same size as die array |
KR100186309B1 (ko) * | 1996-05-17 | 1999-03-20 | 문정환 | 적층형 버텀 리드 패키지 |
JP3173410B2 (ja) * | 1997-03-14 | 2001-06-04 | 松下電器産業株式会社 | パッケージ基板およびその製造方法 |
JPH10270623A (ja) * | 1997-03-24 | 1998-10-09 | Sumitomo Metal Mining Co Ltd | ボールグリッドアレイ用リードフレームおよびこれを用いた半導体装置、並びにその製造方法 |
KR100370852B1 (ko) | 1999-12-20 | 2003-02-05 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 |
JP3854054B2 (ja) * | 2000-10-10 | 2006-12-06 | 株式会社東芝 | 半導体装置 |
JP2002270718A (ja) * | 2001-03-07 | 2002-09-20 | Seiko Epson Corp | 配線基板及びその製造方法、半導体装置及びその製造方法、回路基板並びに電子機器 |
KR100426330B1 (ko) * | 2001-07-16 | 2004-04-08 | 삼성전자주식회사 | 지지 테이프를 이용한 초박형 반도체 패키지 소자 |
KR100435813B1 (ko) * | 2001-12-06 | 2004-06-12 | 삼성전자주식회사 | 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법 |
US6979904B2 (en) * | 2002-04-19 | 2005-12-27 | Micron Technology, Inc. | Integrated circuit package having reduced interconnects |
US6800930B2 (en) * | 2002-07-31 | 2004-10-05 | Micron Technology, Inc. | Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies |
JP2004186422A (ja) * | 2002-12-03 | 2004-07-02 | Shinko Electric Ind Co Ltd | 電子部品実装構造及びその製造方法 |
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2004
- 2004-03-25 JP JP2004088266A patent/JP2005277114A/ja active Pending
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- 2005-03-18 TW TW94108300A patent/TWI323932B/zh not_active IP Right Cessation
- 2005-03-23 US US11/086,990 patent/US7605475B2/en active Active
- 2005-03-24 KR KR20050024408A patent/KR100682004B1/ko not_active IP Right Cessation
- 2005-03-24 CN CNA2005100591360A patent/CN1681116A/zh active Pending
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US20050218526A1 (en) | 2005-10-06 |
CN1681116A (zh) | 2005-10-12 |
TWI323932B (en) | 2010-04-21 |
US7605475B2 (en) | 2009-10-20 |
KR100682004B1 (ko) | 2007-02-15 |
TW200605295A (en) | 2006-02-01 |
KR20060044670A (ko) | 2006-05-16 |
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