JP2005252230A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2005252230A JP2005252230A JP2004356108A JP2004356108A JP2005252230A JP 2005252230 A JP2005252230 A JP 2005252230A JP 2004356108 A JP2004356108 A JP 2004356108A JP 2004356108 A JP2004356108 A JP 2004356108A JP 2005252230 A JP2005252230 A JP 2005252230A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 229910052751 metal Inorganic materials 0.000 claims abstract description 190
- 239000002184 metal Substances 0.000 claims abstract description 190
- 239000010410 layer Substances 0.000 claims abstract description 120
- 239000011229 interlayer Substances 0.000 claims abstract description 48
- 239000000523 sample Substances 0.000 claims description 36
- 150000002739 metals Chemical class 0.000 claims description 10
- 238000007689 inspection Methods 0.000 claims description 9
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 230000001681 protective effect Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 8
- 230000002093 peripheral effect Effects 0.000 description 8
- 239000000758 substrate Substances 0.000 description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 5
- 239000011295 pitch Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- -1 gold-aluminum Chemical compound 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
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Abstract
【解決手段】本発明の半導体装置では、外部接続用電極であるパッド部が、最上層に形成された第1のパッドメタル層61と、第1のパッドメタル層61の下に層間絶縁膜71を挟んで形成された第2のパッドメタル層62と、層間絶縁膜71を貫通して第1のパッドメタル層61と第2のパッドメタル層62を電気的に接続するビア63とからなり、第1のパッドメタル層61の端部と第2のパッドメタル層62の端部とが各層の厚み方向に沿って一致しないように互いにずれて配置される。これにより、第2のパッドメタル層62のエッジに発生する応力を小さくすることができ、層間絶縁膜71などのダメージを低減できる。
【選択図】 図1
Description
図11において、22は電極パッド、31は電極パッド22を除いた半導体基板上に形成された第1の保護膜(例えば、PドープされたP−SiN膜)、32は第1の保護膜31上にさらに形成された第2の保護膜(例えば、ポリイミド膜)である。電極パッド22は、最上層に形成された第1のパッドメタル67と、一つ下の配線層に形成された第2層のパッドメタル65と、第1のパッドメタル67と第2のパッドメタル65をそれらの間の層間絶縁膜71に形成されたビア66を介して電気的に接続する積層ビア構造をとっている。ビア66はW(タングステン)等の金属で形成される。
第2のパッドメタル層の端部は、第1のパッドメタル層の端部よりも外側にずれていてよい。また第2のパッドメタル層の端部は、第1のパッドメタル層の端部よりも内側にずれていてよい。
パッド部の下の層に回路素子または配線が配設されていてよい。
本発明でいう半導体装置は、ウエハ状態の半導体集積回路装置とその個別の半導体装置の双方を含むが、ここでは半導体集積回路装置について説明する。
図2(c)においては、引出し部メタル81の幅より理解されるように、第2のメタル62の幅を第1のメタル61の幅よりも小さくしている。
図5(c)においては、引出し部メタル81の幅より理解されるように、第2のメタル62の幅を第1のメタル61の幅よりも小さくしている。
図6は本発明の第3の実施形態の半導体装置の要部構成を示し、図6(a)、(b)はそれぞれ同半導体装置の外部接続用電極であるパッドとその周辺部の平面図、断面図である。
図7(c)においては、引出し部メタル81の幅より理解されるように、第2のメタル62の幅を第1のメタル61の幅よりも小さくしている。
図8は、図6に示した第3の実施形態の半導体装置について、プロービング、ボールボンドを行なった際のパッド周辺部の状態を示し、図8(a)、(b)はそれぞれ平面図、断面図である。外部パッド69に対してプローブ針42でプロービングを行なっており、プローブ針42のすべりにより、外部パッド69上に、プローブ痕41が生じている。金属バンプ43は内部パッド68上に形成している。
図9は、入出力回路の領域上にパッド部が複数配置された様子を示す平面図である。複数のパッド部のそれぞれにおいて、内側の内部パッド68上に金属バンプ43を設けており、外側の外部パッド69上にプローブ痕41が生じている。
金属バンプ43を交互に内側の内部パッド68上と外側の外部パッド69上とに設けており、残りの内部パッド68と外部パッド69上とにプローブ痕41が生じている。
11 プローブパッド(第2のパッド領域)
21 ボンディングパッド(第1のパッド領域)
42 プローブ針
43 金属バンプ
61 最上層のパッドメタル(第1のパッドメタル層)
61a エッジ
62 第2層のパッドメタル(第2のパッドメタル層)
62a エッジ
63 ビア
64 バッファメタル(ダミーメタル)
71 層間絶縁膜
72 層間絶縁膜
73 層間絶縁膜
81 引出し部メタル
91 第3のメタル
Claims (8)
- 外部接続用電極であるパッド部が、最上層に形成された第1のパッドメタル層と、前記第1のパッドメタル層の下に層間絶縁膜を挟んで形成された第2のパッドメタル層と、前記層間絶縁膜を貫通して第1のパッドメタル層と第2のパッドメタル層を電気的に接続するビアとからなり、前記第1のパッドメタル層の端部と第2のパッドメタル層の端部とが各層の厚み方向に沿って一致しないように互いにずれて配置された半導体装置。
- 外部接続用電極であるパッド部が、ボンディング用の第1のパッド領域とプローブ検査用の第2のパッド領域とからなり、前記第1のパッド領域は、最上層に形成された第1のパッドメタル層と、前記第1のパッドメタル層の下に層間絶縁膜を挟んで形成された第2のパッドメタル層と、前記層間絶縁膜を貫通して第1のパッドメタル層と第2のパッドメタル層を電気的に接続するビアとから構成され、前記第1のパッドメタル層の端部と第2のパッドメタル層の端部とが各層の厚み方向に沿って一致しないように互いにずれて配置され、前記第2のパッド領域は、前記第1のパッドメタル層のみで構成された半導体装置。
- 第1のパッドメタル層の端部と第2のパッドメタル層の端部とが1.5〜2μmずれている請求項1または請求項2のいずれかに記載の半導体装置。
- 第2のパッドメタル層の端部は、第1のパッドメタル層の端部よりも外側にずれている請求項1または請求項2のいずれかに記載の半導体装置。
- 第2のパッドメタル層の端部は、第1のパッドメタル層の端部よりも内側にずれている請求項1または請求項2のいずれかに記載の半導体装置。
- 第2のパッド領域の第1のパッドメタル層の下に層間絶縁膜を挟んで、第2のパッドメタル層と同一層をなすように複数個のダミーメタルが配設された請求項2記載の半導体装置。
- パッド部の下の層に回路素子または配線が配設されている請求項1記載の半導体装置。
- 第1のパッド領域と第2のパッド領域の少なくとも一方の下の層に回路素子または配線が配設されている請求項2記載の半導体装置。
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JP2004356108A JP4242336B2 (ja) | 2004-02-05 | 2004-12-09 | 半導体装置 |
US11/046,697 US7391114B2 (en) | 2004-02-05 | 2005-02-01 | Electrode pad section for external connection |
TW094103037A TWI278073B (en) | 2004-02-05 | 2005-02-01 | Semiconductor device |
CNB2005100091849A CN100365809C (zh) | 2004-02-05 | 2005-02-05 | 半导体装置 |
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JP2008098225A (ja) * | 2006-10-06 | 2008-04-24 | Nec Electronics Corp | 半導体装置 |
US7851880B2 (en) | 2006-11-30 | 2010-12-14 | Sony Corporation | Solid-state imaging device |
JP2009076808A (ja) * | 2007-09-25 | 2009-04-09 | Panasonic Corp | 半導体装置 |
JP2009200394A (ja) * | 2008-02-25 | 2009-09-03 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
US7713764B2 (en) | 2008-07-10 | 2010-05-11 | Nec Electronics Corporation | Method for manufacturing semiconductor device including testing dedicated pad and probe card testing |
JP2011119765A (ja) * | 2011-03-07 | 2011-06-16 | Panasonic Corp | 半導体装置およびその製造方法 |
JP2017224753A (ja) * | 2016-06-16 | 2017-12-21 | セイコーエプソン株式会社 | 半導体装置及びその製造方法 |
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CN100365809C (zh) | 2008-01-30 |
JP4242336B2 (ja) | 2009-03-25 |
US7391114B2 (en) | 2008-06-24 |
US20050173801A1 (en) | 2005-08-11 |
TWI278073B (en) | 2007-04-01 |
TW200531225A (en) | 2005-09-16 |
CN1652329A (zh) | 2005-08-10 |
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