JP2005123591A - 半導体装置及びこれを実装した電子機器 - Google Patents
半導体装置及びこれを実装した電子機器 Download PDFInfo
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Abstract
【解決手段】ノイズを放出し易い信号線とノイズの影響を受け易い信号線とをグループ11、12に分ける。ノイズを放出し易い信号線とノイズの影響を受け易い信号線は、まず、グループに応じて、ICチップ本体10において、IC側パッド15群のうちの隔離されたIC側パッドグループに接続される。さらに、パッケージ基板20側において、やはりグループに応じて、グリッド状に二次元的に配置された外部電極24群のうちの隔離された外部電極グループに接続される。
【選択図】図1
Description
絶縁基材と、該絶縁基材の一面側に、前記IC側パッドにそれぞれ対向して電気的に接続されている基板側パッド群と、前記絶縁基材の他面側に格子状に、且つ前記基板側パッド群に取り囲まれるように配置されて、前記他面側に突出した外部電極群と、前記絶縁基材の一面側から他面側に個々に貫通した多数の貫通孔を介して前記基板側パッド群と前記外部電極群とをそれぞれ接続する多数の配線とを有するパッケージ基板とを備え、
前記ノイズを放出し易い信号線は、前記IC側パッド群のうちの第1グループのIC側パッドのそれぞれに接続され、前記ノイズの影響を受け易い信号線は、前記IC側パッド群のうちの第2グループのIC側パッドのそれぞれに接続され、
前記第1グループのIC側パッドのそれぞれは、前記外部電極群のうちの第1グループの外部電極のそれぞれに接続され、前記第2グループのIC側パッドのそれぞれは、前記外部電極群のうちの第2グループの外部電極のそれぞれに接続され、
前記第1グループのIC側パッドは、前記第2グループのIC側パッドと離間されており、前記第1グループの外部電極は、前記第2グループの外部電極と離間されていることを特徴とする。
絶縁層34である絶縁基材と、該絶縁基材の多数の貫通孔を一面側から他面側に個々に貫通しており、前記絶縁基材の前記一面側で、前記IC側パッドにそれぞれ対向して電気的に接続されているバンプ群と、前記バンプ群に取り囲まれるように、格子状に配置されている外部電極群と、前記バンプ群と前記外部電極群とを前記絶縁基材の他面側でそれぞれ接続する多数の配線とを有する再配線層とを備え、
前記ノイズを放出し易い信号線は、前記IC側パッド群のうちの第1グループのIC側パッドのそれぞれに接続され、前記ノイズの影響を受け易い信号線は、前記IC側パッド群のうちの第2グループのIC側パッドのそれぞれに接続され、
前記第1グループのIC側パッドのそれぞれは、前記外部電極群のうちの第1グループの外部電極のそれぞれに接続され、前記第2グループのIC側パッドのそれぞれは、前記外部電極群のうちの第2グループの外部電極のそれぞれに接続され、
前記第1グループのIC側パッドは、前記第2グループのIC側パッドと隔離されており、前記第1グループの外部電極は、前記第2グループの外部電極と隔離されていることを特徴とする、半導体装置。
11 ノイズを放出し易い信号線が接続されている回路部
11−1 クロック回路
11−2 パルス幅制御回路
12 ノイズの影響を受け易い信号線が接続されている回路部
12−1 増幅回路
12−2 A/D変換回路
13 大電流が流れる信号線が接続されている回路部
13−1 駆動回路
13−2 電源回路
15(P11〜P49) IC側パッド
16 バンプ
20 パッケージ基板
21(Pi1〜Piv9) 基板側パッド
22 配線
23 貫通孔
24(B1−1〜B6−6) 外部電極(ボール状電極)
30 再配線層
31 バンプ
32 配線
33 外部電極
34 絶縁層
Claims (11)
- ノイズを放出し易い信号線が接続されている回路部と、ノイズの影響を受け易い信号線が接続されている回路部とを含んで、一面の外縁部に矩形状に配列されているIC側パッド群を有するICチップ本体と、
絶縁基材と、該絶縁基材の一面側に、前記IC側パッドにそれぞれ対向して電気的に接続されている基板側パッド群と、前記絶縁基材の他面側に格子状に、且つ前記基板側パッド群に取り囲まれるように配置されて、前記他面側に突出した外部電極群と、前記絶縁基材の一面側から他面側に個々に貫通した多数の貫通孔を介して前記基板側パッド群と前記外部電極群とをそれぞれ接続する多数の配線とを有するパッケージ基板とを備え、
前記ノイズを放出し易い信号線は、前記IC側パッド群のうちの第1グループのIC側パッドのそれぞれに接続され、前記ノイズの影響を受け易い信号線は、前記IC側パッド群のうちの第2グループのIC側パッドのそれぞれに接続され、
前記第1グループのIC側パッドのそれぞれは、前記外部電極群のうちの第1グループの外部電極のそれぞれに接続され、前記第2グループのIC側パッドのそれぞれは、前記外部電極群のうちの第2グループの外部電極のそれぞれに接続され、
前記第1グループのIC側パッドは、前記第2グループのIC側パッドと離間されており、前記第1グループの外部電極は、前記第2グループの外部電極と離間されていることを特徴とする、半導体装置。 - 前記第1グループのICパッドと前記第2グループのICパッドとの間にはインピーダンスの低い1つ以上の他のICパッドを有し、前記第1グループの外部電極と前記第2グループの外部電極との間にはインピーダンスの低い1つ以上の他の外部電極を有することを特徴とする、請求項1に記載の半導体装置。
- 前記第1グループのIC側パッドと、前記第2グループのIC側パッドとは、前記IC側パッド群の異なる辺あるいはコーナーに位置していることを特徴とする、請求項1または2に記載の半導体装置。
- 前記第1グループの外部電極と、前記第2グループの外部電極とは、前記外部電極群の異なる辺で、且つ最外周もしくはそれに近接した場所に位置していることを特徴とする、請求項1乃至3のいずれかに記載の半導体装置。
- 前記第1グループの外部電極及び前記第2グループの外部電極の位置は、ノイズを放出し易い信号線であるほどまた、ノイズの影響を受け易い信号線であるほど前記外部電極群の最外周側に優先的に位置させることを特徴とする、請求項4記載の半導体装置。
- 前記ノイズを放出し易い信号線が接続されている回路部は、クロック回路または大電流入出力回路であることを特徴とする、請求項1乃至5のいずれかに記載の半導体装置。
- 前記ノイズの影響を受け易い信号線が接続されている回路部は、高入力インピーダンスの増幅回路またはアナログ特性の要求される入出力回路であることを特徴とする、請求項1乃至5のいずれかに記載の半導体装置。
- アナログ回路とディジタル回路とが混載されていることを特徴とする、請求項1乃至5のいずれかに記載の半導体装置。
- 前記外部電極は、ボール状電極であることを特徴とする、請求項1乃至8のいずれかに記載の半導体装置。
- 前記パッケージ基板は、再配線層であることを特徴とする、請求項1乃至9のいずれかに記載の半導体装置。
- 請求項1乃至10のいずれかに記載の半導体装置を実装したことを特徴とする電子機器。
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011081052A1 (ja) * | 2009-12-28 | 2011-07-07 | 株式会社日立製作所 | Lsi,鉄道用フェールセーフlsi,電子装置,鉄道用電子装置 |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100541655B1 (ko) * | 2004-01-07 | 2006-01-11 | 삼성전자주식회사 | 패키지 회로기판 및 이를 이용한 패키지 |
JP5355499B2 (ja) * | 2010-06-03 | 2013-11-27 | 株式会社東芝 | 半導体装置 |
US8813564B2 (en) | 2010-09-18 | 2014-08-26 | Fairchild Semiconductor Corporation | MEMS multi-axis gyroscope with central suspension and gimbal structure |
WO2012037540A2 (en) | 2010-09-18 | 2012-03-22 | Fairchild Semiconductor Corporation | Micromachined monolithic 3-axis gyroscope with single drive |
WO2012037538A2 (en) | 2010-09-18 | 2012-03-22 | Fairchild Semiconductor Corporation | Micromachined monolithic 6-axis inertial sensor |
KR101443730B1 (ko) | 2010-09-18 | 2014-09-23 | 페어차일드 세미컨덕터 코포레이션 | 미세기계화 다이, 및 직교 오차가 작은 서스펜션을 제조하는 방법 |
US9095072B2 (en) | 2010-09-18 | 2015-07-28 | Fairchild Semiconductor Corporation | Multi-die MEMS package |
KR20130052652A (ko) | 2010-09-18 | 2013-05-22 | 페어차일드 세미컨덕터 코포레이션 | 미세 전자 기계 시스템을 위한 시일된 패키징 |
EP2619536B1 (en) | 2010-09-20 | 2016-11-02 | Fairchild Semiconductor Corporation | Microelectromechanical pressure sensor including reference capacitor |
US9062972B2 (en) | 2012-01-31 | 2015-06-23 | Fairchild Semiconductor Corporation | MEMS multi-axis accelerometer electrode structure |
US9488693B2 (en) | 2012-04-04 | 2016-11-08 | Fairchild Semiconductor Corporation | Self test of MEMS accelerometer with ASICS integrated capacitors |
KR102058489B1 (ko) | 2012-04-05 | 2019-12-23 | 페어차일드 세미컨덕터 코포레이션 | 멤스 장치 프론트 엔드 전하 증폭기 |
EP2647952B1 (en) | 2012-04-05 | 2017-11-15 | Fairchild Semiconductor Corporation | Mems device automatic-gain control loop for mechanical amplitude drive |
EP2647955B8 (en) | 2012-04-05 | 2018-12-19 | Fairchild Semiconductor Corporation | MEMS device quadrature phase shift cancellation |
US9625272B2 (en) | 2012-04-12 | 2017-04-18 | Fairchild Semiconductor Corporation | MEMS quadrature cancellation and signal demodulation |
DE102013014881B4 (de) | 2012-09-12 | 2023-05-04 | Fairchild Semiconductor Corporation | Verbesserte Silizium-Durchkontaktierung mit einer Füllung aus mehreren Materialien |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05243472A (ja) * | 1992-02-27 | 1993-09-21 | Nec Ic Microcomput Syst Ltd | 半導体集積回路 |
JPH09331004A (ja) * | 1996-06-07 | 1997-12-22 | Casio Comput Co Ltd | 半導体装置 |
JPH1197613A (ja) * | 1997-09-19 | 1999-04-09 | Canon Inc | Icパッケージ |
JP2003068859A (ja) * | 2001-08-23 | 2003-03-07 | Hitachi Maxell Ltd | 半導体チップ及びこれを用いた半導体装置 |
JP2003086683A (ja) * | 2001-09-07 | 2003-03-20 | Ricoh Co Ltd | ボルテージレギュレータ |
JP2003209181A (ja) * | 2000-06-21 | 2003-07-25 | Hitachi Maxell Ltd | 半導体チップの製造方法 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5866939A (en) | 1996-01-21 | 1999-02-02 | Anam Semiconductor Inc. | Lead end grid array semiconductor package |
US5672911A (en) * | 1996-05-30 | 1997-09-30 | Lsi Logic Corporation | Apparatus to decouple core circuits power supply from input-output circuits power supply in a semiconductor device package |
US5691568A (en) * | 1996-05-31 | 1997-11-25 | Lsi Logic Corporation | Wire bondable package design with maxium electrical performance and minimum number of layers |
JP3177464B2 (ja) * | 1996-12-12 | 2001-06-18 | 株式会社日立製作所 | 入出力回路セル及び半導体集積回路装置 |
JP2000223576A (ja) * | 1999-02-02 | 2000-08-11 | Rohm Co Ltd | 集積回路 |
US6838773B2 (en) * | 2000-06-21 | 2005-01-04 | Hitachi Maxell, Ltd. | Semiconductor chip and semiconductor device using the semiconductor chip |
JP2002351401A (ja) * | 2001-03-21 | 2002-12-06 | Mitsubishi Electric Corp | 自発光型表示装置 |
TW511414B (en) | 2001-04-19 | 2002-11-21 | Via Tech Inc | Data processing system and method, and control chip, and printed circuit board thereof |
TW507339B (en) | 2001-07-11 | 2002-10-21 | Taiwan Semiconductor Mfg | Improved bump processing method of flip-chip bonding device |
US7358607B2 (en) * | 2002-03-06 | 2008-04-15 | Intel Corporation | Substrates and systems to minimize signal path discontinuities |
US6930381B1 (en) * | 2002-04-12 | 2005-08-16 | Apple Computer, Inc. | Wire bonding method and apparatus for integrated circuit |
CN1185703C (zh) * | 2002-06-05 | 2005-01-19 | 威盛电子股份有限公司 | 倒装芯片式封装基板 |
JP3657246B2 (ja) * | 2002-07-29 | 2005-06-08 | Necエレクトロニクス株式会社 | 半導体装置 |
US6741200B2 (en) * | 2002-08-14 | 2004-05-25 | Intel Corporation | Method and apparatus of stage amplifier of analog to digital converter |
JP2004103665A (ja) * | 2002-09-05 | 2004-04-02 | Toshiba Corp | 電子デバイスモジュール |
US6762367B2 (en) * | 2002-09-17 | 2004-07-13 | International Business Machines Corporation | Electronic package having high density signal wires with low resistance |
JP4150604B2 (ja) * | 2003-01-29 | 2008-09-17 | 日立マクセル株式会社 | 半導体装置 |
JP3811467B2 (ja) * | 2003-05-19 | 2006-08-23 | 沖電気工業株式会社 | 半導体パッケージ |
US7038319B2 (en) * | 2003-08-20 | 2006-05-02 | International Business Machines Corporation | Apparatus and method to reduce signal cross-talk |
KR101566410B1 (ko) * | 2009-04-10 | 2015-11-06 | 삼성전자주식회사 | 그라운드 임피던스를 이용하여 패키지에서의 전력 잡음을 제거한 반도체 패키지 |
-
2004
- 2004-09-07 JP JP2004259714A patent/JP2005123591A/ja active Pending
- 2004-09-15 TW TW093127830A patent/TWI336122B/zh not_active IP Right Cessation
- 2004-09-17 KR KR1020040074411A patent/KR20050030547A/ko not_active Application Discontinuation
- 2004-09-22 CN CNB2004100921722A patent/CN100392848C/zh active Active
- 2004-09-23 US US10/948,100 patent/US7719107B2/en active Active
-
2010
- 2010-03-26 US US12/748,217 patent/US7944040B2/en active Active
- 2010-12-28 US US12/980,155 patent/US8304885B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05243472A (ja) * | 1992-02-27 | 1993-09-21 | Nec Ic Microcomput Syst Ltd | 半導体集積回路 |
JPH09331004A (ja) * | 1996-06-07 | 1997-12-22 | Casio Comput Co Ltd | 半導体装置 |
JPH1197613A (ja) * | 1997-09-19 | 1999-04-09 | Canon Inc | Icパッケージ |
JP2003209181A (ja) * | 2000-06-21 | 2003-07-25 | Hitachi Maxell Ltd | 半導体チップの製造方法 |
JP2003068859A (ja) * | 2001-08-23 | 2003-03-07 | Hitachi Maxell Ltd | 半導体チップ及びこれを用いた半導体装置 |
JP2003086683A (ja) * | 2001-09-07 | 2003-03-20 | Ricoh Co Ltd | ボルテージレギュレータ |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011081052A1 (ja) * | 2009-12-28 | 2011-07-07 | 株式会社日立製作所 | Lsi,鉄道用フェールセーフlsi,電子装置,鉄道用電子装置 |
JP2011138852A (ja) * | 2009-12-28 | 2011-07-14 | Hitachi Ltd | Lsi,鉄道用フェールセーフlsi,電子装置,鉄道用電子装置 |
GB2489353A (en) * | 2009-12-28 | 2012-09-26 | Hitachi Ltd | LSI, fail-safe LSI for railways, electronic device, and electronic device for railways |
Also Published As
Publication number | Publication date |
---|---|
CN100392848C (zh) | 2008-06-04 |
US8304885B2 (en) | 2012-11-06 |
TW200512915A (en) | 2005-04-01 |
CN1617334A (zh) | 2005-05-18 |
US20100181668A1 (en) | 2010-07-22 |
US7719107B2 (en) | 2010-05-18 |
US20110089565A1 (en) | 2011-04-21 |
KR20050030547A (ko) | 2005-03-30 |
US7944040B2 (en) | 2011-05-17 |
US20050067696A1 (en) | 2005-03-31 |
TWI336122B (en) | 2011-01-11 |
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