JP2005108930A - 薄膜トランジスタの製造方法および薄膜トランジスタ - Google Patents
薄膜トランジスタの製造方法および薄膜トランジスタ Download PDFInfo
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- JP2005108930A JP2005108930A JP2003336939A JP2003336939A JP2005108930A JP 2005108930 A JP2005108930 A JP 2005108930A JP 2003336939 A JP2003336939 A JP 2003336939A JP 2003336939 A JP2003336939 A JP 2003336939A JP 2005108930 A JP2005108930 A JP 2005108930A
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Abstract
【解決手段】複数の異なるガスの反応エネルギーを利用する反応性熱CVD法によって、不純物を含有する多結晶性の半導体薄膜からなるソース・ドレイン層24を基板21上に形成する。ソース・ドレイン層24をパターニングすることにより、ソース領域24aおよびドレイン領域24bを形成する。ソース領域24aおよびドレイン領域24bを覆う状態で、複数の異なるガスの反応エネルギーを利用する反応性熱CVD法によって、多結晶性の半導体薄膜からなる活性層25を形成する。活性層25の上部にゲート絶縁膜26を形成する。ゲート絶縁膜26および活性層25を介してソース領域24aおよびドレイン領域24bの端部上に両端部が所定状態で重ねて配置されるようにゲート電極27を形成する。
【選択図】図2
Description
図1は、下記実施形態において使用される処理装置の一例を示す構成図である。この図に示す処理装置1は成膜処理装置であり、内部が気密状態に保たれるようにシールされた複数の処理室2、3を備えている。これらの処理室2、3は搬送室4を介して連通され、処理室2−処理室3間において、基板Wを大気解放することなく移送可能に構成されている。また、処理室2,3は反応性熱CVDによる成膜が可能な構成となっており、特に処理室2はプラズマCVDによる成膜も可能な構成となっている。
図2〜図4の断面工程図は、第1実施形態の薄膜トランジスタの製造方法を説明するための図である。ここでは、これらの図を用いて薄膜半導体装置としてトップゲート型の積層TFTの製造方法を説明し、さらにはこれを用いた表示装置の製造方法を説明する。
図5〜図6の断面工程図は、第2実施形態の薄膜トランジスタの製造方法を説明するための図である。ここでは、これらの図を用いて薄膜半導体装置としてボトムゲート型の積層TFTの製造方法を説明し、さらにはこれを用いた表示装置の製造方法を説明する。
Claims (3)
- 複数の異なるガスの反応エネルギーを利用する反応性熱CVD法によって、不純物を含有する多結晶性の半導体薄膜からなるソース・ドレイン層を基板上に形成する工程と、
前記ソース・ドレイン層をパターニングすることにより、ソース領域およびドレイン領域を形成する工程と、
前記ソース領域およびドレイン領域を覆う状態で、複数の異なるガスの反応エネルギーを利用する反応性熱CVD法によって、多結晶性の半導体薄膜からなる活性層を形成する工程と、
前記活性層の上部にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜および活性層を介して前記ソース領域およびドレイン領域の端部上に両端部が所定状態で重ねて配置されるようにゲート電極を形成する工程とを行う
ことを特徴とする薄膜トランジスタの製造方法。 - 基板上にゲート電極を形成し、これをゲート絶縁膜で覆う工程と、
前記ゲート絶縁膜上に、複数の異なるガスの反応エネルギーを利用する反応性熱CVD法によって、多結晶性の半導体薄膜からなる活性層を形成する工程と、
複数の異なるガスの反応エネルギーを利用する反応性熱CVD法によって、不純物を含有する多結晶性の半導体薄膜からなるソース・ドレイン層を前記活性層上に形成する工程と、
前記ソース・ドレイン層をパターニングすることにより、前記ゲート絶縁膜および活性層を介して前記ゲート電極の両端部上にそれぞれの端部が所定状態で重ねて配置されるようにソース領域とドレイン領域とを形成する工程とを行う
ことを特徴とする薄膜トランジスタの製造方法。 - 基板上に、ゲート電極と、ゲート絶縁膜と、半導体薄膜からなる活性層と、ソース領域およびドレイン領域とがこの順、または逆の順に積層されてなる薄膜トランジスタにおいて、
前記活性層と、ソース領域およびドレイン領域とが、複数の異なるガスの反応エネルギーを利用する反応性熱CVD法によって形成された多結晶性の半導体薄膜で構成され、
前記ゲート絶縁膜および活性層を介して、前記ゲート電極の両端部と、前記ソース領域およびドレイン領域の端部がそれぞれ所定状態に重ねて配置されている
ことを特徴とする薄膜トランジスタ。
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JP2003336939A JP2005108930A (ja) | 2003-09-29 | 2003-09-29 | 薄膜トランジスタの製造方法および薄膜トランジスタ |
US10/942,066 US20050070055A1 (en) | 2003-09-29 | 2004-09-15 | Thin film transistor and method for production thereof |
KR1020040076419A KR20050031398A (ko) | 2003-09-29 | 2004-09-23 | 박막 트랜지스터 및 그 제조 방법 |
US11/420,302 US20060199317A1 (en) | 2003-09-29 | 2006-05-25 | Thin film transistor and method for production thereof |
US11/763,744 US20070298553A1 (en) | 2003-09-29 | 2007-06-15 | Thin Film Transistor and Method For Production Thereof |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2006156921A (ja) * | 2004-11-30 | 2006-06-15 | Rikogaku Shinkokai | 半導体装置およびその製造方法 |
JP2008033073A (ja) * | 2006-07-31 | 2008-02-14 | Sony Corp | 表示装置およびその製造方法 |
US8654045B2 (en) | 2006-07-31 | 2014-02-18 | Sony Corporation | Display and method for manufacturing display |
JP2014187390A (ja) * | 2008-08-08 | 2014-10-02 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
JP7507220B2 (ja) | 2009-10-09 | 2024-06-27 | 株式会社半導体エネルギー研究所 | 半導体装置 |
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KR101293562B1 (ko) * | 2006-06-21 | 2013-08-06 | 삼성디스플레이 주식회사 | 유기 발광 표시 장치 및 그 제조 방법 |
KR101293566B1 (ko) | 2007-01-11 | 2013-08-06 | 삼성디스플레이 주식회사 | 유기 발광 표시 장치 및 그 제조 방법 |
JP5303119B2 (ja) * | 2007-06-05 | 2013-10-02 | 株式会社ジャパンディスプレイ | 半導体装置 |
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WO2011125275A1 (ja) * | 2010-04-06 | 2011-10-13 | シャープ株式会社 | 薄膜トランジスタ基板及びその製造方法 |
CN104992949B (zh) * | 2015-06-04 | 2018-03-09 | 京东方科技集团股份有限公司 | 一种阵列基板及其制备方法、显示装置 |
CN106356378B (zh) * | 2016-09-26 | 2023-10-27 | 合肥鑫晟光电科技有限公司 | 阵列基板及其制作方法 |
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JP3486240B2 (ja) * | 1994-10-20 | 2004-01-13 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JPH11111991A (ja) * | 1997-09-30 | 1999-04-23 | Sanyo Electric Co Ltd | 薄膜トランジスタ及び薄膜トランジスタの製造方法 |
JP2001284267A (ja) * | 2000-04-03 | 2001-10-12 | Canon Inc | 排気処理方法、プラズマ処理方法及びプラズマ処理装置 |
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2003
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2004
- 2004-09-15 US US10/942,066 patent/US20050070055A1/en not_active Abandoned
- 2004-09-23 KR KR1020040076419A patent/KR20050031398A/ko not_active Application Discontinuation
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- 2006-05-25 US US11/420,302 patent/US20060199317A1/en not_active Abandoned
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Cited By (12)
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JP2006156921A (ja) * | 2004-11-30 | 2006-06-15 | Rikogaku Shinkokai | 半導体装置およびその製造方法 |
JP2008033073A (ja) * | 2006-07-31 | 2008-02-14 | Sony Corp | 表示装置およびその製造方法 |
US8654045B2 (en) | 2006-07-31 | 2014-02-18 | Sony Corporation | Display and method for manufacturing display |
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US8994626B2 (en) | 2006-07-31 | 2015-03-31 | Sony Corporation | Display and method for manufacturing display |
JP2014187390A (ja) * | 2008-08-08 | 2014-10-02 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
US9166058B2 (en) | 2008-08-08 | 2015-10-20 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US9236456B2 (en) | 2008-08-08 | 2016-01-12 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
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JP7507220B2 (ja) | 2009-10-09 | 2024-06-27 | 株式会社半導体エネルギー研究所 | 半導体装置 |
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US20070298553A1 (en) | 2007-12-27 |
US20050070055A1 (en) | 2005-03-31 |
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US20060199317A1 (en) | 2006-09-07 |
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