1248683 九、發明說明： 【發明所屬之技術領域】 本發明特別關於一種積層型的薄膜電晶體及其製造方 法，其使用適合作為主動矩陣型之液晶顯示裝置及有機電 致發光（以下稱EL)等之驅動元件的多晶矽。 【先前技術】 主動矩陣型顯示裝置中的驅動元件中，有使用到薄膜電 晶體（thin film transistor:TFT)。其中，在與源極暨汲極區域 不同層上形成活性層的積層型TFT，相較於源極暨汲極區域 及通道區域以相同的半導體層構成的平面構造之tft，在製 程上具有使用之光罩數目少的優點。 的製造工序。[Technical Field] The present invention relates in particular to a laminated type thin film transistor and a method of manufacturing the same, which use a liquid crystal display device suitable for an active matrix type and organic electroluminescence (hereinafter referred to as EL) Wait for the polysilicon of the drive element. [Prior Art] Among the driving elements in the active matrix display device, a thin film transistor (TFT) is used. Wherein, the layered TFT forming an active layer on a different layer from the source and drain regions has a tft of a planar structure composed of the same semiconductor layer than the source and drain regions and the channel region, and is used in the process. The advantage of a small number of reticle. Manufacturing process.
。以下說明積層型TFT W面圖。為了形成此圖所示 在基板101上圖案形成閘極 圖9為底閘極型之積層TFT的剖面圖 之底閘極型的積層TFT，首先，在基$ ’接著形成閘極絕緣膜1〇3。 .、下來〃 CVD法形成由非晶矽形成之不含雜質的本壤. The W-side view of the laminated TFT will be described below. In order to form a gate electrode of a bottom gate type in which a gate electrode of FIG. 9 is patterned as a gate electrode of the bottom gate type as shown in the figure, first, a gate insulating film 1 is formed at the base $'. 3. ., 〃 〃 CVD method to form a non-impurity of the soil formed by amorphous germanium
接著， 藉由對金屬膜107及半導體薄膜 106進行圖案化， 94667.doc 1248683 形成由半導體薄膜106形成之源極區域l〇6a及汲極區域 l〇6b，由金屬膜1〇7形成之電極l〇7a、107b，而得到底閘極 . 型的積層TFT。 如上述般的底閘極型的積層TFT中，閘極絕緣膜103與活 性層104a的界面上會形成通道。此外，藉由使活性層1 〇4a 之雜質濃度為1017/cm3以下，也能使此活性層1 〇4&起作用為 電場緩和區域。 (以上，參照如下的專利文獻1) 另一方面，圖10(1)為頂閘極型之積層TFT的剖面圖。為 _ 了形成此圖所示之頂閘極型的積層TFT，首先，在基板2〇i 上形成多晶矽膜202後，利用以光阻圖案為光罩的離子植 入，將源極暨汲極形成用的雜質添加至多晶砍膜2〇2，接 著，藉由對此多晶矽膜202進行圖案化，形成源極區域扣以 及汲極區域202b。接著，以被覆源極區域2〇2a及汲極區域 2〇2b的狀態來形成非晶矽膜203,以雷射光照射此非晶矽膜 203而使其結晶化之後，藉由進行圖案化而形成由多晶矽形 φ 成之活性層203a。接著，在此活性層2〇3a上形成閑極絕緣籲 膜204(僅在剖面圖内圖示），接著，在活性層川“上介以閘 極絕緣膜204,圖案化形成閘極2〇5,藉此得到頂閉極型的 積層TFT。此外，將閘極2〇5設定成相對於源極區域搬a、， 没極區域202b具有指定的重疊部dl、们，藉此，防止在閘. 極205與源極區域202a及與汲極區域2〇孔的重疊部μ、们上 產生的寄生·電容過剩地增加。 (以上，參照如下專利文獻2)。 94667.doc 1248683 [專利文獻i】#開200 i i 〇2584號公報（參照特開中的圖 1及段落0009至0013) 【專利文獻2】專利第275919號 【發明内容】 然而，將TFT作為驅動元件使用的平面顯示器中的有機 EL顯示器’其係自發光型之元件（有機肛元件）配列而成的 顯示器，具有色重現性、廣視角、高速響應性、高對比等 的許多優良特徵。並且，用於此有機EL顯示器的有機肛元 件為電流驅動型之元件，因此，對此進行驅動的像素電晶 體以使用電流驅動能力優良之多晶矽的多晶矽tft為佳。為 此’上述的積層型的TFT中’藉由使活性層及源極暨沒極以 多晶矽來構成，可得到高的電流驅動能力。 在此，以往的多晶矽TFT的製造工序中，如上所述，乃對 非晶矽膜照射激光雷射，使其熔融再結晶化而形成多晶矽 膜。然而，依此方法，不僅需要增加結晶化工序，並且肇 因於雷射能量的偏差，薄膜電晶體的特性也會發生偏差。 此外，特別在源極及汲極的形成上，乃以離子摻雜裝置 及離子植入裝置來植入雜質，並以熱退火或燈退火等方法 來使雜質活性化。然而，此等裝置極限上能適用的基板尺 寸最大為730 X 920 mm2左右的所謂***基板，極難進行 更進一步的裝置大型化，而已經成為阻礙顯示器大型化的 原因。 有鑑於此，本發明之目的在於提供一種薄膜電晶體的製 造方法及以此方法形成之薄膜電晶體，能夠以更少的工序 94667.doc 1248683 來形成因為採用多晶性半導體薄膜而動作速度快、能夠增 加驅動電流、特性差異小的薄膜電晶體，並且能夠進行基· 板的大型化。 為達成此目的之本發明之薄膜電晶體的第一製造方法的 特徵在於以如下工序實施。首先，以利用複數相異氣體之 反應能的反應性熱CVD法，將由含雜質的多晶性半導體薄 膜形成之源極及汲極層形成在基板上。接著，藉由將源極 暨汲極層圖案化而形成源極區域及汲極區域。之後，以被 _ 覆源極區域及汲極區域的狀態，以利用複數相異氣體之反 鲁 應能的反應性熱CVD法形成由多晶性半導體薄膜形成之活 性層。並且，在此活性層的上部形成閘極絕緣膜後，以將 兩端邵經由閘極絕緣膜及活性層以特定狀態重疊配置在源 極區域及汲極區域的端部上之方式形成閘極。 此外’第二製造方法的特徵在於以如下步騾實施。首先， 在基板上形成閘極，並將此以閘極絕緣膜被覆。接著，在 閘極絕緣膜上，以利用複數相異氣體之反應能的反應性熱 馨 cv〇法，形成由多晶性半導體薄膜形成的活性層。之後，_ 以利用複數相異氣體之反應能的反應性熱CVD法，在活性 層上形成由含有雜質之多晶性半導體薄膜形成的源極暨汲 極層。接著，藉由將源極暨汲極層圖案化，以將各自的端 · 部經由閘極絕緣膜及活性層以特定狀態重疊配置在閘極的 、 兩端部上之方式形成源極區域及汲極區域。 依這種第一製造方法及第二製造方法，藉由以反應性熱 CVD去开》成活性層及源極暨汲極層，無需特別實施使半導 94667.doc 1248683 體薄膜結晶化的工序，便可得到層積由預先具有結晶性構 造之半導體薄膜形成之此等層的積層型薄膜電晶體。因 此，雖然省略結晶化的工序，藉由使活性層及源極暨汲極 層以結晶性的半導體薄膜構成，可得到比使用非晶質之半 導體薄膜時之動作速度更快的積層型薄膜電晶體。此外， 藉由省略結晶化的工序，因為沒有必要擔心起因於結晶化 工序的各種偏差，因此可謀求特性的均勻化。再者，作為 源極暨汲極層，形成已導入雜質的結晶性的半導體薄膜， 因此成膜後也沒有必要實施導入雜質的工序。 並且，特別是依第一製造方法，可得到頂閘極型的薄膜 迅曰曰體，依第二製造方法，可得到底閘極型的薄膜電晶體。 此等薄膜電晶體係經由閘極絕緣膜及活性層，將閘極的兩 袖邵與源極區域及汲極區域的端部分別重疊配置成特定狀 悲。因此，在閘極-源極區域間及閘極-汲極區域間各自成為 夾持有活性層邵分的狀態。因此，在薄膜電晶體〇N的狀態 下’此被夾持的活性層部分為電場所調變而成低電阻，使 ON電流增大。 此外，本發明也為一種藉由上述的第一製造方法及第二 製造方法得到的薄膜半導體裝置，且活性層、源極區域及 沒極區域係以利用複數相異氣體之反應能的反應性熱Cvd 法形成的多晶性半導體薄膜所構成。並且，特徵為經由閘 極絕緣膜及活性層’將閘極電極的兩端部與源極區域及汲 極區域的端部分別重疊配置成特定狀態。 如上述I說明，依本發明之薄膜電晶體之製造方法，藉 94667.doc 1248683 由以反應性熱CVD法成膜出活性層及源極暨汲極層，無需 進行使半導體薄膜結晶化的工序及對源極暨汲極層添加雜* 質的工序，利用動作速度快的多晶性的半導體薄膜，便可 v 得到可使ON電流變大（即，驅動電流變大）的積層型薄膜電 晶體。依此結果，不僅可簡化製造工序及減少製造成本， 並可得到結晶化所致之差異被消弭的薄膜電晶體。此外， 如上所述’藉由省略結晶化工序及雜質添加工序，可對大 型基板形成特性均勻的薄膜電晶體，實現具有此薄膜電晶 _ 體之顯TF裝置的大型化。 · 此外’依本發明之薄膜電晶體，藉由以反應性熱Cvd法 得到的多晶性半導體薄膜來構成源極暨汲極層及活性層， 可使積層型薄膜電晶體的動作速度提升，並藉由在源極區 域及汲極區域與閘極之間設置指定的重疊部分，可使驅動 電流增大。 【實施方式】Next, by patterning the metal film 107 and the semiconductor film 106, 94667.doc 1248683 forms a source region 16a and a drain region 16b formed by the semiconductor film 106, and an electrode formed of the metal film 1? L〇7a, 107b, and a bottom gate type laminated TFT is obtained. In the bottom gate type multilayer TFT as described above, a channel is formed at the interface between the gate insulating film 103 and the active layer 104a. Further, by setting the impurity concentration of the active layer 1 〇 4a to 1017 / cm 3 or less, the active layer 1 〇 4 & can function as an electric field relaxation region. (Patent Document 1 below) On the other hand, Fig. 10 (1) is a cross-sectional view of a multilayer gate type multilayer TFT. In order to form the top gate type multilayer TFT shown in this figure, first, after the polysilicon film 202 is formed on the substrate 2〇i, the source and the drain are used by ion implantation using the photoresist pattern as a mask. The impurity for formation is added to the polycrystalline dicing film 2〇2, and then, the source region button and the drain region 202b are formed by patterning the polysilicon film 202. Then, the amorphous germanium film 203 is formed in a state in which the source region 2〇2a and the drain region 2〇2b are covered, and the amorphous germanium film 203 is irradiated with laser light to be crystallized, and then patterned by patterning. An active layer 203a formed of a polycrystalline crucible φ is formed. Next, a dummy insulating film 204 is formed on the active layer 2A3a (illustrated only in the cross-sectional view), and then, the gate layer 2 is patterned by forming a gate electrode 2 on the active layer. 5, thereby obtaining a top-closed-type laminated TFT. Further, the gate 2〇5 is set to move a with respect to the source region, and the non-polar region 202b has a predetermined overlapping portion d1, thereby preventing In the electrode 205 and the source region 202a and the overlap portion μ of the pupil region 2, the parasitic capacitance generated in the gate region is excessively increased. (See Patent Document 2 below.) 94667.doc 1248683 [Patent Literature i] #开200 ii 〇2584 (refer to FIG. 1 and paragraphs 0009 to 0013 in the special opening) [Patent Document 2] Patent No. 275919 [Summary of the Invention] However, in a flat panel display using a TFT as a driving element The organic EL display is a display in which a self-luminous type element (organic anal element) is arranged, and has many excellent features such as color reproducibility, wide viewing angle, high-speed responsiveness, high contrast, etc., and is used for the organic EL. The organic anal component of the display is current driven Therefore, the pixel transistor to be driven is preferably a polycrystalline germanium tft using a polysilicon having excellent current driving capability. For this, in the above-mentioned laminated TFT, the active layer and the source and the gate are polycrystalline. In the conventional polycrystalline germanium TFT manufacturing process, as described above, the amorphous germanium film is irradiated with a laser beam to be melted and recrystallized to form a polycrystalline germanium film. According to this method, not only the crystallization process needs to be increased, but also the characteristics of the thin film transistor are deviated due to the deviation of the laser energy. In addition, especially in the formation of the source and the drain, ion doping is performed. The device and the ion implantation device are used to implant impurities, and the impurities are activated by thermal annealing or lamp annealing, etc. However, the so-called fourth generation of the substrate having a maximum substrate size of about 730 X 920 mm 2 can be applied to the limits of such devices. The substrate is extremely difficult to carry out further enlargement of the device, and has become a cause of hindering the enlargement of the display. In view of the above, it is an object of the present invention to provide a thin film. The method for producing a transistor and the thin film transistor formed by the method can form a thin film electrode which is fast in operation speed and can increase driving current and small difference in characteristics by using a polycrystalline semiconductor thin film in a lesser process 94667.doc 1248683 The first method for producing a thin film transistor of the present invention for achieving the object is characterized by the following steps. First, the reactivity of the reaction energy using a plurality of dissimilar gases is used. In the thermal CVD method, a source and a drain layer formed of an impurity-containing polycrystalline semiconductor thin film are formed on a substrate, and then a source region and a drain region are formed by patterning the source and drain layers. Thereafter, an active layer formed of a polycrystalline semiconductor thin film is formed in a state in which the source region and the drain region are covered by a reactive thermal CVD method using a reverse reaction of a plurality of different gases. Further, after the gate insulating film is formed on the upper portion of the active layer, the gate electrode is formed so as to overlap both ends of the source region and the drain region in a specific state via the gate insulating film and the active layer. . Further, the second manufacturing method is characterized by the following steps. First, a gate is formed on the substrate, and this is covered with a gate insulating film. Next, an active layer formed of a polycrystalline semiconductor thin film is formed on the gate insulating film by a reactive thermal cv〇 method using the reaction energy of a plurality of different gases. Thereafter, a source and a ruthenium layer formed of a polycrystalline semiconductor thin film containing impurities are formed on the active layer by a reactive thermal CVD method using the reaction energy of a plurality of different gases. Then, by patterning the source and drain layers, the source regions are formed such that the respective end portions are overlapped and disposed on the both ends of the gate via the gate insulating film and the active layer in a specific state. Bungee area. According to the first manufacturing method and the second manufacturing method, the active layer and the source and the drain layer are formed by reactive thermal CVD, and the process of crystallizing the semi-conductive 94667.doc 1248683 film is not required. Thus, a laminated thin film transistor in which these layers formed of a semiconductor thin film having a crystal structure in advance is laminated can be obtained. Therefore, by omitting the crystallization step, the active layer and the source and drain layers are formed of a crystalline semiconductor thin film, whereby a laminated thin film electricity having a faster operation speed than when an amorphous semiconductor thin film is used can be obtained. Crystal. Further, by omitting the crystallization step, it is not necessary to worry about various variations due to the crystallization step, so that the characteristics can be made uniform. Further, since the crystalline semiconductor thin film into which the impurity has been introduced is formed as the source and the drain layer, it is not necessary to carry out the step of introducing the impurity after the film formation. Further, in particular, according to the first manufacturing method, a top gate type thin film transistor can be obtained, and according to the second manufacturing method, a bottom gate type thin film transistor can be obtained. These thin film electromorphic systems are arranged such that the two sleeves of the gate are overlapped with the end portions of the source region and the drain region, respectively, via the gate insulating film and the active layer. Therefore, each of the gate-source regions and the gate-drain regions is in a state in which the active layer is sandwiched. Therefore, in the state of the thin film transistor 〇N, the portion of the active layer to be sandwiched is modulated by the electric field to have a low resistance, and the ON current is increased. Furthermore, the present invention is also a thin film semiconductor device obtained by the first manufacturing method and the second manufacturing method described above, and the active layer, the source region, and the non-polar region are reactive with a reaction energy of a plurality of different gases. A polycrystalline semiconductor thin film formed by a thermal Cvd method. Further, it is characterized in that the both end portions of the gate electrode and the end portions of the source region and the drain region are overlapped and arranged in a specific state via the gate insulating film and the active layer ′. As described in the above I, according to the method for producing a thin film transistor of the present invention, the active layer and the source and the drain layer are formed by a reactive thermal CVD method by using 94667.doc 1248683, and the process of crystallizing the semiconductor film is not required. And a process of adding a heterogeneous layer to the source and the drain layer, and using a polycrystalline semiconductor film having a high speed of operation, a laminated thin film electric power which can increase the ON current (that is, the drive current becomes large) can be obtained. Crystal. As a result, not only the manufacturing process can be simplified, but also the manufacturing cost can be reduced, and a thin film transistor in which the difference in crystallization is eliminated can be obtained. Further, as described above, by omitting the crystallization step and the impurity addition step, it is possible to form a thin film transistor having uniform characteristics for a large substrate, and to increase the size of the TF device having the thin film transistor. In addition, according to the thin film transistor of the present invention, the source and the drain layer and the active layer are formed by the polycrystalline semiconductor thin film obtained by the reactive thermal Cvd method, so that the operating speed of the laminated thin film transistor can be improved. The drive current can be increased by providing a specified overlap between the source region and the drain region and the gate. [Embodiment]
<處理裝置〉<Processing device〉
2、3乃介以搬運室4而連通， 安又1固處理室2、3。此等處理室 使得處理室2與處理室3間具有 94667.doc •10- 1248683 能夠使基板w被搬運時不暴露於大氣的構造。此外，處理 室2、3具有能夠藉由以反應性CVD來成膜的構造，特別為 · 處理室2也具有能以電漿CVD來成膜的構造。 > 此等處理室2、3設有在此省略圖示的減壓手段（例如渦輪 分子泵：TMP)及自動壓力控制手段（APC)，使得内部保持 在所需的固定壓力。 此外，各處理室2、3内設有：下部電極5，其係兼作為基 板固定手段；及上部電極6，其係兼作為與下部電極做相對 _ 配置的氣體擴散手段。並且，特別在處理室2中之下部電極 馨 5與上部電極6之間連接有高頻電源（RF)7。此外，在兼作為 基板固定手段的各下部電極5設有加熱手段8。加熱手段8例 如為執行電氣性加熱的加熱器，可使固定於下部電極5上之 基板W維持在200°C至600°C。 另一方面，兼作為氣體擴散手段的上部電極6連接有將複 數種氣體供應至處理室2内的氣體供應手段9。此氣體供應 手段9上，依成膜所需的氣體的種類而連接有複數條的供應 ® 管線（省略圖示），例如矽烷（SiH4)、氨（ΝΗ3)、一氧化二氮 · (N20)、乙矽烷（Si2H6)、氟（F2)、四氟化鍺（GeF4)、膦（PH3)、 乙烷（B2H6)、胂（AsH3)、氮（N2)、氧（02)、氦（He)、氬（Αι〇、 氫（H2)等之成膜氣體（原料氣體及稀釋氣體）G以各自的比 夤 例分別被供應至處理室2、3内。此外，各氣體供應手段9設 有質量式流量控制器（MFC)9a，對處理室2、3内的氣體供應 量個別地進行調整。 並且，上述的高頻電源（RF)7、加熱手段8的電源（加熱電 94667.doc -11 - 1248683 源）、及質量式流量控制器如連接有用以對此等進行控制的 可程式控制器10。 彖 在上述構造的處理裝置丨中，例如在成膜出氮化矽膜及氧‘ 化矽膜等之絕緣膜時，乃由氣體供應手段9將siH4、NH3、 N20、02等之成膜氣體G導入處理室2内，藉由高頻電源 (RF)7在下部電極5與上部電極6之間施加高頻波。藉此，·固 足在下邵電極5上的基板貿上會電漿CVD成膜出此等的絕 緣膜。 此外，在成膜出矽薄膜等之半導體薄膜時，乃由氣體供讀 應手段9將Si2H6、F2、Ar等之成膜氣體G導入處理室2、3 内，不在下部電極5與上部電極6間施加高頻波，而將下部 電極5加熱至約45(TC。藉此，利用原料氣體本身具有的化 學反應性而使原料氣體激勵、分解，在被固定於下部電極5 上且被加熱的基板W上，反應性熱CVD成膜出多晶矽膜。 再者’在成膜出N型摻雜石夕薄膜時，乃將Si2jj6、F2、Ar、 PH3作為成·膜氣體G導入處理室2、3内。另一方面，在成膜穩 出P型摻雜矽薄膜時，則將si2H6、F2、Ar、B2H6作為成膜籲 氣體G而導入處理室2、3内。藉此，可反應性熱CVD成膜出 含有各雜質的多晶碎膜。 上述般的Si2H6-F2類之反應性熱CVD成膜為一種藉由氧 化還元反應的成膜，以2丑6被172氧化而產生Si。作為依此反 · 應系統得到的膜，可得到不含氫的具有1〇至1〇〇 nm左右晶 粒直徑之多晶狀態之結晶性的膜。此外，作為雜質的p、B 等之原子在成膜時會藉由導入Si的晶格位置而被自我活 94667.doc -12- 1248683 化，因此’無需進行活化退火等而在成膜的同時得到低電 阻的N型或P型的多晶碎膜。 - 並且’此等的成膜工序，藉由切換由氣體供應手段9供應v 之成膜氣體G的氣體種類，可連續性地在相同的處理室2、3 内實施。此外，此一連串的處理工序係藉由可程式控制器 10來控制。 以下，說明使用上述處理裝置1進行的薄膜電晶體之製造 方法的實施方式。 馨 第一實施方式 圖2至圖4的剖面工序圖為用以說明第一實施方式的薄膜 電晶體之製造方法的圖。在此，將利用此等圖式來說明作 為薄膜半導體裝置的頂閘極型積層TFT的製造方法，並且， 進一步說明使用此的顯示裝置之製造方法。 首先’如圖2(a)所示，備妥絕緣性的基板21。此基板21 可適用例如旭玻璃社製的AN635、AN100、康寧（corning) 公司製的 Codel737、Eagle2000等。 看 並且，以電漿CVD法或LPCVD法等之成膜方法，在此基❿ 板上’作為緩衝層依序以約5〇 nm至400 nm的膜厚成膜出氮 化矽（SiNx)膜22及氧化矽（SiOx)膜23。 上述之後，以反應性熱CVD法，在氧化矽膜23上，成膜 出含有η型（或p型）雜質的多晶石夕或多晶石夕鍺所形成的源極 暨汲極層24。此源極暨汲極層24可為單層膜或為含有雜質 之多晶矽及含有雜質之多晶矽鍺的積層膜，成膜成1〇至2〇〇 nm的膜厚，並以1〇〇 nm的膜厚為佳。 94667.doc -13- 1248683 例如，以反應性熱CVD法成膜出由η型的多晶矽形成的源 極暨汲極層24時，基板溫度保持在450至600°C。接著，作 β 為成膜氣體使用乙矽烷（Si2H6)、氟（F2)，作為雜質氣體使 、 用膦（PH3)，作為稀釋氣體則使用氦（He)、氮（N2)、氬（At*)、 氪（K〇等之非活性氣體或氫氣（H2)。氣體流量方面，例如設 定成乙矽烷（Si2H6)為 20 seem，氟（F2)為 0.8 seem，膦（ΡΗ3) 為1 seem，作為稀釋氣體將氦（He)設定成1000至4000 seem，並將氣體壓力保持在約600 Pa。藉此，Si2H6與F2產馨 生熱化學反應，以0.2 nm/秒左右的反應速度堆積出η型的多 纏 晶矽。薄膜堆積的同時會產生結晶化，因此，雜質的活化 也會同時進行。 此外，以反應性熱CVD法成膜出由ρ型多晶矽形成的源極 暨汲極層24時，作為成膜氣體，將以乙硼烷（Β2Η6)來取代 上述的膦（ΡΗ3)來作為雜質氣體。 此外，以反應性熱CVD法成膜出η型或ρ型的多晶矽鍺所 形成之源極暨汲極層24時，，則以四氟化鍺（GeF4)來取代 € 氟。此時，藉由乙矽烷（Si2H6)與四氟化鍺（GeF4)的流量 # 比，可得到具有各種矽-鍺組成比的η型或ρ型的多晶矽鍺 薄膜。 如上所述，在形成含有雜質的多晶性之源極暨汲極層24 後，對此源極暨汲極層施以圖案化而形成源極區域24a、及 沒極區域24b。 接著，如圖2(b)所示，以被覆在源極區域24a、及汲極區 域24b上的狀態，利用反應性熱CVD法，成膜出不含雜質的 94667.doc -14- 1248683 多晶矽或多晶矽鍺所形成的活性層25。此活性層25的膜厚 約20至l00nm，並以成膜成4〇nm的膜厚為佳。此成膜乃依· 以圖2(a)說明之成膜條件中去除雜質氣體的條件來實施。此· 外，為了避免雜質的交叉污染，乃以與上述的含有雜質之 多晶性之源極暨汲極層（24)之形成時不同的處理室來進行 成膜處理。 之後，藉由對此活性層25施以圖案化，使端部成為重疊 在兩侧的源極區域24a、及汲極區域24b的端部上的島狀。_ 接著，如圖2(c)所示，將基板1移至可進行電漿CVD成膜 _ 的處理室，以10至200 nm的膜厚成膜出由氧化矽（81〇乂）形 成之閘極絕緣膜26，並以成膜成10〇 nm的膜厚為佳。 接著，如圖2(d)所示，在被圖案化的活性層25上，介以 間極絶緣膜26而形成閘極27。此時，首先，以5〇至250 nm 的膜厚成膜出妲（Ta)、鉬（Mo)、鎢（W)、鉻（Cr)、銅（Cu)或 此等之合金所形成的導電膜，接著，對此導電膜施以圖案 化而形成問極27。 特別在於此閘極27的兩端會被圖案化成介以閘極絕緣膜籲 26及被圖案化的活性層25，重疊在源極區域24a、及汲極區 域24b的端部上的形狀。 如圖3的平面圖所示，介以上述般的活性層25之閘極電極 27與源極區域24a間及與汲極區域24b的重疊部分dl、d2具 有平面的重疊邵分。此等的重疊部分dl、d2的大小（寬度及 面積）為了減少寄生電容乃以較小為佳，然而，受限於光刻 工序的容許誤差精度，將分別設定成適當的值，例如設定 94667.doc -15- 1248683 成約0.5至1.0 μιη的範圍。此外，源極區域24a及汲極區域24b 與閘極27的兩端部的重疊部分dl、d2，基於減少例如閘極· 27與源極區域24a間、及閘極27與汲極區域24b之間的寄生，， 電容的目的，也可分別設定成適當的值。此外，此等之重 疊部分dl、d2，也可僅為閘極27與源極24a間及閘極27與汲 極24b間之至少一方即可。 如上所述，在形成頂閘極型的積層TFT 28後，如圖4(e) 所示，以被覆TFT 28的狀態，利用電漿CVD法，連續形成_ 氧化矽膜3 1及其上邵之含有氫原子的氮化矽膜32作為層間 _ 絕緣膜。此層間絕緣膜係成膜成2〇〇至4〇〇 nm的膜厚。此 外，成膜後，在氮氣（N2)環境中，以350至4〇(rc進行丨小時 左右的氫化退火。 在此之後，更進一步地如圖4(f)所示般地，在氮化碎膜32 及氧化矽膜31上形成連接孔，濺鍍鋁_矽等之配線用電極， 隨後藉由施以圖案化，形成連接於源極區域24a、及汲極區 域24b的配線電極3 3。 · 接著，塗上丙晞類有機樹脂、有機s〇G等約i μιη而形成修 平坦化絕緣膜34。隨後，在平坦化絕緣膜34上形成可達到 1配線電極33的連接孔34a，以埋入此連接孔34a内的狀 態，以濺鍍成膜出Ah Cr、M〇等成為陽極之電極材料膜。 接著，藉由對此電極材料膜進行圖案化，形成像素電極35。 接著，以約220 C在N2中進行3〇分鐘的退火後，在其上依 序積層出電洞輸送層36、發光層37、及電子輸送層38，並 在此上部形成起作用為透明導電性之陰極的共通電極39。 94667.doc -16- 1248683 藉此’可得到在像素電極35所構成的陽極與由共通電極39 所構成的陰極之間夾持由電洞輸送層36、發光層37、及電 子輸送層38積層的有機層而成的有機el元件40。 上述之後，在此雖省略圖示，以被覆有機EL元件40的狀 悲’在基板上形成緩衝層，並更進一步地以夾持有機EL元 件40的狀態，將對向玻璃基板貼合在基板1上，完成顯示裝 置。此顯示裝置為由基板1相對側的透明電極39側（對向玻 璃基板側）取出有機EL元件40的發光光線的頂部發光構造。 此外，顯示裝置並不限於此種頂部發光構造，藉由使像 素電極35由透明導電性材料來形成，也可採用由基板丨側取 出有機EL元件40之發光光線的底部發光構造。此外，藉由 變更電洞輸送層36、發光層37、及電子輸送層38等所形成 之有機層的積層狀態，也可使像素電極35成為陰極，使共 通電極39成為陽極。 依上述的製造方法，在形成薄膜TFT 28時，如以圖2(a)、 圖2 (b )所做的說明，乃利用反應性熱c v D法來形成源極暨沒 極層24及活性層25。據此，無需特別實施使半導體薄膜結 晶化的工序’便可得到以預先具有結晶性構造之半導體薄 膜形成之此等層來積層而成的薄膜電晶體。因此，不僅可 省略結晶化的工序，藉由使源極暨汲極層24及活性層25以 結晶性的半導體薄膜來構成’可得到比利用非晶質之半導 體薄膜時動作速度更快的積層型的薄膜TFT 28。 此外’藉由肩略結晶化的工序，由於沒有必要擔心起因 於結晶化工序的各種誤差，因此，有助於特性的均勻性。 94667.doc -17- 1248683 再者，作為源極暨汲極層24，由於會成膜出預先添加雜質 的結晶性半導體薄膜，因此，沒有必要在成膜後進行添加 雜質的工序。 並且，特別如圖2(d)及圖3所做的說明，藉由在源極區域 24a及汲極區域24b的端部上使閘極27的兩端部重疊配置， 閘極27與源極區域24a間、及閘極27與汲極區域24b間分別 成為活性層25部分被夾持的狀態。因此，薄膜TFT 28在ON 狀態時，會受施加於閘極27之電壓所造成之電場的影響， 閘極27的下部的活性層25部分會形成反轉層。藉此，源極 區域24a端及汲極區域24b端的電阻會下降，積層TFT 28的 ON電流增大，即有助於驅動電流的增大。此外，積層TFT 在OFF狀態時，閘極27與源極區域24a間、及閘極27與汲極 區域24b間被夾持的活性層25部分會空乏化而成為高電 阻。因此，可減少OFF電流。 依上述的結果，適於對利用動作速度快的多晶性半導體 膜來增大驅動電流的有機EL元件進行驅動的積層TFT 28能 以較少的工序數目來形成，並且，可得到結晶化所致之偏 差被消？耳的薄膜電晶體。此外，如上所述，由於能夠省略 結晶化工序及雜質添加工序，因此，可對大型基板形成特 性均勻的薄膜電晶體，實現具有此薄膜電晶體之顯示裝置 的大型化。 此外，藉由上述的顯示裝置的大型化，可將選擇開關整 合於週邊電路，大幅減少外接電路的連接端子，有助於實 現高可靠性、低成本、低耗電量的大型顯示裝置。並且， 94667.doc -18- 1248683 可T來Sb對對角線尺寸超過4〇叶的大型電致發光裝置等之 大型顯示器以高生產性、低成本地進行製造的優點。本實 施例雖以利用有機EL元件的顯示裝置為例做說明，然而， 本發明並不限於使用有機EL元件的顯示裝置，可應用於使 用操機EL元件、液晶顯示元件等之顯示裝置整體。 第二實施方式 圖5至圖6的剖面工序圖為用以說明第二實施方式之薄膜 電晶體之製造方法之圖。在此，依據此等圖式說明作為薄 膜半導體裝置之底閘極型之積層TFT的製造方法，並且，進 一步地說明利用此的顯示裝置之製造方法。 首先，如圖5(a)所示，在如同第一實施方式的絕緣性的基 板51上以約50至250 nm的膜厚成膜出由鈕、鉬（M〇)、 鎢（W)、絡（Cr)、銅（Cu)或此等之合金所形成的導電膜，接 著，對此導電膜施以圖案化而形成閘極52。 接著，如圖5(b)所示，以電漿CVD法、常壓CVD法、減歷： CVD法等連續成膜出氮化矽膜53a(膜厚3〇至5〇 nm)及氧化 矽膜53b(膜厚約50至200 nm)，形成由此等積層膜形成的閘 極絕緣膜5 3。 接著，以反應性熱CVD法，成膜出不含雜質的多晶矽或 多晶矽鍺所形成的活性層54。此活性層54以約20至100 nm 的膜厚來成膜。此活性層54的成膜係以與第一實施方式中 以圖2(b)說明之活性層（25)的成膜相同的方式進行。惟，為 了调整在此形成的積層TFT的Vth，也可在成膜氣體中添加 微量的雜質氣體。此外，被添加的雜質氣體乃依在此形成 94667.doc •19- 1248683 之積層TFT的導電型來選擇。接著，再度利用電漿CVD法， 將氧化矽薄膜55以100至200 nm的膜厚成膜於活性層54上。’ 隨後，如圖5(c)所示，藉由實施將閘極52作為光罩使用的 - 背面曝光，在氧化矽膜55上形成光阻圖案56。 接著，如圖5(d)所示，藉由以光阻圖案56作為光罩而對 氧化矽薄膜55進行蝕刻，形成由氧化矽形成之蝕刻阻止層 55a。之後，去除光阻圖案56。 隨後，如圖6(e)所示，以被覆在蚀刻阻止層55a上的狀態，_ 在不含雜質之多晶性半導體所形成的活性層54上，成膜出 ❿ 含有η型（或p型）雜質的多晶矽或多晶矽鍺所形成的源極暨 汲極層5 6。此源極暨汲極層5 6的成膜係以與第一實施方式 中以圖2(a)說明之源極暨汲極層（24)相同的方式進行。 上述之後，如圖6(f)所示，將源極暨汲極層56及活性層54 圖案蝕刻成跨過閘極52的相同島狀。接著，使含有雜質的 多晶性的源極暨汲極層56在閘極52上分離，形成由此源極 暨汲極層56形成的源極區域56a、及汲極區域56b。 ® 此時，如圖7的平面圖所示，使源極區域56a及汲極區域 5 6b的端部介以活性層54相對於閘極52具有平面性的重疊 部分d 1、d2般地，在餘刻阻止層5 5 a上使源極暨沒極層5 6分 ♦ 離。在此，重疊部分dl、d2不含蝕刻阻止層55a被夾置的部 分。此外，此重疊部分dl、d2係以與第一實施方式相同的 方式設定。 此外，圖6(f)的剖面圖所示之2個構成積層TFT 60的源極 區域56&及汲極區域56b也可為被圖案化成連續帶狀的多種 94667.doc -20- 1248683 閘極構造，也可使在此省略圖示的3處以上之閘極52以多重 閘極構造來構成。在此情況中，也可使構成多重閘極的所-有的閘極52與源極區域56a間、及閘極52與汲極區域56b間 _ 中至少僅一者具有重疊部分。 依上述，可形成底閘極型的積層TFT 60。 接著，如圖6(g)所示，以被覆積層TFT 60的狀態，利用 電漿CVD法，以100至400 nm的膜厚成膜出氧化矽膜57，並 更進一步地以100至400 nm的膜厚連續成膜出含有氫的氮⑩ 化矽膜58。在此之後，在氮氣（N2)環境中以350至400°C進 _ 行1小時的氫化退火。 接著，圖6(h)所示的工程乃以與第一實施方式中以圖4(f) 說明的相同方式實施，形成連接於源極區域56a、及汲極區 域56b的配線電極33、平坦化絕緣膜34、及連接於配線電極 33的有機EL元件40，並貼合對向玻璃電極而完成顯示裝置。 即使為上述的製造方法，如同上述的第一實施方式，在 形成薄膜TFT 60時，如以圖5(b)及圖6(e)所做之說明，有利 _ 用反應性熱CVD法來形成源極暨汲極層56及活性層54，此 _ 外，如依圖6(f)及圖7所做之說明，藉由使源極區域56a及汲 極區域56b的端部重疊配置在閘極52的兩端部上，如同第一 豢 實施方式，使得閘極52與源極區域56a間、及閘極52與沒極 區域56b間分別成為有活性層54部分被夾持的狀態。 ’ 因此，適於對利用動作速度快的多晶性半導體膜來增大 驅動電流的有機EL元件進行驅動的積層TFT 60能以較少的 工序數目來形成’並且’可得到結晶化所致之偏差減少的 94667.doc -21 - 1248683 積層TFT 60。此外，如上所述，由於可省格結晶化工序及 雜質添加工序，可對大型基板形成特性均勻的積層TFT - 60，實現具有此積層TFT 60之顯示裝置的大型化。 . 此外，底閘極型的積層TFT的構造方面，即使為在圖8所 示之源極區域56a及汲極區域56b的正上方設置配線電極81 的構造，也適用本發明之製造方法。在此情況中，在形成 以圖6(e)說明之源極暨汲極層56後，在此源極暨汲極層％ 的上部設置配線電極的形成層，在此之後，藉由同時對源 _ 極暨汲極層56及配線電極之形成層進行圖案化，可減少光 _ 罩片數。惟在此情況中，在源極暨汲極層5 6的上部形成配 線電極的形成層之前，也可以氫電漿、氧電漿、水蒸氣退 火等來減少構成源極暨汲極層56之多晶矽中的缺陷位準。 即使為上述等積層TFT 82的製造方法，如同第二實施方 式，藉由利用反應性熱CVD法來形成源極暨汲極層56及活 性層54，並使源極區域56a及汲極區域5讣的端部重疊於閘 極52的兩端般地被配置形成，可得到與第二實施方式相同 鲁 的效果，並且相車交於第二實施方式，可得到*罩片數減少# 的效果。 【圖式簡單說明】 圖1為使用實施方式之製造方法的成膜裝置之構造圖。 、圖2(a)、（b)、（c)、及（d)為說明第一實施方式之製造方法· 之剖面工序圖（之一）。 圖3為說明第一實施方式中之閘極與源極區域、波極區域 的重疊部分之平面圖。 94667.doc -22- 1248683 圖4(e)、及（f)為說明第一實施方式之製造方法之剖面工 序圖（之二）。 . 圖5(a)、（b)、（c)、及（d)為說明第二實施方式之製造方法， 之剖面工序圖（之一）。 圖6(e)、（f)、（g)、及⑻為說明第二實施方式之製造方法 之剖面工序圖（之二）。 圖7為說明第二實施方式中之閘極與源極區域、汲極區域 的重疊部分之平面圖。 φ 圖8為說明第二實施方式之底閘極型之積層TFT^々其他構鲁 造之圖。 圖9為說明以往之底閘極型之積層TFT之製造之圖。 圖10為說明以往之頂閘極型之積層打丁之製造之圖。 【主要元件符號說明】2, 3 is connected by the transfer chamber 4, and the 1 and 3 solid processing chambers 2, 3. These processing chambers have a configuration in which the processing chamber 2 and the processing chamber 3 have 94667.doc •10-1248683 which can prevent the substrate w from being exposed to the atmosphere when being transported. Further, the processing chambers 2, 3 have a structure capable of being formed by reactive CVD, and in particular, the processing chamber 2 has a structure capable of being formed by plasma CVD. > These processing chambers 2, 3 are provided with a pressure reducing means (for example, a turbo molecular pump: TMP) and an automatic pressure control means (APC) (not shown) so that the inside is maintained at a desired fixed pressure. Further, in each of the processing chambers 2, 3, a lower electrode 5 serving as a substrate fixing means and a top electrode 6 serving as a gas diffusion means disposed opposite to the lower electrode are provided. Further, in particular, a high frequency power source (RF) 7 is connected between the lower electrode 5 and the upper electrode 6 in the processing chamber 2. Further, a heating means 8 is provided for each of the lower electrodes 5 which also serves as a substrate fixing means. The heating means 8 is, for example, a heater for performing electrical heating, and the substrate W fixed to the lower electrode 5 can be maintained at 200 ° C to 600 ° C. On the other hand, the upper electrode 6 serving as a gas diffusion means is connected to a gas supply means 9 for supplying a plurality of kinds of gases into the processing chamber 2. In the gas supply means 9, a plurality of supply lines (not shown) are connected depending on the type of gas required for film formation, such as decane (SiH4), ammonia (ΝΗ3), and nitrous oxide (N20). , ethane oxide (Si2H6), fluorine (F2), germanium tetrafluoride (GeF4), phosphine (PH3), ethane (B2H6), bismuth (AsH3), nitrogen (N2), oxygen (02), helium (He) The film forming gas (raw material gas and diluent gas) G such as argon (H2) or the like is supplied to the processing chambers 2 and 3 in the respective specific examples. Further, each gas supply means 9 is provided with mass. The flow rate controller (MFC) 9a individually adjusts the gas supply amount in the processing chambers 2, 3. Further, the above-mentioned high-frequency power source (RF) 7 and the power source of the heating means 8 (heating power 94667.doc -11 - 1248683 source), and mass flow controller, such as a programmable controller 10 connected to control the same. 彖 In the processing device of the above configuration, for example, a tantalum nitride film and oxygen are formed. In the case of an insulating film such as a ruthenium film, the film forming gas G such as siH4, NH3, N20, and 02 is introduced into the processing by the gas supply means 9. 2, a high-frequency wave is applied between the lower electrode 5 and the upper electrode 6 by the high-frequency power source (RF) 7. Thereby, the substrate on the lower-slung electrode 5 is formed by plasma CVD. In addition, when a semiconductor thin film such as a tantalum film is formed, the film forming gas G such as Si2H6, F2, Ar or the like is introduced into the processing chambers 2 and 3 by the gas supply and reading means 9, and the lower electrode 5 is not A high frequency wave is applied between the upper electrodes 6, and the lower electrode 5 is heated to about 45 (TC. Thereby, the material gas is excited and decomposed by the chemical reactivity of the material gas itself, and is fixed to the lower electrode 5 and heated. On the substrate W, a polycrystalline tantalum film is formed by reactive thermal CVD. In addition, when an N-type doped film is formed, Si2jj6, F2, Ar, and PH3 are introduced into the processing chamber 2 as a film gas G. On the other hand, when a P-type doped germanium film is formed by film formation, si2H6, F2, Ar, and B2H6 are introduced into the processing chambers 2 and 3 as a film forming gas G. The thermal CVD film forms a polycrystalline film containing various impurities. The above-mentioned Si2H6-F2 type reactive thermal CVD is formed. The film is a film formed by oxidation-reduction reaction, and is oxidized by 172 at 2 ugly 6 to produce Si. As a film obtained by the reaction system, a crystal having a hydrogen content of about 1 〇 to 1 〇〇 nm can be obtained. A film having a crystallinity in a polycrystalline state of a particle diameter. Further, atoms such as p, B, etc., which are impurities, are self-lived by the introduction of the lattice position of Si at the time of film formation, so that they are self-lived, 94667.doc -12-1248683 'N-type or P-type polycrystalline fracture film having low resistance is obtained at the same time as film formation without performing activation annealing or the like. Further, the film forming process of these can be carried out continuously in the same processing chambers 2, 3 by switching the gas type of the film forming gas G supplied with v by the gas supply means 9. Moreover, the series of processing operations are controlled by the programmable controller 10. Hereinafter, an embodiment of a method of manufacturing a thin film transistor using the above-described processing apparatus 1 will be described. First Embodiment The cross-sectional process diagrams of Figs. 2 to 4 are views for explaining the method of manufacturing the thin film transistor of the first embodiment. Here, a method of manufacturing the top gate type laminated TFT as a thin film semiconductor device will be described using these drawings, and a method of manufacturing the display device using the same will be further described. First, as shown in Fig. 2(a), an insulating substrate 21 is prepared. For the substrate 21, for example, AN635, AN100 manufactured by Asahi Glass Co., Ltd., Codel 737 manufactured by Corning Co., Ltd., Eagle 2000, or the like can be applied. Further, a film formation method such as plasma CVD or LPCVD is used to form a tantalum nitride (SiNx) film on the substrate as a buffer layer with a film thickness of about 5 Å to 400 nm. 22 and yttrium oxide (SiOx) film 23. After the above, a source and a drain layer 24 formed of a polycrystalline or polycrystalline stone containing an n-type (or p-type) impurity is formed on the hafnium oxide film 23 by a reactive thermal CVD method. . The source and drain layer 24 may be a single layer film or a laminated film containing polycrystalline germanium containing impurities and polycrystalline germanium containing impurities, and formed into a film thickness of 1 〇 to 2 〇〇 nm, and is 1 〇〇 nm. The film thickness is preferred. 94667.doc -13- 1248683 For example, when a source and a drain layer 24 formed of an n-type polycrystalline germanium is formed by a reactive thermal CVD method, the substrate temperature is maintained at 450 to 600 °C. Next, β is hexane oxide (Si2H6) or fluorine (F2) as a film forming gas, phosphine (PH3) is used as an impurity gas, and helium (He), nitrogen (N2), or argon (At*) is used as a diluent gas. ), 氪 (K〇, etc., an inert gas or hydrogen (H2). For gas flow, for example, acetylene (Si2H6) is 20 seem, fluorine (F2) is 0.8 seem, and phosphine (ΡΗ3) is 1 seem. The diluent gas sets helium (He) to 1000 to 4000 seem and maintains the gas pressure at about 600 Pa. Thereby, Si2H6 and F2 produce a thermogenic reaction, and the n-type is deposited at a reaction rate of about 0.2 nm/sec. The entanglement of the film. Crystallization occurs at the same time as the film is deposited. Therefore, the activation of the impurities is simultaneously performed. Further, when the source and the drain layer 24 formed of the p-type polysilicon are formed by the reactive thermal CVD method, As a film forming gas, the above phosphine (ΡΗ3) is replaced by diborane (Β2Η6) as an impurity gas. Further, a source formed by forming an n-type or p-type polycrystalline germanium by reactive thermal CVD is used. When the pole and the bungee layer are at 24 o'clock, the fluorine is replaced by germanium tetrafluoride (GeF4). By comparing the flow rate of oxirane (Si2H6) with germanium tetrafluoride (GeF4), an n-type or p-type polycrystalline germanium film having various 矽-锗 composition ratios can be obtained. As described above, in the formation of impurities containing impurities After the source of the polycrystal and the drain layer 24, the source and drain layers are patterned to form a source region 24a and a gate region 24b. Next, as shown in Fig. 2(b), In the state of being coated on the source region 24a and the drain region 24b, an active layer 25 formed of a polysiloxane or polycrystalline germanium containing no impurity 94647.doc -14-1248683 is formed by a reactive thermal CVD method. The film thickness of the layer 25 is about 20 to 100 nm, and it is preferable to form a film thickness of 4 Å. This film formation is carried out under the conditions of removing impurity gases in the film formation conditions described in Fig. 2(a). In addition, in order to avoid cross-contamination of impurities, a film formation process is performed in a processing chamber different from that of the above-described polycrystalline source and drain layer (24) containing impurities. The active layer 25 is patterned such that the ends are the source regions 24a and the drain regions 24b which are overlapped on both sides. Island shape. _ Next, as shown in Fig. 2(c), the substrate 1 is moved to a processing chamber where plasma CVD film formation is performed, and a film thickness of 10 to 200 nm is formed to form a film of yttrium oxide ( 81〇乂) The gate insulating film 26 is formed, and it is preferable to form a film thickness of 10 〇 nm. Next, as shown in FIG. 2(d), on the patterned active layer 25, The gate electrode 27 is formed by the pole insulating film 26. At this time, first, a film thickness of 5 Å to 250 nm is formed to form tantalum (Ta), molybdenum (Mo), tungsten (W), chromium (Cr), and copper (Cu). Or a conductive film formed of such an alloy, and then the conductive film is patterned to form a question electrode 27. In particular, the both ends of the gate electrode 27 are patterned to have a shape in which the gate insulating film 26 and the patterned active layer 25 are superposed on the end portions of the source region 24a and the drain region 24b. As shown in the plan view of Fig. 3, the overlapping portions d1 and d2 between the gate electrode 27 and the source region 24a and the gate region 24b of the active layer 25 described above have a plane overlapping. The size (width and area) of the overlapping portions dl and d2 is preferably small in order to reduce the parasitic capacitance. However, it is limited to the tolerance value of the photolithography process, and is set to an appropriate value, for example, 94667. .doc -15- 1248683 is in the range of about 0.5 to 1.0 μηη. Further, the overlapping portions d1 and d2 of the source region 24a and the drain region 24b and the both end portions of the gate 27 are based on, for example, reducing between the gate 27 and the source region 24a, and between the gate 27 and the gate region 24b. The parasitic, the purpose of the capacitor can also be set to an appropriate value. Further, the overlapping portions dl and d2 may be at least one of the gate 27 and the source 24a and between the gate 27 and the drain 24b. As described above, after the gate electrode 28 of the top gate type is formed, as shown in FIG. 4(e), the yttrium oxide film 3 1 and the upper portion thereof are continuously formed by the plasma CVD method in a state where the TFT 28 is covered. The tantalum nitride film 32 containing a hydrogen atom serves as an interlayer-insulating film. This interlayer insulating film is formed into a film thickness of 2 〇〇 to 4 〇〇 nm. Further, after film formation, hydrogenation annealing is performed at 350 to 4 Torr in a nitrogen (N2) atmosphere for about 丨 hours. After that, further, as shown in Fig. 4 (f), nitridation is performed. A connection hole is formed in the chip 32 and the yttrium oxide film 31, and an electrode for wiring such as aluminum ruthenium or the like is sputtered, and then patterned to form a wiring electrode 3 3 connected to the source region 24a and the drain region 24b. Then, a flattening insulating film 34 is formed by applying a propylene-based organic resin, an organic s-G, etc., and then a connection hole 34a which can reach the wiring electrode 33 is formed on the planarization insulating film 34, The electrode material film which becomes an anode such as Ah Cr or M 〇 is deposited by sputtering in a state of being buried in the connection hole 34a. Next, the electrode material film is patterned to form the pixel electrode 35. Next, After annealing for about 3 minutes in N2 at about 220 C, the hole transport layer 36, the light-emitting layer 37, and the electron transport layer 38 are sequentially laminated thereon, and the upper portion is formed to function as a transparent conductive layer. The common electrode of the cathode 39. 94667.doc -16- 1248683 The organic EL element 40 in which the organic layer formed by the hole transport layer 36, the light-emitting layer 37, and the electron transport layer 38 is sandwiched between the anode formed of the electrode 35 and the cathode formed of the common electrode 39. Though the illustration is omitted, the buffer layer is formed on the substrate by coating the organic EL element 40, and the opposite glass substrate is bonded to the substrate 1 in a state in which the organic EL element 40 is sandwiched. The display device is a top emission structure in which the illuminating light of the organic EL element 40 is taken out from the side of the transparent electrode 39 on the side opposite to the substrate 1 (opposite to the glass substrate side). Further, the display device is not limited to such a top emission. In the structure, the pixel electrode 35 is formed of a transparent conductive material, and a bottom emission structure in which the light emitted from the organic EL element 40 is taken out from the side of the substrate can be used. Further, the hole transport layer 36 and the light-emitting layer 37 are changed. And the laminated state of the organic layer formed by the electron transport layer 38 or the like, the pixel electrode 35 may be a cathode, and the common electrode 39 may be an anode. According to the above manufacturing method, a thin film is formed. In the case of the TFT 28, as described with reference to FIGS. 2(a) and 2(b), the source and the gate layer 24 and the active layer 25 are formed by the reactive heat cv D method. The step of crystallizing the semiconductor thin film can be obtained by laminating these layers formed of a semiconductor thin film having a crystal structure in advance. Therefore, not only the crystallization step but also the source cum can be omitted. The gate layer 24 and the active layer 25 are formed of a crystalline semiconductor thin film. A laminated thin film TFT 28 having a faster operation speed than that of an amorphous semiconductor thin film can be obtained. Since there is no need to worry about various errors due to the crystallization step, it contributes to the uniformity of characteristics. Further, as the source and the drain layer 24, since a crystalline semiconductor thin film to which impurities are previously added is formed, it is not necessary to carry out a step of adding impurities after film formation. Further, in particular, as shown in FIGS. 2(d) and 3, the gate 27 and the source are overlapped by the end portions of the gate electrode 27 at the end portions of the source region 24a and the drain region 24b. Between the regions 24a and between the gate 27 and the drain region 24b, the active layer 25 is partially sandwiched. Therefore, when the thin film TFT 28 is in the ON state, it is affected by the electric field caused by the voltage applied to the gate electrode 27, and the active layer 25 portion of the lower portion of the gate electrode 27 forms an inversion layer. Thereby, the resistance of the source region 24a end and the drain region 24b end is lowered, and the ON current of the laminated TFT 28 is increased, which contributes to an increase in the drive current. Further, when the build-up TFT is in the OFF state, the portion of the active layer 25 sandwiched between the gate 27 and the source region 24a and between the gate 27 and the drain region 24b is depleted and becomes high resistance. Therefore, the OFF current can be reduced. According to the above results, the laminated TFT 28 which is suitable for driving the organic EL element which increases the driving current by the polycrystalline semiconductor film having a high operating speed can be formed with a small number of steps, and a crystallization can be obtained. The deviation is eliminated? Thin film transistor of the ear. Further, as described above, since the crystallization step and the impurity addition step can be omitted, a thin film transistor having uniform properties can be formed on the large substrate, and the display device having the thin film transistor can be enlarged. Further, by increasing the size of the display device described above, the selection switch can be integrated into the peripheral circuit, and the connection terminals of the external circuit can be greatly reduced, contributing to a large-sized display device with high reliability, low cost, and low power consumption. Further, 94667.doc -18-1248683 has the advantage that Sb can be manufactured with high productivity and low cost for large displays such as large electroluminescent devices having a diagonal size exceeding 4 〇. In the present embodiment, a display device using an organic EL element will be described as an example. However, the present invention is not limited to a display device using an organic EL element, and can be applied to a display device using a device such as an EL device or a liquid crystal display device as a whole. [Second Embodiment] The cross-sectional process diagrams of Figs. 5 to 6 are views for explaining the method of manufacturing the thin film transistor of the second embodiment. Here, a method of manufacturing a gate electrode of a bottom gate type as a thin film semiconductor device will be described based on the drawings, and a method of manufacturing the display device using the same will be further described. First, as shown in FIG. 5(a), a button, molybdenum (M〇), tungsten (W), and a film thickness of about 50 to 250 nm are formed on the insulating substrate 51 as in the first embodiment. A conductive film formed of a complex (Cr), copper (Cu) or the like, and then patterned to form a gate 52. Next, as shown in FIG. 5(b), a tantalum nitride film 53a (film thickness: 3 Å to 5 Å) and cerium oxide are continuously formed by a plasma CVD method, a normal pressure CVD method, or a CVD method. The film 53b (having a film thickness of about 50 to 200 nm) forms a gate insulating film 53 formed by such an interlayer film. Next, an active layer 54 formed of polycrystalline germanium or polycrystalline germanium containing no impurities is formed by a reactive thermal CVD method. This active layer 54 is formed into a film with a film thickness of about 20 to 100 nm. The film formation of the active layer 54 is carried out in the same manner as the film formation of the active layer (25) illustrated in Fig. 2(b) in the first embodiment. However, in order to adjust the Vth of the build-up TFT formed here, a small amount of impurity gas may be added to the film formation gas. Further, the impurity gas to be added is selected in accordance with the conductivity type of the laminated TFT in which 94667.doc • 19-1248683 is formed. Next, the ruthenium oxide film 55 is again deposited on the active layer 54 by a plasma CVD method at a film thickness of 100 to 200 nm. Then, as shown in Fig. 5(c), a photoresist pattern 56 is formed on the hafnium oxide film 55 by performing back exposure using the gate 52 as a photomask. Next, as shown in Fig. 5 (d), the ruthenium oxide film 55 is etched by using the photoresist pattern 56 as a mask to form an etch stop layer 55a made of ruthenium oxide. Thereafter, the photoresist pattern 56 is removed. Subsequently, as shown in Fig. 6(e), on the active layer 54 formed of the polycrystalline semiconductor containing no impurity, in a state of being coated on the etching stopper layer 55a, the film is formed to contain n-type (or p). The source and the drain layer formed by the polycrystalline germanium or polycrystalline germanium of the impurity. The film formation of this source and drain layer 56 is carried out in the same manner as the source and drain layers (24) illustrated in Fig. 2(a) in the first embodiment. After that, as shown in FIG. 6(f), the source and drain layers 56 and the active layer 54 are patterned into the same island shape across the gate 52. Next, the polycrystalline source and drain layer 56 containing impurities is separated on the gate 52 to form a source region 56a and a drain region 56b formed by the source and drain layers 56. ® At this time, as shown in the plan view of FIG. 7, the ends of the source region 56a and the drain region 56b are interposed such that the active layer 54 has a planar overlapping portion d1, d2 with respect to the gate 52. The remaining layer 5 5 a causes the source and the immersion layer to be separated by 5 6 . Here, the overlapping portions d1, d2 do not contain the portion where the etching stopper layer 55a is sandwiched. Further, the overlapping portions d1 and d2 are set in the same manner as in the first embodiment. Further, the two source regions 56 & and the drain region 56b constituting the laminated TFT 60 shown in the cross-sectional view of Fig. 6(f) may be a plurality of 94667.doc -20-1248683 gates patterned into a continuous strip shape. The three or more gates 52, which are omitted here, may be configured in a multiple gate structure. In this case, at least one of the gate 52 and the source region 56a constituting the plurality of gates, and at least one of the gate 52 and the gate region 56b may have overlapping portions. According to the above, the bottom gate type multilayer TFT 60 can be formed. Next, as shown in FIG. 6(g), the ruthenium oxide film 57 is formed by a plasma CVD method at a film thickness of 100 to 400 nm in a state where the build-up TFT 60 is coated, and further 100 to 400 nm. The film thickness of the film is continuously formed into a nitrogen-containing ruthenium film 58 containing hydrogen. After that, hydrogenation annealing was performed at 350 to 400 ° C for 1 hour in a nitrogen (N 2 ) atmosphere. Next, the process shown in FIG. 6(h) is performed in the same manner as described in FIG. 4(f) in the first embodiment, and the wiring electrodes 33 connected to the source region 56a and the drain region 56b are formed and flattened. The insulating film 34 and the organic EL element 40 connected to the wiring electrode 33 are bonded to the glass electrode to complete the display device. Even in the above-described manufacturing method, as in the first embodiment described above, when the thin film TFT 60 is formed, as described with reference to FIGS. 5(b) and 6(e), it is advantageous to form by reactive thermal CVD. The source and drain layers 56 and the active layer 54 are disposed in the gate by overlapping the ends of the source region 56a and the drain region 56b as illustrated in FIG. 6(f) and FIG. At both end portions of the pole 52, as in the first embodiment, the active layer 54 is partially sandwiched between the gate 52 and the source region 56a, and between the gate 52 and the gate region 56b. Therefore, the laminated TFT 60 which is suitable for driving the organic EL element which increases the drive current by the polycrystalline semiconductor film having a fast operation speed can be formed by a small number of processes and can be obtained by crystallization. The deviation is reduced by 94667.doc -21 - 1248683 laminated TFT 60. In addition, as described above, the layered TFT-60 having uniform characteristics can be formed on a large substrate by the crystallization process and the impurity addition step, and the size of the display device having the laminated TFT 60 can be increased. Further, in the structure of the bottom gate type multilayer TFT, the manufacturing method of the present invention is applied even if the wiring electrode 81 is provided directly above the source region 56a and the drain region 56b shown in Fig. 8. In this case, after the source and drain layers 56 described in FIG. 6(e) are formed, a formation layer of the wiring electrodes is provided on the upper portion of the source and drain layers, and thereafter, by simultaneously The formation of the source _ pole and the drain layer 56 and the wiring electrodes is patterned to reduce the number of light shi covers. However, in this case, before forming the formation layer of the wiring electrode on the upper portion of the source and the drain layer 56, the source electrode and the drain layer 56 may be reduced by hydrogen plasma, oxygen plasma, water vapor annealing or the like. Defect level in polysilicon. Even in the second embodiment, the source and drain layers 56 and the active layer 54 are formed by the reactive thermal CVD method, and the source region 56a and the drain region 5 are formed. The end portion of the crucible is disposed so as to overlap the both ends of the gate 52, and the same effect as that of the second embodiment can be obtained, and the effect of the number of the cover sheets is reduced by the second embodiment. . BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a structural view of a film forming apparatus using a manufacturing method of an embodiment. 2(a), (b), (c), and (d) are cross-sectional process drawings (1) for explaining the manufacturing method of the first embodiment. Fig. 3 is a plan view showing the overlapping portion of the gate, the source region, and the wave region in the first embodiment. 94667.doc -22- 1248683 Figures 4(e) and (f) are cross-sectional process diagrams (Part 2) illustrating the manufacturing method of the first embodiment. 5(a), (b), (c), and (d) are cross-sectional process drawings (1) for explaining the manufacturing method of the second embodiment. 6(e), (f), (g), and (8) are cross-sectional process drawings (part 2) for explaining the manufacturing method of the second embodiment. Fig. 7 is a plan view showing the overlapping portion of the gate, the source region, and the drain region in the second embodiment. φ Fig. 8 is a view showing the other structure of the bottom gate type of the gate electrode of the second embodiment. Fig. 9 is a view for explaining the manufacture of a conventional bottom gate type multilayer TFT. Fig. 10 is a view for explaining the manufacture of a conventional top gate type laminated layer. [Main component symbol description]
1 處理裝置 2、3 處理室 4 搬運室 5 下部電極 6 上部電極 7 高頻電源（RF) 8 加熱手段 9 氣體供應手段 9a 質量式流量控制器（MFC) 10 可程式控制器 21 基板 94667.doc -23- 1248683 22 氮化矽（SiNx)膜 23 氧化矽（SiOx)膜 24 源極暨汲極層 24a 源極區域 24b 沒極區域 25 活性層 26 閘極絕緣膜 27 閘極 28 積層TFT 31 氧化矽膜 32 氮化矽膜 33 配線電極 34 平坦化絕緣膜 34a 連接孔 35 像素電極 36 電洞輸送層 37 發光層 38 電子輸送層 39 共通電極、透明電極 40 有機EL元件 51 基板 52 閘極 53 閘極絕緣膜 53a 氮化矽膜 94667.doc - 24 - 1248683 53b 氧化矽膜 54 活性層 55 氧化矽薄膜 55a 雀虫刻阻止層 56 光阻圖案一圖5(e) 56 源極暨沒極層一圖6(e) 5 6a 源極區域 56b 沒極區域 57 氧化矽膜 58 氮化矽膜 60 底閘極型的積層TFT 81 配線電極 103 閘極絕緣膜 104 半導體薄膜 104a 活性層 105 保護圖案 106 半導體薄膜 106a 源極區域 106b 汲極區域 107 金屬膜 107a、107b 電極 201 基板 202 多晶矽膜 202a 源極區域 94667.doc -25- 1248683 202b 203 203a 204 205 dl、d2 沒極區域 非晶碎膜 活性層 閘極絕緣膜 閘極 重疊部 94667.doc -26-1 Processing unit 2, 3 Processing chamber 4 Transfer chamber 5 Lower electrode 6 Upper electrode 7 High-frequency power supply (RF) 8 Heating means 9 Gas supply means 9a Mass flow controller (MFC) 10 Programmable controller 21 Substrate 94667.doc -23- 1248683 22 Cerium nitride (SiNx) film 23 Cerium oxide (SiOx) film 24 Source and drain layer 24a Source region 24b Nom region 25 Active layer 26 Gate insulating film 27 Gate 28 Stacked TFT 31 Oxidation Tantalum film 32 tantalum nitride film 33 wiring electrode 34 planarization insulating film 34a connection hole 35 pixel electrode 36 hole transport layer 37 light-emitting layer 38 electron transport layer 39 common electrode, transparent electrode 40 organic EL element 51 substrate 52 gate 53 gate Pole insulating film 53a tantalum nitride film 94667.doc - 24 - 1248683 53b hafnium oxide film 54 active layer 55 hafnium oxide film 55a finch engraving layer 56 photoresist pattern Figure 5 (e) 56 source and immersion layer Fig. 6(e) 5 6a Source region 56b Nom region 57 Cerium oxide film 58 Tantalum nitride film 60 Bottom gate type laminated TFT 81 Wiring electrode 103 Gate insulating film 104 Semiconductor film 104a Active Layer 105 protection pattern 106 semiconductor film 106a source region 106b drain region 107 metal film 107a, 107b electrode 201 substrate 202 polysilicon film 202a source region 94667.doc -25- 1248683 202b 203 203a 204 205 dl, d2 non-polar region non Crystalline film active layer gate insulating film gate overlap portion 94667.doc -26-