JP2005051149A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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Abstract
【解決手段】半導体装置の製造方法は、集積回路12を有する半導体基板10の第1の面20からの凹部内に導電部30を形成すること、半導体基板10を第2の面21からの一部を除去して薄くして、導電部30を第1の面20から第2の面21に貫通させること、半導体基板10を切断して、複数の個片を得ること、を含む。導電部の形成工程終了後のいずれかの工程で、導電部を介して、半導体基板の電気的特性を検査する。
【選択図】図3
Description
(b)前記半導体基板を第2の面からの一部を除去して薄くして、前記導電部を前記第1の面から前記第2の面に貫通させること、
(c)前記半導体基板を切断して、複数の個片を得ること、
を含み、
前記(a)工程終了後、前記導電部を介して、前記半導体基板の電気的特性を検査する。本発明によれば、導電部の形成工程終了後に、半導体基板の電気的特性を検査するので、検査工程によって導電部の形成工程の信頼性を低下させることがない。したがって、半導体装置の製造方法の信頼性の向上を図ることができる。
(2)この半導体装置の製造方法において、
前記(a)工程で、前記導電部を、最表部にロウ材層を有するように形成してもよい。これによれば、ロウ材層は、柔らかいので、例えば検査ツールの端子を滑らせずに確実に接触保持させることができる。また、仮に最表部に端子の痕跡が形成されても、その後の工程でロウ材層の少なくとも一部を溶融させることによって、その痕跡をなくすことができる。
(3)この半導体装置の製造方法において、
前記(a)工程で、前記導電部を、最表部に金層を有するように形成してもよい。これによれば、金層は、柔らかいので、例えば検査ツールの端子を滑らせずに確実に接触保持させることができる。また、仮に最表部に端子の痕跡が形成されても、その後の工程で金層の少なくとも一部を溶融させることによって、その痕跡をなくすことができる。
(4)この半導体装置の製造方法において、
前記(b)工程前に、前記検査工程を行ってもよい。これによれば、薄型化工程後の半導体基板を検査する場合に比べて、半導体基板の取り扱いが容易になる。詳しくは、半導体基板の損傷を防止することができる。
(5)この半導体装置の製造方法において、
前記(c)工程は、
(c1)前記半導体基板に補強部材を設けること、
(c2)前記検査工程を行うこと、
(c3)前記半導体基板を切断すること、
を含んでもよい。これによれば、半導体基板は補強部材によって補強されているので、半導体基板の取り扱いが容易になる。詳しくは、半導体基板の損傷を防止することができる。
(6)この半導体装置の製造方法において、
前記補強部材は、前記半導体基板の前記第1及び第2の面のいずれか一方の面側に貼り付けられるテープと、前記テープの支持体と、を有してもよい。
(7)本発明に係る半導体装置の製造方法は、上記方法によって製造されてなる複数の半導体装置をスタックすることをさらに含む。
36…最表部、 50…半導体装置、 60…補強部材、 62…テープ、
64…支持体
Claims (7)
- (a)集積回路を有する半導体基板の第1の面からの凹部内に導電部を形成すること、
(b)前記半導体基板を第2の面からの一部を除去して薄くして、前記導電部を前記第1の面から前記第2の面に貫通させること、
(c)前記半導体基板を切断して、複数の個片を得ること、
を含み、
前記(a)工程終了後、前記導電部を介して、前記半導体基板の電気的特性を検査する半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(a)工程で、前記導電部を、最表部にロウ材層を有するように形成する半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(a)工程で、前記導電部を、最表部に金層を有するように形成する半導体装置の製造方法。 - 請求項1から請求項3のいずれかに記載の半導体装置の製造方法において、
前記(b)工程前に、前記検査工程を行う半導体装置の製造方法。 - 請求項1から請求項4のいずれかに記載の半導体装置の製造方法において、
前記(c)工程は、
(c1)前記半導体基板に補強部材を設けること、
(c2)前記検査工程を行うこと、
(c3)前記半導体基板を切断すること、
を含む半導体装置の製造方法。 - 請求項1から請求項5のいずれかに記載の半導体装置の製造方法において、
前記補強部材は、前記半導体基板の前記第1及び第2の面のいずれか一方の面側に貼り付けられるテープと、前記テープの支持体と、を有する半導体装置の製造方法。 - 請求項1から請求項6のいずれかに記載の方法によって製造されてなる複数の半導体装置をスタックすることをさらに含む半導体装置の製造方法。
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