JP2004531054A - 高速cmos電子機器及び高速アナログ回路のための緩和シリコンゲルマニウムプラットフォーム - Google Patents
高速cmos電子機器及び高速アナログ回路のための緩和シリコンゲルマニウムプラットフォーム Download PDFInfo
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- JP2004531054A JP2004531054A JP2002570310A JP2002570310A JP2004531054A JP 2004531054 A JP2004531054 A JP 2004531054A JP 2002570310 A JP2002570310 A JP 2002570310A JP 2002570310 A JP2002570310 A JP 2002570310A JP 2004531054 A JP2004531054 A JP 2004531054A
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- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 105
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- 238000000034 method Methods 0.000 claims abstract description 102
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 229910052681 coesite Inorganic materials 0.000 claims description 2
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- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/802—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors
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- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US27311201P | 2001-03-02 | 2001-03-02 | |
US09/906,545 US6677192B1 (en) | 2001-03-02 | 2001-07-16 | Method of fabricating a relaxed silicon germanium platform having planarizing for high speed CMOS electronics and high speed analog circuits |
US09/906,551 US6724008B2 (en) | 2001-03-02 | 2001-07-16 | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
PCT/US2002/003681 WO2002071495A1 (fr) | 2001-03-02 | 2002-02-07 | Plate-forme de silicium germanium relachee pour electronique cmos tres rapide et circuits analogiques tres rapides |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004531054A true JP2004531054A (ja) | 2004-10-07 |
JP2004531054A5 JP2004531054A5 (fr) | 2005-12-22 |
Family
ID=27402529
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002570310A Pending JP2004531054A (ja) | 2001-03-02 | 2002-02-07 | 高速cmos電子機器及び高速アナログ回路のための緩和シリコンゲルマニウムプラットフォーム |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP1364411A1 (fr) |
JP (1) | JP2004531054A (fr) |
WO (1) | WO2002071495A1 (fr) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007515808A (ja) * | 2003-12-23 | 2007-06-14 | インテル・コーポレーション | Cmos用歪トランジスタの集積化 |
JP2008512868A (ja) * | 2004-09-13 | 2008-04-24 | インターナショナル・ビジネス・マシーンズ・コーポレーション | ウェハ接合技術を用いて欠陥のない高Ge含有量のSiGeオン・インシュレータ(SGOI)基板を製造する方法 |
JP2017112339A (ja) * | 2015-12-18 | 2017-06-22 | 株式会社Sumco | シリコンゲルマニウムエピタキシャルウェーハの製造方法およびシリコンゲルマニウムエピタキシャルウェーハ |
Families Citing this family (20)
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US6750130B1 (en) | 2000-01-20 | 2004-06-15 | Amberwave Systems Corporation | Heterointegration of materials using deposition and bonding |
US6602613B1 (en) | 2000-01-20 | 2003-08-05 | Amberwave Systems Corporation | Heterointegration of materials using deposition and bonding |
US6969875B2 (en) | 2000-05-26 | 2005-11-29 | Amberwave Systems Corporation | Buried channel strained silicon FET using a supply layer created through ion implantation |
JP2004507084A (ja) | 2000-08-16 | 2004-03-04 | マサチューセッツ インスティテュート オブ テクノロジー | グレーデッドエピタキシャル成長を用いた半導体品の製造プロセス |
US6900094B2 (en) | 2001-06-14 | 2005-05-31 | Amberwave Systems Corporation | Method of selective removal of SiGe alloys |
US6916727B2 (en) | 2001-06-21 | 2005-07-12 | Massachusetts Institute Of Technology | Enhancement of P-type metal-oxide-semiconductor field effect transistors |
WO2003015142A2 (fr) | 2001-08-06 | 2003-02-20 | Massachusetts Institute Of Technology | Formation de couches planes soumises a des contraintes |
US7138649B2 (en) | 2001-08-09 | 2006-11-21 | Amberwave Systems Corporation | Dual-channel CMOS transistors with differentially strained channels |
WO2003028106A2 (fr) | 2001-09-24 | 2003-04-03 | Amberwave Systems Corporation | Circuits r.f. comprenant des transistors a couches de materiau contraintes |
US20030227057A1 (en) | 2002-06-07 | 2003-12-11 | Lochtefeld Anthony J. | Strained-semiconductor-on-insulator device structures |
AU2003238963A1 (en) | 2002-06-07 | 2003-12-22 | Amberwave Systems Corporation | Semiconductor devices having strained dual channel layers |
US6982474B2 (en) | 2002-06-25 | 2006-01-03 | Amberwave Systems Corporation | Reacted conductive gate electrodes |
FR2844634B1 (fr) * | 2002-09-18 | 2005-05-27 | Soitec Silicon On Insulator | Formation d'une couche utile relaxee a partir d'une plaquette sans couche tampon |
US6787864B2 (en) * | 2002-09-30 | 2004-09-07 | Advanced Micro Devices, Inc. | Mosfets incorporating nickel germanosilicided gate and methods for their formation |
DE10318283A1 (de) | 2003-04-22 | 2004-11-25 | Forschungszentrum Jülich GmbH | Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur |
DE10318284A1 (de) * | 2003-04-22 | 2004-11-25 | Forschungszentrum Jülich GmbH | Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur |
US7812340B2 (en) | 2003-06-13 | 2010-10-12 | International Business Machines Corporation | Strained-silicon-on-insulator single-and double-gate MOSFET and method for forming the same |
US7329923B2 (en) * | 2003-06-17 | 2008-02-12 | International Business Machines Corporation | High-performance CMOS devices on hybrid crystal oriented substrates |
US6831350B1 (en) * | 2003-10-02 | 2004-12-14 | Freescale Semiconductor, Inc. | Semiconductor structure with different lattice constant materials and method for forming the same |
US20050132952A1 (en) * | 2003-12-17 | 2005-06-23 | Michael Ward | Semiconductor alloy with low surface roughness, and method of making the same |
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US5442205A (en) * | 1991-04-24 | 1995-08-15 | At&T Corp. | Semiconductor heterostructure devices with strained semiconductor layers |
US5534713A (en) * | 1994-05-20 | 1996-07-09 | International Business Machines Corporation | Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers |
US5891769A (en) * | 1997-04-07 | 1999-04-06 | Motorola, Inc. | Method for forming a semiconductor device having a heteroepitaxial layer |
US5906951A (en) * | 1997-04-30 | 1999-05-25 | International Business Machines Corporation | Strained Si/SiGe layers on insulator |
FR2773177B1 (fr) * | 1997-12-29 | 2000-03-17 | France Telecom | Procede d'obtention d'une couche de germanium ou silicium monocristallin sur un substrat de silicium ou germanium monocristallin, respectivement, et produits multicouches obtenus |
EP1070341A1 (fr) * | 1998-04-10 | 2001-01-24 | Massachusetts Institute Of Technology | Systeme de couche d'arret d'attaque chimique au silicium et au germanium |
EP1252659A1 (fr) * | 2000-01-20 | 2002-10-30 | Amberwave Systems Corporation | Transistors a effet de champ, a semi-conducteur metal-oxyde, et a couche de silicium contrainte |
EP1295319A2 (fr) * | 2000-06-22 | 2003-03-26 | Massachusetts Institute Of Technology | Systeme de couche d'arret de gravure |
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2002
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- 2002-02-07 JP JP2002570310A patent/JP2004531054A/ja active Pending
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007515808A (ja) * | 2003-12-23 | 2007-06-14 | インテル・コーポレーション | Cmos用歪トランジスタの集積化 |
JP2008512868A (ja) * | 2004-09-13 | 2008-04-24 | インターナショナル・ビジネス・マシーンズ・コーポレーション | ウェハ接合技術を用いて欠陥のない高Ge含有量のSiGeオン・インシュレータ(SGOI)基板を製造する方法 |
JP2017112339A (ja) * | 2015-12-18 | 2017-06-22 | 株式会社Sumco | シリコンゲルマニウムエピタキシャルウェーハの製造方法およびシリコンゲルマニウムエピタキシャルウェーハ |
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EP1364411A1 (fr) | 2003-11-26 |
WO2002071495A1 (fr) | 2002-09-12 |
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