EP1364411A1 - Plate-forme de silicium germanium relachee pour electronique cmos tres rapide et circuits analogiques tres rapides - Google Patents

Plate-forme de silicium germanium relachee pour electronique cmos tres rapide et circuits analogiques tres rapides

Info

Publication number
EP1364411A1
EP1364411A1 EP02709406A EP02709406A EP1364411A1 EP 1364411 A1 EP1364411 A1 EP 1364411A1 EP 02709406 A EP02709406 A EP 02709406A EP 02709406 A EP02709406 A EP 02709406A EP 1364411 A1 EP1364411 A1 EP 1364411A1
Authority
EP
European Patent Office
Prior art keywords
layer
sige
relaxed
siι
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02709406A
Other languages
German (de)
English (en)
Inventor
Eugene A. Fitzgerald
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Amber Wave Systems Inc
Original Assignee
Amber Wave Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/906,545 external-priority patent/US6677192B1/en
Priority claimed from US09/906,551 external-priority patent/US6724008B2/en
Application filed by Amber Wave Systems Inc filed Critical Amber Wave Systems Inc
Publication of EP1364411A1 publication Critical patent/EP1364411A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/802—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/0251—Graded layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
    • H01L29/66916—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with a PN heterojunction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs

Definitions

  • the invention relates to the field of relaxed SiGe platforms for high speed CMOS electronics and high speed analog circuits.
  • Si CMOS as a platform for digital integrated circuits has progressed predictably through the industry roadmap. The progress is created through device miniaturization, leading to higher performance, greater reliability, and lower cost. However, new bottlenecks in data flow are appearing as the interconnection hierarchy is expanded. Although digital integrated circuits have progressed at unprecedented rates, analog circuitry has hardly progressed at all. Furthermore, it appears that in the near future, serious economic and technological issues will confront the progress of digital integrated circuits. The digital and communication chip markets need an enhancement to Si CMOS and the maturing roadmap. One promising candidate material that improves digital integrated circuit technology and introduces new analog integrated circuit possibilities is relaxed SiGe material on Si substrates.
  • Relaxed SiGe alloys on Si can have thin layers of Si deposited on them, creating tension in the thin Si layers.
  • Tensile Si layers have many advantageous properties for the basic device in integrated circuits, the metal-oxide field effect transistor (MOSFET).
  • MOSFET metal-oxide field effect transistor
  • First, placing Si in tension increases the mobility of electrons moving parallel to the surface of the wafer, thus increasing the frequency of operation of the MOSFET and the associated circuit.
  • the band offset between the relaxed SiGe and the tensile Si will confine electrons in the Si layer. Therefore, in an electron channel device (n-channel), the channel can be removed from the surface or 'buried'. This ability to spatially separate the charge carriers from scattering centers such as ionized impurities and the 'rough' oxide interface enables the production of low noise, high performance analog devices and circuits.
  • Novel device structures in research laboratories have been fabricated on early, primitive versions of the relaxed buffer.
  • relaxed Si, surface channel nMOSFETs have been created that show enhancements of over 60% in intrinsic g m wifh electron mobility increases of over 75% (Rim et al, IEDM 98 Tech. Dig. p. 707). Strained
  • Si buried channel devices demonstrating high transconductance and high mobility have also been fabricated (U. Konig, MRS Symposium Proceedings 533, 3 (1998)).
  • these devices possess a variety of problems with respect to commercialization.
  • the material quality that is generally available is insufficient for practical utilization, since the surface of SiGe on Si becomes very rough as the material is relaxed via dislocation introduction.
  • These dislocations are essential in the growth of relaxed SiGe layers on Si since they compensate for the stress induced by the lattice mismatch between the materials.
  • researchers have tried to intrinsically control the surface morphology through epitaxial growth, but since the stress fields from the misfit dislocations affect the growth front, no intrinsic epitaxial solution is possible.
  • the invention describes a method of planarization and regrowth that allows all devices on relaxed SiGe to possess a significantly flatter surface. This reduction in surface roughness increases the yield for fine-line lithography, thus enabling the manufacture of strained Si devices.
  • Exemplary embodiments of the invention describe structures and methods to fabricate advanced strained-layer Si devices, and structures and methods to create circuits based on a multiplicity of devices, all fabricated from the same starting material platform. Starting from the same material platform is key to minimizing cost as well as to allowing as many circuit topologies to be built on this platform as possible.
  • the invention provides a material platform of planarized relaxed SiGe with regrown device layers.
  • the planarization and regrowth strategy allows device layers to have minimal surface roughness as compared to strategies in which device layers are grown without planarization.
  • This planarized and regrown platform is a host for strained Si devices that can possess optimal characteristics for both digital and analog circuits. Structures and processes are described that allow for the fabrication of high performance digital logic or analog circuits, but the same structure can be used to host a combination of digital and analog circuits, forming a single system-on-chip.
  • a semiconductor structure including a planarized relaxed Si ⁇ - x Ge x layer on a substrate; and a device heterostructure deposited on said planarized relaxed Si ⁇ - x Ge x layer including at least one strained layer.
  • FIG. 1 is a schematic block diagram of a structure including a relaxed SiGe layer epitaxially grown on a Si substrate;
  • FIG. 2 is a schematic block diagram of an exemplary structure showing that the origin of the Crosshatch pattern is the stress fields from injected misfit dislocations;
  • FIG. 3 is a table showing surface roughness data for relaxed SiGe buffers produced by dislocation injection via graded SiGe layers on Si substrates;
  • FIGs. 4A-4D show an exemplary process flow and resulting platform structure in accordance with the invention
  • FIGs. 5A-5D are schematic diagrams of the corresponding process flow and layer structure for a surface channel FET platform in accordance with the invention.
  • FIGs. 6A-6D are schematic diagrams of the corresponding process flow and layer structure for a buried channel FET platform in accordance with the invention
  • FIGs. 7A-7D are schematic diagrams of a process flow for a surface channel MOSFET in accordance with the invention
  • FIGs. 8A and 8B are schematic block diagrams of surface channel devices with protective layers
  • FIGs. 9A and 9B are schematic block diagrams of surface channel devices with Si layers on Ge-rich layers for use in suicide formation
  • FIGs. 10 is schematic diagram of a buried channel MOSFET after device isolation in accordance with the invention.
  • FIG. 11 is a schematic flow of the process, for any heterostructure FET device deposited on relaxed SiGe, in accordance with the invention
  • FIGs. 12A-12D are schematic diagrams of a process flow in the case of forming the surface channel MOSFET in the top strained Si layer in accordance with the invention
  • FIGs. 13A-13D are schematicdiagrams of a process flow in the case of forming the surface channel MOSFET in the buried strained Si layer in accordance with the invention
  • FIGs. 14A and 14B are schematic diagrams of surface and buried channel devices with Sii- y Ge y channels on a relaxed Si ⁇ . z Ge z layer.
  • FIG. 1 is a schematic block diagram of a structure 100 including a relaxed SiGe layer epitaxially grown on a Si substrate 102.
  • a compositionally graded buffer layer 104 is used to accommodate the lattice mismatch between the uniform SiGe layer 106 and the Si substrate.
  • the graded buffer minimizes the number of dislocations reaching the surface and thus provides a method for growing high-quality relaxed SiGe films on Si.
  • Any method of growing a high-quality, relaxed SiGe layer on Si will produce roughness on the surface of the SiGe layer in a well-known Crosshatch pattern.
  • This Crosshatch pattern is typically a few hundred angstroms thickness over distances of microns.
  • the Crosshatch pattern is a mild, undulating surface morphology with respect to the size of the electron or hole. For that reason, it is possible to create individual devices that achieve enhancements over their control Si device counterparts.
  • the origin of the Crosshatch pattern is the stress fields from the injected misfit dislocations. This effect is depicted by the exemplary structure 200 shown in FIG. 2.
  • the dislocations must be introduced in order to accommodate the lattice-mismatch between the SiGe alloy and the Si substrate.
  • the stress fields originate at the dislocations, and are terminated at the surface of the film. However, the termination at the surface creates crystal lattices that vary from place to place on the surface of the wafer. Since growth rate can be correlated to lattice constant size, different thicknesses of deposition occur at different points on the wafer. One may think that thick layer growth beyond the misfit dislocations will smooth the layer of these thickness differences. Unfortunately, the undulations on the surface have a relatively long wavelength; therefore, surface diffusion is typically not great enough to remove the morphology.
  • FIG. 3 is a table that displays surface roughness data for relaxed SiGe buffers produced by dislocation injection via graded SiGe layers on Si substrates. Note that the as-grown Crosshatch pattern for relaxed Sio 8 Ge o 2 buffers creates a typical roughness of approximately 7.9nm. This average roughness increases as the Ge content in the relaxed buffer is increased. Thus, for any SiGe layer that is relaxed through dislocation introduction during growth, the surface roughness is unacceptable for state-of-the-art fabrication facilities. After the process in which the relaxed SiGe is planarized, the average roughness is less than 2nm (typically 0.57nm), and after device layer deposition, the average roughness is 0.77nm with a 1.5 ⁇ m regrowth thickness. Therefore, after the complete structure is fabricated, over one order of magnitude of roughness reduction can be achieved.
  • 2nm typically 0.57nm
  • the average roughness is 0.77nm with a 1.5 ⁇ m regrowth thickness. Therefore, after the complete structure is fabricated, over one order of magnitude of
  • the regrowth device layers can be either greater than or less than the critical thickness of the regrowth layer.
  • thin layers can be deposited without fear of dislocation introduction at the interface.
  • any lattice-mismatch between the film and substrate will introduce misfit dislocations into the regrown heterostructure. These new dislocations can cause additional surface roughness.
  • the lattice-mismatch between the regrowth device layers and relaxed SiGe buffer is too great, the effort of planarizing the relaxed SiGe may be lost since massive dislocation introduction will roughen the surface.
  • the regrowth thickness There are two distinct possibilities with respect to the regrowth thickness and the quality of surface. If the regrowth layers are very thin, then exact lattice matching of the regrowth layer composition and the relaxed buffer composition is not necessary. In this case, the surface roughness will be very low, approximately equal to the post-planarization flatness. However, in many applications for devices, the regrowth layer thickness will be 1 -2 ⁇ m or more. For a 1% difference in Ge concentration between the relaxed SiGe and the regrowth layer, the critical thickness is approximately 0.5 ⁇ m. Thus, if optimal flatness is desired, it is best to keep the regrowth layer below approximately 0.5 ⁇ m unless excellent control of the uniformity of Ge concentration across the wafer is achieved.
  • FIG. 3 shows that less precise matching, i.e., within 2% Ge, results in misfit dislocation introduction and introduction of a new Crosshatch pattern.
  • the lattice mismatch is so small, the average roughness is still very low, approximately 0.77nm. Thus, either lattice-matching or slight mismatch will result in excellent device layer surfaces for processing.
  • the relaxed SiGe alloy with surface roughness may not necessarily be a uniform composition relaxed SiGe layer on a graded composition layer.
  • this material layer structure has been shown to be an early example of high quality relaxed SiGe, there are some disadvantages to this structure.
  • SiGe alloys possess a much worse coefficient of thermal conductivity than pure Si.
  • it may be relatively difficult to guide the heat away from the device areas due to the thick graded composition layer and uniform composition layer.
  • FIGs. 4A-4D show an exemplary process flow and resulting platform structure in accordance with the invention.
  • the structure is produced by first forming a relaxed uniform SiGe alloy 400 via a compositionally graded layer 402 on a Si substrate 404.
  • the SiGe layer 400 is then transferred to a second Si substrate 406 using conventional bonding.
  • the uniform SiGe alloy 400 on the graded layer 402 can be planarized to remove the
  • the graded layer 402 and the original substrate 404 can be removed by a variety of conventional processes. For example, one process is to grind the original Si substrate away and selectively etch to the SiGe, either by a controlled dry or wet etch, or by embedding an etch stop layer. The end result is a relaxed SiGe alloy 400 on Si without the thick graded layer. This structure is more suited for high power applications since the heat can be conducted away from the SiGe layer more efficiently.
  • the bond and substrate removal technique can also be used to produce SiGe on insulator substrates, or SGOI.
  • An SGOI wafer is produced using the same technique shown in FIGs. 4A-4D; however, the second substrate is coated with a Si0 2 layer before bonding.
  • both wafers can be coated with Si0 2 to enable oxide-to-oxide bonding.
  • the resulting structure after substrate removal is a high quality, relaxed SiGe layer on an insulating film. Devices built on this platform can utilize the performance enhancements of both strained Si and the SOI architecture. It will be appreciated that in the scenario where the SiGe layer is transferred to another host substrate, one may still need to planarize before regrowing the device layer structure.
  • the SiGe surface can be too rough for state of the art processing due to the substrate removal technique.
  • the relaxed SiGe is planarized, and the device layers are regrown on top of the high-quality relaxed SiGe surface. Planarization of the surface via mechanical or other physical methods is required to flatten the surface and to achieve CMOS-quality devices.
  • the field effect transistors (FETs) that allow for enhanced digital and analog circuits are very thin, and thus would be removed by the planarization step.
  • FETs field effect transistors
  • FIGs. 5 and 6 show the process sequence and regrowth layers required to create embodiments of surface channel and buried channel FETs, respectively.
  • FIGs. 5A-5D are schematic diagrams of a process flow and resulting layer structure in accordance with the invention.
  • FIG. 5A shows the surface roughness 500, which is typical of a relaxed SiGe alloy 502 on a substrate 504, as an exaggerated wavy surface.
  • the substrate is labeled in a generic way, since the substrate could itself be Si, a relaxed compositionally graded SiGe layer on Si, or another material in which the relaxed SiGe has been transferred through a wafer bonding and removal technique.
  • the relaxed SiGe alloy 502 is planarized (FIG. 5B) to remove the substantial roughness, and then device regrowth layers 506 are epitaxially deposited (FIG. 5C).
  • a strained Si layer 508 of thickness less than 0.1 ⁇ m is then grown on top of the relaxed SiGe 502 with an optional sacrificial layer 510, as shown in FIG. 5D.
  • the strained layer 508 is the layer that will be used as the channel in the final CMOS devices.
  • FIGs. 6A-6D are schematic diagrams of the corresponding process flow and layer structure for a buried channel FET platform in accordance with the invention.
  • the regrowth layers 606 include a lattice matched SiGe layer 602, a strained Si channel layer 608 with a thickness of less than 0.05 ⁇ m, a SiGe separation or spacer layer 612, a Si gate oxidation layer 614, and an optional sacrificial layer 610 used to protect the heterostructure during the initial device processing steps.
  • FIGs. 1-10 A simplified version of the process flow for a surface channel MOSFET in accordance with the invention is shown in FIGs.
  • This surface channel MOSFET contains a relaxed SiGe layer 700 and a strained
  • the device isolation oxide 704, depicted in FIG. 7A, is typically formed first.
  • the SiN layer 706, which is on top of a thin pad oxide layer 708, serves as a hard mask for either local oxidation of silicon (LOCOS) or shallow trench isolation (STI). Both techniques use a thick oxide (relative to device dimensions) to provide a high threshold voltage between devices; however, STI is better suited for sub-quarter-micron technologies.
  • Figure 7B is a schematic of the device area after the gate oxide 716 growth and the shallow-source drain implant.
  • the implant regions 710 are self-aligned by using a poly-Si gate 712 patterned with photoresist 714 as a masking layer.
  • Figure 7D is a schematic of the device after the first level of metal interconnects 726 have been deposited and etched. Since there are limited-thickness layers on top of the entire structure, the removal of surface material during processing becomes more critical than with standard Si. For surface channel devices, the structure that is regrown consists primarily of nearly lattice- matched SiGe, and a thin surface layer of strained Si. Many of the processes that are at the beginning of a Si fabrication sequence strip Si from the surface. If the processing is not carefully controlled, the entire strained Si layer can be removed before the gate oxidation. The resulting device will be a relaxed SiGe channel FET and thus the benefits of a strained Si channel will not be realized.
  • a logical solution to combat Si removal during initial processing is to make the strained Si layer thick enough to compensate for this removal.
  • thick Si layers are not possible for two reasons.
  • the enhanced electrical properties originate from the fact that the Si is strained and thick layers experience strain relief through the introduction of misfit dislocations.
  • the misfit dislocations themselves are undesirable in significant quantity, since they can scatter carriers and increase leakage currents injunctions.
  • FIG. 8A shows a strained Si heterostructure of a relaxed SiGe layer 800 and a strained Si channel layer 802 protected by a surface layer 804 of SiGe.
  • the surface SiGe layer 804 should have a Ge concentration similar to that of the relaxed SiGe layer 800 below, so that the thickness is not limited by critical thickness constraints.
  • the SiGe sacrificial layer is removed instead of the strained Si channel layer.
  • the thickness of the sacrificial layer can either be tuned to equal the removal thickness, or can be made greater than the removal thickness. In the latter case, the excess SiGe can be selectively removed before the gate oxidation step to reveal a clean, strained Si layer at the as grown thickness. If the particular fabrication facility prefers a Si terminated surface, a sacrificial Si layer may be deposited on top of the SiGe sacrificial cap layer.
  • FIG. 8B shows a structure where a layer 806 of Si0 2 and a surface layer 808 of either a poly-crystalline or an amorphous material are used as protective layers.
  • an oxide layer is either grown or deposited after the epitaxial growth of the strained Si layer.
  • a polycrystalline or amorphous layer of Si, SiGe, or Ge is deposited.
  • These semiconductor layers protect the strained-Si layer in the same manner as a SiGe cap during the processing steps before gate oxidation.
  • the poly/amorphous and oxide layers are selectively removed.
  • the sacrificial layers are shown as protection for a surface channel device, the same techniques can be employed in a buried channel heterostructure.
  • FIG. 7C Another way in which conventional Si processing is modified is during the source- drain silicide-germanide formation (FIG. 7C).
  • a metal typically Ti, Co, or Ni
  • the metal reacts with both Si and Ge simultaneously. Since the suicides have much lower free energy than the germanides, there is a tendency to form a suicide while the Ge is expelled. The expelled germanium creates agglomeration and increases the resistance of the contacts. This increase in series resistance offsets the benefits of the extra drive current from the heterostructure, and negates the advantages of the structure.
  • Ti and Ni can form phases in which the Ge is not rejected severely, thus allowing the formation of a good contact. Co is much more problematic.
  • a protective layer(s) at the device epitaxy stage can be applied instead of optimizing the SiGe-metal reaction.
  • the strained Si that will become the surface channel can be coated with a high-Ge-content SiGe alloy (higher Ge content than the initial relaxed SiGe), followed by strained Si.
  • Two approaches are possible using these surface contact layers. Both methods introduce thick Si at the surface and allow the conventional suicide technology to be practiced without encountering the problems with
  • the first approach shown on a surface channel heterostructure 900 in FIG. 9A, uses a Ge-rich layer 906 thin enough that it is substantially strained.
  • the layer 906 is provided on a strained Si channel layer 904 and relaxed SiGe layer 902.
  • the compressive Ge-rich layer 906 acts as a barrier to dislocations entering the strained Si channel 904. This barrier is beneficial since dislocations do not adversely affect the suicide process; thus, their presence in the subsequent Si layer 908 is of no consequence. However, if the dislocations were to penetrate to the channel, there would be adverse effects on the device.
  • a second approach, shown in FIG. 9B, is to allow a Ge-rich layer 910 to intentionally exceed the critical thickness, thereby causing substantial relaxation in the Ge- rich layer.
  • an arbitrarily thick Si layer 912 can be applied on top of the relaxed Ge-rich layer. This layer will contain more defects than the strained channel, but the defects play no role in device operation since this Si is relevant only in the suicide reaction. In both cases, the process is free from the metal-SiGe reaction concerns, since the metal will react with Si-only.
  • Si/SiGe FET heterostructures to achieve enhanced performance is the compatibility with conventional Si techniques. Many of the processes are identical to Si CMOS processing, and once the front-end of the process, i.e., the processing of the Si/SiGe heterostructure, is complete, the entire back-end process is uninfluenced by the fact that Si/SiGe lies below.
  • FIG. 10 is a schematic block diagram of a buried channel MOSFET structure 1000 after the device isolation oxide 1016 has been formed using a SiN mask 1014.
  • the strained channel 1002 on a first SiGe layer 1010 is separated from the surface by the growth of another SiGe layer 1004, followed by another Si layer 1006.
  • This Si layer is needed for the gate oxide 1008 since gate-oxide formation on SiGe produces a very high interface state density, thus creating non-ideal MOSFETs.
  • this Si layer is that if it is too thick, a substantial portion of the Si layer will remain after the gate oxidation. Carriers can populate this residual Si layer, creating a surface channel in parallel with the desired buried channel and leading to deleterious device properties.
  • the surface layer Si must be kept as thin as possible, typically less than 5 ⁇ A and ideally in the range of 5- 15 A.
  • a supply layer implant Another added feature that is necessary for a buried channel device is the supply layer implant.
  • the field experienced in the vertical direction when the device is turned on is strong enough to pull carriers from the buried channel 1002 and force them to populate a Si channel 1006 near the Si/Si0 2 interface 1012, thus destroying any advantage of the buried channel.
  • a supply layer of dopant must be introduced either in the layer 1004 between the buried channel and the top Si layer 1006, or below the buried channel in the underlying SiGe 1010. In this way, the device is forced on with little or no applied voltage, and turned off by applying a voltage (depletion mode device).
  • FIG. 11 is a schematic flow of the process, for any heterostructure FET device deposited on relaxed SiGe, in accordance with the invention.
  • the main process steps are shown in the boxes, and optional steps or comments are shown in the circles.
  • the first three steps (1100,1102,1104) describe the fabrication of the strained silicon heterostructure.
  • the sequence includes production of relaxed SiGe on Si, planarization of the SiGe, and regrowth of the device layers.
  • MOS fabrication begins with device isolation (1 112) using either STI (1 110) or LOCOS (1108).
  • buried channel devices undergo a supply and threshold implant (1114), and any protective layers applied to either a buried or surface channel heterostructure must be selectively removed (1116).
  • the processing sequence after the gate oxidation (1118) is similar to conventional Si CMOS processing. These steps include gate deposition, doping, and definition (1 120), self-aligned shallow source-drain implant (1122), spacer formation (1 124), self-aligned deep source-drain implant (1 126), salicide formation (1128), and pad isolation via metal deposition and etch (1130). The steps requiring significant alteration have been discussed.
  • FIG. 11 One particular advantage of the process of FIG. 11 is that it enables the use of surface channel and buried channel devices on the same platform.
  • FIGs. 12A-12D and FIGs. 13A-13D show a universal substrate layer configuration and a process that leads to the co-habitation of surface and buried channel MOSFETs on the same chip.
  • the universal substrate is one in which both surface channel and buried channel devices can be fabricated.
  • FIGs. 12 and 13 There are two possibilities in fabricating the surface channel device in this sequence, shown in FIGs. 12 and 13.
  • the process flows for combining surface and buried channel are similar to the previous process described in FIG. 7. Therefore, only the critical steps involved in exposing the proper gate areas are shown in FIGs. 12 and 13.
  • FIGs. 12A and 13A depict the same basic heterostructure 1200,1300 for integrating surface channel and buried channel devices.
  • Two strained Si layers are necessary because the buried channel MOSFET requires a surface Si layer to form the gate oxide and a buried Si layer to form the device channel.
  • the figures also show a device isolation region 1210 that separates the buried channel device area 1212,1312 from the surface channel device area 1214,1314.
  • FIG. 12B is a schematic diagram of a surface channel gate oxidation 1216 in the top Si layer 1202.
  • a thicker top Si layer is desired, since after oxidation, a residual strained Si layer must be present to form the channel.
  • FIG. 12B also shows a possible position for the buried channel supply implant 1218, which is usually implanted before the buried channel gate oxide is grown.
  • top Si layer is optimized for the surface channel device, it may be necessary to strip some of the top strained Si in the regions 1220 where buried channel devices are being created, as shown in FIG. 12C. This removal is necessary in order to minimize the surface Si thickness after gate oxide 1222 formation (FIG. 12D), and thus avoid the formation of a parallel device channel.
  • the top strained Si layer can be thin, i.e., designed optimally for the buried channel MOSFET.
  • FIG. 13B the top strained Si and SiGe layers are removed in the region 1312 where the surface channel MOSFETs are formed. Because Si and SiGe have different properties, a range of selective removal techniques can be used, such as wet or dry chemical etching. Selective oxidation can also be used since SiGe oxidizes at much higher rates than Si, especially under wet oxidation conditions.
  • FIG. 13C shows the gate oxidation 1314 of the surface channel device as well as the supply layer implant 1316 for the buried channel device.
  • FIG. 13D shows the position of the buried channel gate oxide 1318. No thinning of the top Si layer is required prior to the oxidation since the epitaxial thickness is optimized for the buried channel device.
  • Another key step in the process is the use of a localized implant to create the supply layer needed in the buried channel device.
  • a localized implant to create the supply layer needed in the buried channel device.
  • MOSFET MOSFET structure
  • when the channel is turned on large vertical fields are present that bring carriers to the surface.
  • the band offset between the Si and SiGe that confines the electrons in the buried strained Si layer is not large enough to prevent carriers from being pulled out of the buried channel.
  • the buried channel MOSFET would appear useless.
  • the MOSFET would become a depletion-mode device, i.e. normally on and requiring bias to turn off the channel.
  • a supply layer implant can be created in the regions where the buried channel will be fabricated, thus easing process integration. If for some reason the supply layer implant is not possible, note that the process shown in FIG. 11 in which the surface channel is created on the buried Si layer is an acceptable process, since the dopant can be introduced into the top SiGe layer during epitaxial growth. The supply layer is then removed from the surface channel MOSFET areas when the top SiGe and strained Si layers are selectively etched away. In the processes described in FIGs. 10, 12 and 13, it is assumed that the desire is to fabricate a buried channel MOSFET.
  • a buried channel device with a metal gate (termed a MODFET or HEMT).
  • a metal gate termed a MODFET or HEMT.
  • the advantage of this device is that the transconductance can be much higher since there is a decrease in capacitance due to the missing oxide.
  • FIGs. 14A and 14B are schematic diagrams of surface 1400 and buried 1450 channel devices with Si ⁇ . y Ge y channels 1402 on a relaxed Si ⁇ - z Ge z layer 1404. The devices are shown after salicidation and thus contain a poly-Si gate 1410, gate oxide 1408, silicide regions 1412, spacers 1414, and doped regions 1416.
  • a thin layer 1406 of Si must be deposited onto the Si ⁇ . y Ge y layer 1402 to form the gate oxide 1408, as previously described for buried channel devices.
  • the device layer sequence is unchanged and consists of a buried strained channel 1402, a SiGe spacer layer 1418, and a surface Si layer 1420 for oxidation.
  • the lattice constant of the channel layer must be less than that of the relaxed SiGe layer, i.e., y must be less than z. Since n-channel devices are sensitive to alloy scattering, the highest mobilities result when the Ge concentration in the channel is low. In order to have strain on this channel layer at a reasonable critical thickness, the underlying SiGe should have a Ge concentration in the range of 10-50%.
  • enhancement mode surface channel devices n and p channel, through implants as in typical Si CMOS technology
  • depletion-mode buried channel MOSFETs and MODFETs it is possible to create highly integrated digital/analog systems.
  • the enhancement mode devices can be fabricated into high performance CMOS, and the regions of an analog circuit requiring the high performance low-noise depletion mode device can be fabricated in the buried channel regions.
  • optimal communication stages, digital processing stages, etc. on a single platform. These different regions are connected electrically in the backend of the Si
  • CMOS chip just as transistors are connected by the back-end technology today.
  • the only changes to the CMOS process are some parameters in the processes in the fabrication facility, and the new material, but otherwise, the entire manufacturing process is transparent to the change.
  • the economics favor such a platform for integrated Si CMOS systems on chip.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

Structures et procédés servant à fabriquer des systèmes extrêmement rapides numériques, analogiques ou numériques/analogiques combinés au moyen de SiGe relaxé et planarisé en tant que plate-forme de matériaux. Ce SiGe relaxé permet d'obtenir une pléthore de couches contraintes de Si possédant des propriétés électroniques améliorées. On peut créer des circuits extrêmement rapides numériques et/ou analogiques selon que l'on place le canal du MOSFET sur la surface ou qu'on l'enterre. La planarisation préalable au dépôt des couches épitaxiales du composant permet d'obtenir une surface plate pour des opérations lithographiques de l'état actuel de la technique. Dans un mode de réalisation, l'invention concerne une structure de semi-conducteur comprenant une couche planarisée et relaxée de Si1-xGex sur un substrat, ainsi qu'une hétérostructure déposée sur ladite couche planarisée et relaxée de Si1-xGex comprenant au moins une couche contrainte.
EP02709406A 2001-03-02 2002-02-07 Plate-forme de silicium germanium relachee pour electronique cmos tres rapide et circuits analogiques tres rapides Withdrawn EP1364411A1 (fr)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US27311201P 2001-03-02 2001-03-02
US273112P 2001-03-02
US09/906,545 US6677192B1 (en) 2001-03-02 2001-07-16 Method of fabricating a relaxed silicon germanium platform having planarizing for high speed CMOS electronics and high speed analog circuits
US906545 2001-07-16
US906551 2001-07-16
US09/906,551 US6724008B2 (en) 2001-03-02 2001-07-16 Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
PCT/US2002/003681 WO2002071495A1 (fr) 2001-03-02 2002-02-07 Plate-forme de silicium germanium relachee pour electronique cmos tres rapide et circuits analogiques tres rapides

Publications (1)

Publication Number Publication Date
EP1364411A1 true EP1364411A1 (fr) 2003-11-26

Family

ID=27402529

Family Applications (1)

Application Number Title Priority Date Filing Date
EP02709406A Withdrawn EP1364411A1 (fr) 2001-03-02 2002-02-07 Plate-forme de silicium germanium relachee pour electronique cmos tres rapide et circuits analogiques tres rapides

Country Status (3)

Country Link
EP (1) EP1364411A1 (fr)
JP (1) JP2004531054A (fr)
WO (1) WO2002071495A1 (fr)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6602613B1 (en) 2000-01-20 2003-08-05 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
US6750130B1 (en) 2000-01-20 2004-06-15 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
US6555839B2 (en) 2000-05-26 2003-04-29 Amberwave Systems Corporation Buried channel strained silicon FET using a supply layer created through ion implantation
DE60125952T2 (de) 2000-08-16 2007-08-02 Massachusetts Institute Of Technology, Cambridge Verfahren für die herstellung eines halbleiterartikels mittels graduellem epitaktischen wachsen
AU2002322105A1 (en) 2001-06-14 2003-01-02 Amberware Systems Corporation Method of selective removal of sige alloys
WO2003001671A2 (fr) 2001-06-21 2003-01-03 Amberwave Systems Corporation Amelioration de transistors a effet de champ a semi-conducteur a oxyde metallique de type p
EP1415331A2 (fr) 2001-08-06 2004-05-06 Massachusetts Institute Of Technology Formation de couches planes soumises a des contraintes
US7138649B2 (en) 2001-08-09 2006-11-21 Amberwave Systems Corporation Dual-channel CMOS transistors with differentially strained channels
WO2003028106A2 (fr) 2001-09-24 2003-04-03 Amberwave Systems Corporation Circuits r.f. comprenant des transistors a couches de materiau contraintes
US20030227057A1 (en) 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
WO2003105204A2 (fr) 2002-06-07 2003-12-18 Amberwave Systems Corporation Dispositifs a semi-conducteur comprenant des couches contraintes en tension a deux canaux
US6982474B2 (en) 2002-06-25 2006-01-03 Amberwave Systems Corporation Reacted conductive gate electrodes
FR2844634B1 (fr) * 2002-09-18 2005-05-27 Soitec Silicon On Insulator Formation d'une couche utile relaxee a partir d'une plaquette sans couche tampon
US6787864B2 (en) * 2002-09-30 2004-09-07 Advanced Micro Devices, Inc. Mosfets incorporating nickel germanosilicided gate and methods for their formation
DE10318283A1 (de) 2003-04-22 2004-11-25 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur
DE10318284A1 (de) * 2003-04-22 2004-11-25 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer verspannten Schicht auf einem Substrat und Schichtstruktur
US7812340B2 (en) 2003-06-13 2010-10-12 International Business Machines Corporation Strained-silicon-on-insulator single-and double-gate MOSFET and method for forming the same
US7329923B2 (en) * 2003-06-17 2008-02-12 International Business Machines Corporation High-performance CMOS devices on hybrid crystal oriented substrates
US6831350B1 (en) * 2003-10-02 2004-12-14 Freescale Semiconductor, Inc. Semiconductor structure with different lattice constant materials and method for forming the same
US20050132952A1 (en) * 2003-12-17 2005-06-23 Michael Ward Semiconductor alloy with low surface roughness, and method of making the same
US7662689B2 (en) * 2003-12-23 2010-02-16 Intel Corporation Strained transistor integration for CMOS
US7235812B2 (en) * 2004-09-13 2007-06-26 International Business Machines Corporation Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques
JP6686419B2 (ja) * 2015-12-18 2020-04-22 株式会社Sumco シリコンゲルマニウムエピタキシャルウェーハの製造方法およびシリコンゲルマニウムエピタキシャルウェーハ

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5442205A (en) * 1991-04-24 1995-08-15 At&T Corp. Semiconductor heterostructure devices with strained semiconductor layers
US5534713A (en) * 1994-05-20 1996-07-09 International Business Machines Corporation Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers
US5891769A (en) * 1997-04-07 1999-04-06 Motorola, Inc. Method for forming a semiconductor device having a heteroepitaxial layer
US5906951A (en) * 1997-04-30 1999-05-25 International Business Machines Corporation Strained Si/SiGe layers on insulator
FR2773177B1 (fr) * 1997-12-29 2000-03-17 France Telecom Procede d'obtention d'une couche de germanium ou silicium monocristallin sur un substrat de silicium ou germanium monocristallin, respectivement, et produits multicouches obtenus
WO1999053539A1 (fr) * 1998-04-10 1999-10-21 Massachusetts Institute Of Technology Systeme de couche d'arret d'attaque chimique au silicium et au germanium
JP2003520452A (ja) * 2000-01-20 2003-07-02 アンバーウェーブ システムズ コーポレイション ひずみシリコン酸化金属半導体電界効果トランジスタ
WO2001099169A2 (fr) * 2000-06-22 2001-12-27 Massachusetts Institute Of Technology Systeme de couche d'arret de gravure

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO02071495A1 *

Also Published As

Publication number Publication date
WO2002071495A1 (fr) 2002-09-12
JP2004531054A (ja) 2004-10-07

Similar Documents

Publication Publication Date Title
US9515196B2 (en) Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6724008B2 (en) Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6646322B2 (en) Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6723661B2 (en) Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6703688B1 (en) Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6677192B1 (en) Method of fabricating a relaxed silicon germanium platform having planarizing for high speed CMOS electronics and high speed analog circuits
US6593641B1 (en) Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6900103B2 (en) Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
EP1364411A1 (fr) Plate-forme de silicium germanium relachee pour electronique cmos tres rapide et circuits analogiques tres rapides
JP3376211B2 (ja) 半導体装置、半導体基板の製造方法及び半導体装置の製造方法
US7504311B2 (en) Structure and method of integrating compound and elemental semiconductors for high-performance CMOS
US7029994B2 (en) Strained channel on insulator device
US7034362B2 (en) Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures
US7208754B2 (en) Strained silicon structure
JP3512701B2 (ja) 半導体装置及びその製造方法
US7915100B2 (en) Hybrid orientation CMOS with partial insulation process
US7560328B2 (en) Strained Si on multiple materials for bulk or SOI substrates
US20140103366A1 (en) Silicon device on si:c-oi and sgoi and method of manufacture
KR20050106432A (ko) 마이크로 전자기술을 위한 이중 변형 상태 ＳｉＧｅ 층
KR20060033692A (ko) 변형된 실리콘 기반 층, 이의 제조 방법, 다수의 디바이스및 전자 시스템
US20100078687A1 (en) Method for Transistor Fabrication with Optimized Performance
JP2000031491A (ja) 半導体装置，半導体装置の製造方法，半導体基板および半導体基板の製造方法
WO2002071491A1 (fr) Plate-forme au silicium-germanium relachee pour electronique cmos grande vitesse et circuits analogiques grande vitesse
WO2002071488A1 (fr) Plate-forme silicium germanium a relaxation pour systemes electroniques cmos grande vitesse et circuits analogiques grande vitesse
WO2002071493A2 (fr) Plate-forme de silicium-germanium (sige) a l'etat detendu pour electronique de mos complementaire (cmos) grande vitesse et pour circuits analogiques grande vitesse

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20030917

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

AX Request for extension of the european patent

Extension state: AL LT LV MK RO SI

17Q First examination report despatched

Effective date: 20040511

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20051005