JP2004172378A - Power module, substrate therefor and method for manufacturing the both - Google Patents

Power module, substrate therefor and method for manufacturing the both Download PDF

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Publication number
JP2004172378A
JP2004172378A JP2002336571A JP2002336571A JP2004172378A JP 2004172378 A JP2004172378 A JP 2004172378A JP 2002336571 A JP2002336571 A JP 2002336571A JP 2002336571 A JP2002336571 A JP 2002336571A JP 2004172378 A JP2004172378 A JP 2004172378A
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Prior art keywords
power module
plating layer
substrate
manufacturing
nip
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JP2002336571A
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JP3922166B2 (en
Inventor
Reiko Ogawa
怜子 小川
Yoshiyuki Nagatomo
義幸 長友
Toshiyuki Nagase
敏之 長瀬
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Mitsubishi Materials Corp
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Mitsubishi Materials Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Abstract

<P>PROBLEM TO BE SOLVED: To improve the wetting property of a solder layer, and to reduce a voice rate in a method for manufacturing a substrate for a power module, a substrate for a power module, and a power module. <P>SOLUTION: This method for manufacturing a substrate for a power module comprises: a first plating process for carrying out NiP plating on a metallic substrate to form an NiP plated layer 6; a surface processing process for removing the surface of the NiP plated layer more deeply than a surface oxide film to smooth it, and a second plating process for carrying out Ni plating on the electrolytic polished NiP plated layer to form an Ni plated layer 7. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、電気自動車や電気車両等、大電流・大電圧を制御する半導体装置に用いられるパワーモジュール用基板の製造方法並びにパワーモジュール用基板及びパワーモジュールに関する。
【０００２】
【従来の技術】
半導体素子の中でも電力供給のためのパワーモジュールは発熱量が比較的高いため、これを搭載する基板としては、通常、図３に示すように、セラミックス基板１上にＡｌ等の回路基板２が直接又はろう材を介して接着されたパワーモジュール用基板が用いられる。なお、この例では、セラミックス基板１の下面にＡｌ等の金属基板３が接着され、この金属基板３を介して放熱板４上にパワーモジュール用基板全体が接着されている。このような技術は、例えば、下記の特許文献１に記載されている。
【０００３】
【特許文献１】
実開平０３−５７９４５号公報
【０００４】
上記パワーモジュール用基板の回路基板２及び金属基板３は、パワー素子のＳｉチップ５を搭載するため及び放熱板４上に接着するために、従来、図４の（ａ）に示すように、金属基板３上にＮｉＰメッキ層６の下地メッキを行い、その表層に形成された表面酸化膜６ａをシアン化ナトリウム等で除去する前処理を行い、さらに、図４の（ｂ）に示すように、その上にＮｉメッキ層７をメッキしている。そして、該Ｎｉメッキ層７上に半田付けを行うことにより、半田層８を介してＳｉチップ５をパワーモジュール用基板上に搭載し、またパワーモジュール用基板を放熱板４に接着していた。
【０００５】
【発明が解決しようとする課題】
しかしながら、上記従来の回路基板の製造技術には、以下の課題が残されている。従来技術では、ＮｉＰメッキ層の表面酸化膜だけを除去するため、粗い下地（ＮｉＰメッキ層）の凹凸をそのまま反映した状態でメッキされたＮｉメッキ層となってしまう。すなわち、Ｎｉメッキ層の表面粗れが大きくなり、その後、半田付けにより形成される半田層の濡れ性の低下やボイド率の増大を招いてしまう不都合があった。このため、半田層の濡れ性が悪くフィレット形成ができない（例えば、図３中の２点鎖線部分）とともに、ボイドの発生率が高くなって応力集中が生じ、いずれも信頼性を低下させてしまう。また、ボイド率を低減させるために、真空中で又は超音波を加えて半田付けを行う必要があり、製造工程の高コスト化を招いていた。
【０００６】
本発明は、前述の課題に鑑みてなされたもので、半田層の濡れ性向上及びボイド率の低減を図ることができるパワーモジュール用基板の製造方法並びにパワーモジュール用基板及びパワーモジュールを提供することを目的とする。
【０００７】
【課題を解決するための手段】
本発明は、前記課題を解決するために以下の構成を採用した。すなわち、本発明のパワーモジュール用基板の製造方法は、金属基板上にＮｉＰメッキを施してＮｉＰメッキ層を形成する第１のメッキ工程と、該ＮｉＰメッキ層の表面を表面酸化膜よりも深く除去して平滑化する表面処理工程と、平滑化された前記ＮｉＰメッキ層上にＮｉメッキを施してＮｉメッキ層を形成する第２のメッキ工程とを有することを特徴とする。
【０００８】
このパワーモジュール用基板の製造方法では、ＮｉＰメッキ層の表面を表面酸化膜よりも深く除去して平滑化する表面処理工程を有するので、平滑化されたＮｉＰメッキ層により、半田濡れ性の低下やボイド率の増大を防ぐことができる。なお、上記表面処理手段としては、研削、パフ研磨、サンドブラスト、ケミカルエッチング（希硝酸、フッ硝酸等）、電解エッチング、電解研磨等が採用される。
【０００９】
また、本発明のパワーモジュール用基板の製造方法は、前記表面処理工程において、電解研磨作用と電解エッチング作用との両作用を有する電解液で処理する技術が採用される。
【００１０】
このパワーモジュール用基板の製造方法では、ＮｉＰメッキの表面を電解研磨作用と電解エッチング作用との両作用を有する電解液で処理するので、電解研磨作用でＮｉＰメッキの表面酸化膜を除去すると共に表面の凹凸を緩和することができ、さらに電解エッチング作用により表面に微細な孔が多数形成され、積層される層の密着性を向上（アンカー効果）させることができる。したがって、平滑性及び密着性の優れたＮｉＰメッキ層表面上にＮｉメッキ層を形成するので、さらにその上に形成される半田層の濡れ性が向上すると共に、ボイド率を低減させることができる。また、真空中で又は超音波を加えて半田付けしなくても、十分にボイド率の低い半田層を形成することができる。
なお、上記の「電解研磨作用と電解エッチング作用との両作用を有する」とは、いずれか一方の作用が支配的でないことを意味する。すなわち、電解研磨作用が支配的で電解エッチング作用がほとんど生じない電解液を用いると、微細孔による密着性向上が困難である。また、逆に電解エッチング作用が支配的で電解研磨作用がほとんど生じない電解液を用いると、表面酸化膜及び表面凹凸の除去が困難である。また、上記「表面の凹凸」は、上記「微細な孔」に対して１桁以上大きなサイズ及び周期で形成される凹凸である。
【００１１】
また、本発明のパワーモジュール用基板の製造方法は、表面処理工程において、前記ＮｉＰメッキ層の表面粗さをＲａ０．４以下にし、かつ拡散反射率を６０％以下にまで処理することが好ましい。すなわち、このパワーモジュール用基板の製造方法では、表面処理工程において、ＮｉＰメッキ層の表面粗さをＲａ０．４以下にし、かつ拡散反射率を６０％以下にまで処理することにより、高融点半田（Ｓｎ１０％）を半田付けした際に、半田層の濡れ率が７５％以上となると共に、ボイド率が５％以下にすることができる。なお、上記拡散反射率とは、測定対象物の表面に入射させた所定の入射光の光量に対する拡散反射光の光量を百分率で示したものである。
【００１２】
本発明のパワーモジュール用基板は、上記本発明のパワーモジュール用基板の製造方法で作製されたことを特徴とする。すなわち、このパワーモジュール用基板では、上記本発明のパワーモジュール用基板の製造方法で作製されているので、接着特性の優れた半田付けが可能であり、半導体チップの接着に関し高い信頼性を得ることができる。
【００１３】
本発明のパワーモジュールは、セラミックス基板と該セラミックス基板上に回路基板とを備え、該回路基板上に半導体チップが搭載されたパワーモジュールであって、前記回路基板は、上記本発明のパワーモジュール用基板であり、前記半導体チップは、前記回路基板上に半田付けにより接着されていることを特徴とする。すなわち、このパワーモジュールでは、回路基板が、上記本発明のパワーモジュール用基板であり、半導体チップが、回路基板上に半田付けにより接着されているので、接着特性の優れた半田付けにより高い信頼性を有することができる。
【００１４】
【発明の実施の形態】
以下、本発明に係るパワーモジュール用基板の製造方法並びにパワーモジュール用基板及びパワーモジュールの一実施形態を、図１及び図２を参照しながら説明する。
【００１５】
本実施形態のパワーモジュール用基板及びこれを用いたパワーモジュールは、図１に示すように、電力供給用のパワー素子を有するＳｉチップ（半導体チップ）５を搭載するものである。このパワーモジュール用基板及びパワーモジュールの構造を、その製造プロセスと合わせて説明すると、まず、Ａｌ２Ｏ３等を含むセラミックス基板１の上面にＡｌ（アルミニウム）等の回路基板２を直接又はろう材を介して接着すると共に、セラミックス基板１の下面にＡｌ等の金属基板３を直接又はろう材を介して接着する。なお、上記回路基板２の表面には、所望の回路パターンが形成されている。
【００１６】
次に、上記回路基板２及び金属基板３の表面上に、従来と同様に、図４の（ａ）に示すように、ＮｉＰメッキ層６の下地メッキを化学メッキにより行う。
次に、ＮｉＰメッキ層６の表面を、図２の（ａ）に示すように、表面酸化膜６ａよりも深く除去するため、電解研磨作用と電解エッチング作用との両作用を有する電解液で処理する。なお、電解液としては、所定の硫酸濃度とした硫酸溶液を用いる。なお、表面処理の傾向として、電解研磨作用が大きい場合、表面が削れた後の面に光沢が生じ易くなり、電解エッチング作用が大きい場合、表面が削れた後の面は微細に荒れていて白く曇り易くなる。
【００１７】
また、この際、ＮｉＰメッキ層６の表面粗さがＲａ０．４以下、かつ拡散反射率が６０％以下になるまで処理を行う。なお、本実施形態では、表面粗さの値として「ミツトヨ製ｓｕｒｆｔｅｓｔ５０１」でＲａ測定モードにて測定したものを用いると共に、拡散反射率の値として「スガ試験機製カラーコンピュータ」を用いて測定したものを用いている。
【００１８】
この表面処理の工程では、電解研磨作用でＮｉＰメッキ層６の表面酸化膜６ａが除去されると共に表面の凹凸が緩和され、平滑性のある表面となる。さらに電解エッチング作用により表面に微細な孔が多数形成され、アンカー効果の高い表面状態となる。
次に、上記表面処理されたＮｉＰメッキ層６上に、Ｎｉメッキ層７を電解メッキする。この際、平滑性及び密着性の優れたＮｉＰメッキ層６表面上にＮｉメッキ層７を形成するので、ＮｉＰメッキ層６の表面状態が反映されて平滑性及び密着性の優れたＮｉメッキ層７が得られる。このように上記工程により、本実施形態のパワーモジュール用基板が作製される。
【００１９】
なお、上記表面処理されたＮｉＰメッキ層６の平滑レベルは、
Ｒａ（算術平均粗さ）が０．０１から０．４である。
Ｒｚ（十点平均粗さ）が０．０１から３．０である。
Δａ（算術返金傾斜）が１から６である。
Ｓｍ（凹凸の平均間隔）が２０から６０である。
すなわち、Ｒａ、Ｒｚが小さいため、凹凸は小さく半田濡れ性に悪影響を与えることがない。また、Δａ、Ｓｍが小さいので、凹凸の山谷が細かいため、ＮｉＰメッキ層７上に施す電解Ｎｉメッキ層との密着性向上（もしくは確保）を図ることができる。
【００２０】
次に、上記パワーモジュール用基板の回路基板２上面、すなわちＮｉメッキ層７上に、Ｓｉチップ５を半田付けにより接着すると共に、パワーモジュール用基板を、金属基板３を介して放熱板４上に半田付けにより接着する。なお、上記半田付けは、高融点半田（Ｓｎ１０％）を用い、真空中ではなく、かつ超音波等を加えずに行う。この半田付けの際、回路基板２上及び金属基板３上のＮｉメッキ層７は、平滑性及び密着性の高い表面状態であるので、半田付けにより形成される半田層８の濡れ性が向上し、良好なフィレット形成（例えば、図１中の２点鎖線部分）ができると共に、ボイド率を低減できる。
このようにして、本実施形態のパワーモジュールが作製される。
【００２１】
本実施形態では、ＮｉＰメッキ層６の表面を電解研磨作用と電解エッチング作用との両作用を有する電解液で処理するので、凹凸が緩和されると共に微細孔を有したＮｉＰメッキ層６表面上に平滑性及び密着性の優れたＮｉメッキ層７を形成することができ、さらにその上に形成される半田層８の濡れ性が向上すると共に、ボイド率を低減させることができる。
【００２２】
さらに、ＮｉＰメッキ層６の表面粗さをＲａ０．４以下にし、かつ拡散反射率を６０％以下にまで処理することにより、高融点半田（Ｓｎ１０％）を半田付けした際に、半田層の濡れ率が７５％以上となると共に、ボイド率が５％以下にすることができる。
【００２３】
このように、回路基板２上にＳｉチップ５を接着特性の優れた半田付けにより搭載することができ、パワーモジュールとして高い信頼性を有することができる。
【００２４】
なお、本発明の技術範囲は上記実施の形態に限定されるものではなく、本発明の趣旨を逸脱しない範囲において種々の変更を加えることが可能である。
例えば、上記実施形態では、回路基板２及び金属基板３の両表面において上記表面処理工程を行ったメッキ及び半田付けを行ったが、いずれか一方にのみ行っても構わない。なお、回路基板２及び金属基板３の両表面に適用すれば、両方で半田接合部の高い信頼性が得られ、より好ましいことは言うまでもない。
また、上記回路基板及び金属基板の表面は、荒れている方が上記下地メッキが密着良くつきやすい。すなわち、無電解メッキ（下地メッキ（Ｎｉメッキ））の前処理であるジンケートは、被メッキ表面のうち活性点の高いところから結晶が置換析出してその結晶核を起点に成長が始まるからである。
また、上記表面処理工程の他の例としては、研削、パフ研磨、サンドブラスト、ケミカルエッチング（希硝酸、フッ硝酸等）、電解エッチング、電解研磨等を採用しても構わない。
【００２５】
【発明の効果】
本発明によれば、以下の効果を奏する。
すなわち、本発明のパワーモジュール用基板の製造方法並びにパワーモジュール用基板及びパワーモジュールによれば、ＮｉＰメッキ層の表面を表面酸化膜よりも深く除去して平滑化するので、平滑化されたＮｉＰメッキ層により、半田濡れ性の低下やボイド率の増大を防ぐことができる。したがって、低コストで接合部分の高い信頼性を有するパワーモジュールを得ることができる。
【図面の簡単な説明】
【図１】本発明に係る一実施形態において、パワーモジュールを示す断面図である。
【図２】本発明に係る一実施形態において、パワーモジュールの製造工程（表面処理工程及びＮｉメッキ工程）を説明するための断面図である。
【図３】本発明に係る従来例において、パワーモジュールを示す断面図である。
【図４】本発明に係る従来例において、パワーモジュールの製造工程（ＮｉＰメッキ工程及びＮｉメッキ工程）を説明するための断面図である。
【符号の説明】
１ セラミックス基板
２ 回路基板（金属基板）
３ 金属基板
４ 放熱板
５ Ｓｉチップ（半導体チップ）
６ ＮｉＰメッキ層
６ａ 表面酸化膜
７ Ｎｉメッキ層
８ 半田層[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a power module substrate used in a semiconductor device that controls a large current and a large voltage, such as an electric vehicle and an electric vehicle, and a power module substrate and a power module.
[0002]
[Prior art]
Since a power module for supplying power among semiconductor elements generates a relatively large amount of heat, a circuit board 2 such as Al is usually directly mounted on a ceramic substrate 1 as shown in FIG. Alternatively, a power module substrate bonded through a brazing material is used. In this example, a metal substrate 3 of Al or the like is adhered to the lower surface of the ceramic substrate 1, and the entire power module substrate is adhered to the heat radiating plate 4 via the metal substrate 3. Such a technique is described, for example, in Patent Document 1 below.
[0003]
[Patent Document 1]
Japanese Utility Model Publication No. 03-57945 [0004]
Conventionally, as shown in FIG. 4A, the circuit board 2 and the metal substrate 3 of the power module substrate are mounted on a metal plate as shown in FIG. A base treatment of the NiP plating layer 6 is performed on the substrate 3, and a pretreatment for removing the surface oxide film 6 a formed on the surface layer with sodium cyanide or the like is performed. Further, as shown in FIG. The Ni plating layer 7 is plated thereon. Then, by performing soldering on the Ni plating layer 7, the Si chip 5 was mounted on the power module substrate via the solder layer 8, and the power module substrate was bonded to the heat sink 4.
[0005]
[Problems to be solved by the invention]
However, the following problems remain in the conventional circuit board manufacturing technology. In the prior art, since only the surface oxide film of the NiP plating layer is removed, the Ni plating layer is plated in a state in which the unevenness of the rough underlayer (NiP plating layer) is directly reflected. That is, the surface roughness of the Ni plating layer becomes large, and thereafter, there is a disadvantage that the wettability of the solder layer formed by soldering is reduced and the void ratio is increased. For this reason, the fillet cannot be formed due to the poor wettability of the solder layer (for example, a two-dot chain line portion in FIG. 3), and the occurrence rate of voids increases, and stress concentration occurs, and in any case, the reliability decreases. . Further, in order to reduce the void ratio, it is necessary to perform the soldering in a vacuum or by applying ultrasonic waves, which has led to an increase in the cost of the manufacturing process.
[0006]
The present invention has been made in view of the above-described problems, and provides a method for manufacturing a power module substrate, and a power module substrate and a power module that can improve the wettability of a solder layer and reduce the void ratio. With the goal.
[0007]
[Means for Solving the Problems]
The present invention has the following features to attain the object mentioned above. That is, in the method for manufacturing a power module substrate according to the present invention, a first plating step of forming a NiP plating layer by applying NiP plating on a metal substrate, and removing the surface of the NiP plating layer deeper than the surface oxide film And a second plating step of applying a Ni plating on the smoothed NiP plating layer to form a Ni plating layer.
[0008]
This method of manufacturing a power module substrate includes a surface treatment step of removing and smoothing the surface of the NiP plating layer deeper than the surface oxide film, so that the smoothed NiP plating layer causes a reduction in solder wettability. An increase in the void ratio can be prevented. As the surface treatment means, grinding, puff polishing, sand blasting, chemical etching (dilute nitric acid, hydrofluoric nitric acid, etc.), electrolytic etching, electrolytic polishing and the like are employed.
[0009]
Further, in the method of manufacturing a power module substrate according to the present invention, in the surface treatment step, a technique is employed in which the substrate is treated with an electrolytic solution having both an electrolytic polishing action and an electrolytic etching action.
[0010]
In this method of manufacturing a power module substrate, the surface of the NiP plating is treated with an electrolytic solution having both an electrolytic polishing action and an electrolytic etching action. Unevenness can be reduced, and a large number of fine holes are formed on the surface by the electrolytic etching action, whereby the adhesion of the layers to be laminated can be improved (anchor effect). Therefore, since the Ni plating layer is formed on the surface of the NiP plating layer having excellent smoothness and adhesion, the wettability of the solder layer formed thereon can be further improved, and the void ratio can be reduced. Further, a solder layer having a sufficiently low void ratio can be formed without soldering in a vacuum or by applying ultrasonic waves.
Here, “having both the electrolytic polishing action and the electrolytic etching action” means that one of the actions is not dominant. That is, if an electrolytic solution in which the electrolytic polishing action is dominant and the electrolytic etching action hardly occurs is used, it is difficult to improve the adhesion by the fine holes. Conversely, if an electrolytic solution in which the electrolytic etching action is dominant and the electropolishing action hardly occurs is used, it is difficult to remove the surface oxide film and the surface irregularities. Further, the “surface irregularities” are irregularities formed in a size and a period larger than the “fine holes” by one digit or more.
[0011]
In the method of manufacturing a power module substrate according to the present invention, it is preferable that, in the surface treatment step, the NiP plating layer has a surface roughness of 0.4 or less and a diffuse reflectance of 60% or less. That is, in the method for manufacturing a power module substrate, in the surface treatment step, the surface roughness of the NiP plating layer is reduced to Ra 0.4 or less and the diffuse reflectance is reduced to 60% or less, so that the high melting point solder ( When Sn (10% Sn) is soldered, the wetting rate of the solder layer is 75% or more and the void rate can be 5% or less. Note that the diffuse reflectance is a percentage of the amount of diffuse reflected light with respect to the amount of predetermined incident light incident on the surface of the measurement object.
[0012]
A power module substrate according to the present invention is manufactured by the above-described method for manufacturing a power module substrate according to the present invention. That is, since the power module substrate is manufactured by the above-described method for manufacturing a power module substrate of the present invention, it is possible to perform soldering with excellent adhesive properties and obtain high reliability in bonding semiconductor chips. Can be.
[0013]
A power module according to the present invention is a power module including a ceramic substrate and a circuit board on the ceramic substrate, and a semiconductor chip mounted on the circuit board, wherein the circuit board is used for the power module according to the present invention. A substrate, wherein the semiconductor chip is bonded to the circuit board by soldering. That is, in this power module, the circuit board is the power module board of the present invention, and the semiconductor chip is bonded to the circuit board by soldering. Can be provided.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of a method for manufacturing a power module substrate, a power module substrate, and a power module according to the present invention will be described with reference to FIGS.
[0015]
The power module substrate and the power module using the same according to the present embodiment mount an Si chip (semiconductor chip) 5 having a power element for power supply as shown in FIG. The structure of the power module substrate and the power module will be described together with the manufacturing process. First, a circuit board 2 such as Al (aluminum) is directly or brazed onto a ceramic substrate 1 containing Al 2 O 3 or the like. And a metal substrate 3 of Al or the like is bonded to the lower surface of the ceramic substrate 1 directly or via a brazing material. A desired circuit pattern is formed on the surface of the circuit board 2.
[0016]
Next, on the surfaces of the circuit board 2 and the metal board 3, as shown in FIG. 4A, a base plating of the NiP plating layer 6 is performed by chemical plating, as in the conventional case.
Next, in order to remove the surface of the NiP plating layer 6 deeper than the surface oxide film 6a, as shown in FIG. 2A, the surface is treated with an electrolytic solution having both an electrolytic polishing action and an electrolytic etching action. I do. Note that a sulfuric acid solution having a predetermined sulfuric acid concentration is used as the electrolytic solution. In addition, as a tendency of the surface treatment, when the electrolytic polishing action is large, the surface after the surface is polished tends to be glossy, and when the electrolytic etching action is large, the surface after the surface is polished is finely rough and white. It becomes cloudy easily.
[0017]
At this time, the process is performed until the surface roughness of the NiP plating layer 6 becomes Ra 0.4 or less and the diffuse reflectance becomes 60% or less. In the present embodiment, the value of the surface roughness measured in the Ra measurement mode with "Mitsutoyo Surftest 501" is used, and the value of the diffuse reflectance is measured using the "Suga Test Machine Color Computer". Is used.
[0018]
In this surface treatment step, the surface oxide film 6a of the NiP plating layer 6 is removed by the electrolytic polishing action, and the unevenness on the surface is alleviated, resulting in a smooth surface. Furthermore, a large number of fine holes are formed on the surface by the electrolytic etching action, resulting in a surface state having a high anchor effect.
Next, a Ni plating layer 7 is electrolytically plated on the surface-treated NiP plating layer 6. At this time, since the Ni plating layer 7 is formed on the surface of the NiP plating layer 6 having excellent smoothness and adhesion, the surface state of the NiP plating layer 6 is reflected and the Ni plating layer 7 having excellent smoothness and adhesion is provided. Is obtained. As described above, the power module substrate of the present embodiment is manufactured through the above steps.
[0019]
The smoothness level of the surface-treated NiP plating layer 6 is as follows:
Ra (arithmetic mean roughness) is 0.01 to 0.4.
Rz (ten-point average roughness) is 0.01 to 3.0.
Δa (arithmetic refund slope) is 1 to 6.
Sm (average interval of unevenness) is 20 to 60.
That is, since Ra and Rz are small, the irregularities are small and do not adversely affect the solder wettability. Further, since Δa and Sm are small, the peaks and valleys of the unevenness are fine, so that it is possible to improve (or secure) the adhesion to the electrolytic Ni plating layer formed on the NiP plating layer 7.
[0020]
Next, the Si chip 5 is adhered to the upper surface of the circuit board 2 of the power module substrate, that is, the Ni plating layer 7 by soldering, and the power module substrate is placed on the heat sink 4 via the metal substrate 3. Adhere by soldering. The above soldering is performed using high melting point solder (Sn 10%), not in a vacuum, and without applying ultrasonic waves or the like. At the time of this soldering, the Ni plating layer 7 on the circuit board 2 and the metal board 3 has a surface state with high smoothness and adhesion, so that the wettability of the solder layer 8 formed by soldering is improved. In addition, good fillet formation (for example, a two-dot chain line portion in FIG. 1) can be performed, and a void ratio can be reduced.
Thus, the power module of the present embodiment is manufactured.
[0021]
In the present embodiment, since the surface of the NiP plating layer 6 is treated with an electrolytic solution having both an electrolytic polishing action and an electrolytic etching action, the unevenness is reduced and the NiP plating layer 6 has fine pores. The Ni plating layer 7 having excellent smoothness and adhesion can be formed, and the wettability of the solder layer 8 formed thereon can be improved, and the void ratio can be reduced.
[0022]
Further, the surface roughness of the NiP plating layer 6 is set to Ra 0.4 or less and the diffuse reflectance is reduced to 60% or less, so that when the high melting point solder (Sn 10%) is soldered, the solder layer is wetted. The ratio can be 75% or more, and the void ratio can be 5% or less.
[0023]
As described above, the Si chip 5 can be mounted on the circuit board 2 by soldering having excellent adhesive properties, and the power module can have high reliability.
[0024]
The technical scope of the present invention is not limited to the above-described embodiment, and various changes can be made without departing from the spirit of the present invention.
For example, in the above-described embodiment, plating and soldering in which the above-described surface treatment step is performed are performed on both surfaces of the circuit board 2 and the metal substrate 3, but may be performed on only one of them. When applied to both surfaces of the circuit board 2 and the metal substrate 3, it is needless to say that high reliability of the solder joint is obtained at both the surfaces, which is more preferable.
In addition, the rougher the surfaces of the circuit board and the metal substrate, the better the adhesion of the base plating with good adhesion. That is, in the zincate which is a pretreatment of the electroless plating (undercoating (Ni plating)), the crystals are substituted and precipitated from a portion having a high active point on the surface to be plated, and the growth starts from the crystal nucleus as a starting point. .
Further, as other examples of the surface treatment step, grinding, puff polishing, sand blasting, chemical etching (dilute nitric acid, hydrofluoric nitric acid, etc.), electrolytic etching, electrolytic polishing, and the like may be employed.
[0025]
【The invention's effect】
According to the present invention, the following effects can be obtained.
That is, according to the method for manufacturing a power module substrate, the power module substrate, and the power module of the present invention, the surface of the NiP plating layer is removed more deeply than the surface oxide film and smoothed. The layer can prevent a decrease in solder wettability and an increase in void ratio. Therefore, it is possible to obtain a low-cost power module having high reliability of the joint portion.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a power module according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view for explaining a power module manufacturing process (a surface treatment process and a Ni plating process) in one embodiment according to the present invention.
FIG. 3 is a sectional view showing a power module in a conventional example according to the present invention.
FIG. 4 is a cross-sectional view for explaining a power module manufacturing process (NiP plating process and Ni plating process) in the conventional example according to the present invention.
[Explanation of symbols]
1 ceramic substrate 2 circuit substrate (metal substrate)
3 Metal substrate 4 Heat sink 5 Si chip (semiconductor chip)
6 NiP plating layer 6a Surface oxide film 7 Ni plating layer 8 Solder layer

Claims (5)

金属基板上にＮｉＰメッキを施してＮｉＰメッキ層を形成する第１のメッキ工程と、
該ＮｉＰメッキ層の表面を表面酸化膜よりも深く除去して平滑化する表面処理工程と、
平滑化された前記ＮｉＰメッキ層上にＮｉメッキを施してＮｉメッキ層を形成する第２のメッキ工程とを有することを特徴とするパワーモジュール用基板の製造方法。A first plating step of forming a NiP plating layer by applying NiP plating on a metal substrate;
A surface treatment step of removing and smoothing the surface of the NiP plating layer deeper than the surface oxide film;
A second plating step of forming a Ni plating layer by applying Ni plating on the smoothed NiP plating layer. 請求項１に記載のパワーモジュール用基板の製造方法において、
前記表面処理工程は、電解研磨作用と電解エッチング作用との両作用を有する電解液で処理することを特徴とするパワーモジュール用基板の製造方法。The method for manufacturing a power module substrate according to claim 1,
The method for manufacturing a power module substrate, wherein the surface treatment step is performed with an electrolytic solution having both an electrolytic polishing action and an electrolytic etching action. 請求項１又は２に記載のパワーモジュール用基板の製造方法において、
前記表面処理工程は、前記ＮｉＰメッキ層の表面粗さをＲａ０．４以下にし、かつ拡散反射率を６０％以下にまで処理することを特徴とするパワーモジュール用基板の製造方法。The method for manufacturing a power module substrate according to claim 1 or 2,
The method of manufacturing a power module substrate, wherein the surface treatment step comprises treating the NiP plating layer to a surface roughness of Ra 0.4 or less and a diffuse reflectance of 60% or less. 請求項１から３のいずれかに記載のパワーモジュール用基板の製造方法で作製されたことを特徴とするパワーモジュール用基板。A power module substrate manufactured by the method for manufacturing a power module substrate according to claim 1. セラミックス基板と該セラミックス基板上に回路基板とを備え、該回路基板上に半導体チップが搭載されたパワーモジュールであって、
前記回路基板は、請求項４に記載のパワーモジュール用基板であり、
前記半導体チップは、前記回路基板上に半田付けにより接着されていることを特徴とするパワーモジュール。A power module comprising a ceramic substrate and a circuit board on the ceramic substrate, and a semiconductor chip mounted on the circuit board,
The circuit board is a power module board according to claim 4,
The power module according to claim 1, wherein the semiconductor chip is bonded to the circuit board by soldering.
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