WO2017222061A1 - Method for manufacturing insulated circuit board, insulated circuit board, and thermoelectric conversion module - Google Patents

Method for manufacturing insulated circuit board, insulated circuit board, and thermoelectric conversion module Download PDF

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Publication number
WO2017222061A1
WO2017222061A1 PCT/JP2017/023272 JP2017023272W WO2017222061A1 WO 2017222061 A1 WO2017222061 A1 WO 2017222061A1 JP 2017023272 W JP2017023272 W JP 2017023272W WO 2017222061 A1 WO2017222061 A1 WO 2017222061A1
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Prior art keywords
layer
aluminum
titanium
circuit board
ceramic substrate
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Application number
PCT/JP2017/023272
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French (fr)
Japanese (ja)
Inventor
伸幸 寺▲崎▼
東洋 大橋
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三菱マテリアル株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2017121741A external-priority patent/JP6904094B2/en
Application filed by 三菱マテリアル株式会社 filed Critical 三菱マテリアル株式会社
Priority to CN201780034318.3A priority Critical patent/CN109219878B/en
Priority to EP17815526.3A priority patent/EP3477695B1/en
Priority to US16/306,708 priority patent/US10798824B2/en
Priority to EP20180726.0A priority patent/EP3734654B1/en
Publication of WO2017222061A1 publication Critical patent/WO2017222061A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0055—After-treatment, e.g. cleaning or desmearing of holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/062—Etching masks consisting of metals or alloys or metallic inorganic compounds
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/80—Constructional details
    • H10N10/81—Structural details of the junction
    • H10N10/817—Structural details of the junction the junction being non-separable, e.g. being cemented, sintered or soldered
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0341—Intermediate metal, e.g. before reinforcing of conductors by plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10219—Thermoelectric component

Definitions

  • the present invention relates to a method for manufacturing an insulated circuit board, a insulated circuit board, and a thermoelectric conversion module including a ceramic substrate and a circuit layer having a circuit pattern disposed on one surface of the ceramic substrate.
  • the present application claims priority based on Japanese Patent Application No. 2016-124667 filed in Japan on June 23, 2016, and Japanese Patent Application No. 2017-121741 filed in Japan on June 21, 2017. The contents are incorporated herein.
  • thermoelectric conversion modules have a structure in which a semiconductor element or a thermoelectric element is bonded on a circuit layer made of a conductive material.
  • a semiconductor element or a thermoelectric element is bonded on a circuit layer made of a conductive material.
  • the amount of heat generated is large. Therefore, for example, AlN (aluminum nitride), Al 2.
  • an insulating circuit board including a ceramic substrate made of 2 O 3 (alumina) and a circuit layer formed by bonding a metal plate having excellent conductivity to one surface of the ceramic substrate has been widely used. It has been.
  • a ceramic substrate having a metal layer formed on the other surface is also provided.
  • the power module shown in Patent Document 1 is bonded to an insulating circuit board in which a circuit layer and a metal layer made of Al are formed on one surface and the other surface of a ceramic substrate, and a solder material is bonded to the circuit layer. And a semiconductor device that has been manufactured. A heat sink is bonded to the other surface side of the insulating circuit board, and the heat transmitted from the semiconductor element to the insulating circuit board side is dissipated to the outside through the heat sink.
  • Patent Document 1 discloses a technique for joining a circuit layer and a semiconductor element, and a metal layer and a heat sink by using a silver oxide paste containing silver oxide particles and a reducing agent made of an organic substance as an alternative to a solder material. Has been proposed.
  • Patent Document 4 proposes an insulated circuit board in which the circuit layer has a laminated structure of an aluminum layer and a metal member layer made of copper, nickel, or silver.
  • This insulated circuit board has a structure in which an aluminum layer and a metal member layer are bonded via a titanium layer.
  • thermoelectric conversion module when the circuit layer is made of aluminum or the like, aluminum diffuses into the thermoelectric element, which may deteriorate the characteristics of the thermoelectric element. For this reason, in order to prevent aluminum from diffusing into the thermoelectric element, it is conceivable to form a titanium layer as a diffusion preventing layer on the surface of the circuit layer.
  • an etching process may be performed to form a circuit pattern in the circuit layer.
  • ferric chloride is used as an etchant used when etching copper or aluminum.
  • the above-mentioned etching agent cannot etch the titanium layer, there is a problem that the circuit pattern having the titanium layer cannot be etched to form a circuit pattern.
  • the present invention has been made in view of the circumstances described above, and includes an aluminum layer disposed on one surface of a ceramic substrate and titanium formed on the surface of the aluminum layer opposite to the ceramic substrate.
  • An object of the present invention is to provide an insulating circuit board manufacturing method, an insulating circuit board, and a thermoelectric conversion module capable of forming a circuit pattern with high accuracy and efficiency with respect to a circuit layer having a layer.
  • an insulating circuit board manufacturing method includes an insulating circuit board including a ceramic substrate and a circuit layer having a circuit pattern disposed on one surface of the ceramic substrate.
  • the circuit layer includes an aluminum layer disposed on one surface of the ceramic substrate, and a titanium layer formed on a surface of the aluminum layer opposite to the ceramic substrate.
  • a titanium layer forming step of forming the titanium layer is characterized in that the aluminum layer wherein the titanium layer is formed and a, and an etching process for etching the circuit pattern.
  • the titanium layer can be formed in a circuit pattern on the surface of the aluminum layer.
  • the aluminum layer having the titanium layer formed into a circuit pattern is provided with an etching process step, the titanium layer acts as a resist material, and the aluminum layer is etched into a circuit pattern. be able to.
  • the resist material application process, the curing process and the peeling process can be omitted, and the etching process process can be performed efficiently.
  • the circuit pattern is accurately applied to the circuit layer having the aluminum layer disposed on one surface of the ceramic substrate and the titanium layer formed on the surface of the aluminum layer opposite to the ceramic substrate. And can be formed efficiently.
  • the circuit layer includes a metal member layer made of copper, nickel, or silver laminated on a surface of the titanium layer opposite to the aluminum layer. And a metal member layer forming step of forming the metal member layer on the surface of the titanium layer formed in a circuit pattern after the etching treatment step.
  • the metal member layer is made of copper or copper alloy, nickel or nickel alloy, or silver or silver alloy.
  • the metal member which consists of copper, nickel, or silver on a titanium layer A layer can be formed.
  • the circuit pattern can be formed with high accuracy and efficiency with respect to the circuit layer having.
  • the metal member layer can be reliably formed on the titanium layer by cleaning the surface of the titanium layer.
  • a titanium layer can be formed in a circuit pattern on the aluminum layer.
  • the manufacturing method of the insulated circuit board of this invention you may implement the said ceramics / aluminum joining process after the said titanium layer formation process.
  • the aluminum plate and the ceramic substrate can be joined after the titanium layer is formed in a circuit pattern on the aluminum plate.
  • the titanium layer forming step and the ceramic / aluminum bonding step may be performed simultaneously.
  • an insulated circuit board having a circuit pattern can be efficiently manufactured by simultaneously performing the titanium layer forming step and the ceramic / aluminum bonding step.
  • the aluminum washing process which wash
  • the aluminum layer or the aluminum material and the titanium material can be reliably bonded to form a titanium layer.
  • Si is added to Al 3 Ti at the interface between the titanium layer and the aluminum layer by forming the Si enriched layer on the surface of the aluminum layer or the aluminum material on the side where the titanium layer is formed. can be dissolved, hard Al 3 Ti can suppress the is formed more than necessary, it is possible to suppress the occurrence of cracks at the bonding interface between the titanium layer and an aluminum layer.
  • the insulated circuit board of the present invention is an insulated circuit board comprising a ceramic substrate and a circuit layer having a circuit pattern disposed on one surface of the ceramic substrate, wherein the circuit layer is the ceramic substrate. It has the aluminum layer arrange
  • the titanium layer since the titanium layer is formed on the surface of the aluminum layer opposite to the ceramic substrate, the titanium layer can function as a diffusion preventing layer. Therefore, diffusion of aluminum in the aluminum layer into the element mounted on the circuit layer can be suppressed.
  • thermoelectric conversion module of the present invention is characterized in that a thermoelectric element is mounted on the circuit layer of the above-described insulated circuit board.
  • thermoelectric conversion module having this configuration since the thermoelectric element is mounted on the circuit layer formed with the titanium layer formed on the surface of the aluminum layer opposite to the ceramic substrate, the aluminum of the aluminum layer is the thermoelectric element. And the deterioration of the thermoelectric element characteristics can be suppressed.
  • a circuit for a circuit layer having an aluminum layer disposed on one surface of a ceramic substrate and a titanium layer formed on the surface of the aluminum layer opposite to the ceramic substrate. It is possible to provide an insulating circuit board manufacturing method, an insulating circuit board, and a thermoelectric conversion module that can form a pattern with high accuracy and efficiency.
  • brazing filler material is not necessarily limited to a material containing lead.
  • FIG. 1 the power module 1 using the insulated circuit board 10 which is 1st embodiment of this invention is shown.
  • the power module 1 includes an insulating circuit board 10, a semiconductor element 3 bonded to one surface (the upper surface in FIG. 1) of the insulating circuit board 10 via a first solder layer 2, and a bottom of the insulating circuit board 10. And a heat sink 41 joined via a second solder layer 42 to the side.
  • the semiconductor element 3 is made of a semiconductor material such as Si.
  • the first solder layer 2 that joins the insulating circuit board 10 and the semiconductor element 3 is, for example, a Sn—Ag, Sn—Cu, Sn—In, or Sn—Ag—Cu solder material (so-called lead-free solder). Material).
  • the heat sink 41 is for dissipating heat on the insulated circuit board 10 side.
  • the heat sink 41 is made of copper or a copper alloy, and is made of oxygen-free copper in this embodiment.
  • the second solder layer 42 that joins the insulating circuit board 10 and the heat sink 41 is, for example, a Sn—Ag, Sn—Cu, Sn—In, or Sn—Ag—Cu solder material (so-called lead-free solder material). ).
  • the insulated circuit board 10 As shown in FIGS. 1 and 2, the insulated circuit board 10 according to the present embodiment is disposed on the ceramic substrate 11 and one surface (the upper surface in FIGS. 1 and 2) of the ceramic substrate 11. A circuit layer 20 and a metal layer 30 disposed on the other surface (the lower surface in FIGS. 1 and 2) of the ceramic substrate 11 are provided.
  • the ceramic substrate 11 is made of highly insulating AlN (aluminum nitride), Si 3 N 4 (silicon nitride), Al 2 O 3 (alumina), or the like. In the present embodiment, it is composed of Si 3 N 4 excellent in strength (silicon nitride). In addition, the thickness of the ceramic substrate 11 is set within a range of 0.2 to 1.5 mm, and in this embodiment is set to 0.32 mm.
  • the circuit layer 20 is laminated with an aluminum layer 21 disposed on one surface of the ceramic substrate 11 and a titanium layer 25 on one surface of the aluminum layer 21. And a copper layer 22 (metal member layer).
  • the thickness of the aluminum layer 21 in the circuit layer 20 is set within a range of 0.1 mm or more and 1.0 mm or less, and is set to 0.4 mm in the present embodiment.
  • the thickness of the copper layer 22 in the circuit layer 20 is set within a range of 0.1 mm or more and 6.0 mm or less, and is set to 1.0 mm in the present embodiment.
  • a circuit pattern is formed as shown in FIG.
  • the metal layer 30 is laminated with an aluminum layer 31 disposed on the other surface of the ceramic substrate 11 and a titanium layer 35 on the other surface of the aluminum layer 31. And a copper layer 32 (metal member layer).
  • the thickness of the aluminum layer 31 in the metal layer 30 is set within a range of 0.1 mm to 3.0 mm, and is set to 0.4 mm in the present embodiment.
  • the thickness of the copper layer 32 in the metal layer 30 is set within a range of 0.1 mm or more and 6.0 mm or less, and is set to 1.0 mm in the present embodiment.
  • the aluminum layers 21 and 31 are formed by bonding aluminum plates 51 and 61 to one surface and the other surface of the ceramic substrate 11.
  • the aluminum plates 51 and 61 to be the aluminum layers 21 and 31 are made of aluminum (2N aluminum) having a purity of 99 mass% or more. Note that the Si content is in the range of 0.03 mass% to 1.0 mass%.
  • the copper layers 22 and 32 are formed by bonding a copper plate (metal member) made of copper or a copper alloy to one surface and the other surface of the aluminum layers 21 and 31 via the titanium layers 25 and 35. Yes.
  • the copper plates (metal members) constituting the copper layers 22 and 32 are oxygen-free copper rolled plates.
  • Al—Ti—Si layers 26 and 36 are formed at the bonding interfaces between the aluminum layers 21 and 31 and the titanium layers 25 and 35.
  • the Al—Ti—Si layers 26, 36 are formed on Al 3 Ti formed by mutual diffusion of Al atoms in the aluminum layers 21, 31 and Ti atoms in the titanium layers 25, 35. This is formed by solid solution of Si.
  • the thickness of the Al—Ti—Si layers 26 and 36 is set to 0.5 ⁇ m or more and 10 ⁇ m or less, and is 3 ⁇ m in this embodiment.
  • the Al—Ti—Si layers 26, 36 are formed on the first Al—Ti—Si layers 26 A, 36 A formed on the titanium layers 25, 35 side and the aluminum layers 21, 31 side.
  • Second Al—Ti—Si layers 26B and 36B That is, at the junction between the aluminum layers 21 and 31 and the copper layers 22 and 32, the titanium layers 25 and 35, the first Al—Ti—Si layers 26A and 36A, the second Al—Ti—Si layers 26B and 36B, Is formed.
  • the first Al—Ti—Si layers 26A and 36A and the second Al—Ti—Si layers 26B and 36B are made of an Al—Ti—Si phase in which Si is dissolved in Al 3 Ti as described above.
  • the Si concentration of the Ti—Si layers 26B and 36B is lower than the Si concentration of the first Al—Ti—Si layers 26A and 36A.
  • Si contained in the first Al—Ti—Si layers 26A and 36A and the second Al—Ti—Si layers 26B and 36B is composed of Si diffused in the aluminum layers 21 and 31 as described later. Diffusion and concentration in the Ti-Si layers 26 and 36.
  • the Si concentration of the first Al—Ti—Si layers 26A and 36A is 10 at% or more and 30 at% or less, and is 20 at% in the present embodiment.
  • the Si concentration of the second Al—Ti—Si layers 26B and 36B is 1 at% or more and 10 at% or less, and is 3 at% in this embodiment.
  • titanium materials 55 and 65 are disposed on the surfaces of the aluminum plates 51 and 61.
  • the titanium material 55 is arranged in a circuit pattern on the surface of the aluminum plate 51 to be the circuit layer 20.
  • a film forming method such as vapor deposition or ion plating may be applied.
  • the titanium material 55 can be arranged in a circuit pattern by forming a titanium film using a metal mask.
  • the titanium foil may be arranged in a circuit pattern.
  • the thickness of the titanium materials 55 and 65 is preferably in the range of 7 ⁇ m to 20 ⁇ m.
  • an aluminum plate 51 and a titanium material 55 are disposed on one surface of the ceramic substrate 11, and an aluminum plate 61 and a titanium material 65 are disposed on the other surface of the ceramic substrate 11.
  • an Al—Si brazing material is interposed between the aluminum plate 51 and the ceramic substrate 11 and between the aluminum plate 61 and the ceramic substrate 11. These are placed in a vacuum heating furnace in a state where they are pressurized in the stacking direction (load: 3 to 20 kgf / cm 2 (0.29 to 1.96 MPa)) and heated.
  • the pressure in the vacuum heating furnace is set in the range of 10 ⁇ 6 Pa to 10 ⁇ 3 Pa
  • the heating temperature is set to 600 ° C. to 640 ° C.
  • the holding time is set in the range of 30 minutes to 180 minutes. It is preferable.
  • the aluminum plate 51 and the ceramic substrate 11 and the ceramic substrate 11 and the aluminum plate 61 are joined (ceramic / aluminum joining step).
  • the aluminum plate 51 and the titanium material 55, the aluminum plate 61, and the titanium material 65 are joined, and the titanium layers 25 and 35 are formed (titanium layer formation process).
  • Al 3 Ti is formed at the bonding interface between the aluminum plate 51 and the titanium material 55 and between the aluminum plate 61 and the titanium material 65. Since the aluminum plates 51 and 61 contain Si in the range of 0.03 mass% to 1.0 mass%, Si is dissolved in Al 3 Ti, and the Al—Ti—Si layers 26, 36 described above are dissolved. Is formed.
  • a titanium layer 25 is formed in a circuit pattern on the aluminum plate 51 to be the circuit layer 20.
  • an etching process is performed on the aluminum layer 21 in which the titanium layer 25 is formed in a circuit pattern.
  • ferric chloride is used as an etching agent.
  • the concentration of ferric chloride in the etching agent (etching solution) is 35 wt% to 60 wt%, and etching can be performed at an etching temperature of 40 ° C. to 60 ° C. for 2 minutes to 20 minutes.
  • the titanium layer 25 since the titanium layer 25 is hardly etched by ferric chloride, the titanium layer 25 acts as a resist material. That is, the portion where the titanium layer 25 is formed is not etched, and only the portion where the titanium layer 25 is not formed is etched. Thereby, the aluminum layer 21 is also formed in a circuit pattern.
  • Tianium layer cleaning step S04 Next, as shown in FIG. 4, the surfaces of the titanium layers 25 and 35 on which the copper layers 22 and 32 are disposed are cleaned.
  • a mixed liquid of ammonia and hydrogen peroxide is used for cleaning the titanium layers 25 and 35.
  • an aqueous solution of 10 wt% ammonia, 3 wt% hydrogen peroxide, and 12 wt% EDTA (ethylenediaminetetraacetic acid) can be used.
  • the cleaning may be performed at a temperature of 40 ° C. to 50 ° C. for 10 minutes to 30 minutes.
  • a copper plate (metal member) is joined to the surfaces of the titanium layers 25 and 35 to form the copper layers 22 and 32.
  • a solid phase diffusion bonding method may be applied or a brazing material may be used for bonding.
  • titanium layers 25 and 35 and a copper plate (metal member) are stacked and pressed in the stacking direction (load 3 to 20 kgf / cm 2 ) in a vacuum heating furnace.
  • the pressure is in the range of 10 ⁇ 6 Pa to 10 ⁇ 3 Pa
  • the heating temperature is 600 ° C. to 650 ° C., more preferably 620 ° C. to 643 ° C.
  • the holding time is 30 minutes to 180 minutes, more preferably It is good to join within the range of 60 minutes or more and 120 minutes or less.
  • a Cu—P—Sn brazing material When joining using a brazing material, a Cu—P—Sn brazing material, a Cu—P—Sn—Ni based brazing material, a Cu—P—Sn—Fe based brazing material, a Cu—P—Sn—Mn based brazing material, A brazing foil such as a Cu—P—Sn—Cr brazing filler metal was disposed between the titanium layers 25 and 35 and the copper plate (metal member) and pressed in the stacking direction (load 3 to 20 kgf / cm 2 ).
  • the pressure in the vacuum heating furnace is in the range of 10 ⁇ 6 Pa to 10 ⁇ 3 Pa, the heating temperature is 600 ° C. to 650 ° C., more preferably 620 ° C.
  • a copper plate (metal member) is disposed and bonded on the titanium layer 25 formed in a circuit pattern.
  • a circuit pattern is formed on the circuit layer 20 in which the aluminum layer 21, the titanium layer 25, and the copper layer 22 are laminated, and the insulated circuit board 10 according to this embodiment is manufactured.
  • the titanium material arrangement in which the titanium material 55 to be the titanium layer 25 is arranged in a circuit pattern on the surface of the aluminum plate 51 Since the process S01 is provided, the titanium layer 25 can be formed in a circuit pattern on the surface of the aluminum layer 21 by the subsequent titanium layer forming process and the ceramic / aluminum bonding process S02.
  • the etching process step S03 for performing an etching process on the aluminum layer 21 on which the titanium layer 25 is formed the titanium layer 25 acts as a resist material, and the aluminum layer 21 is etched into a circuit pattern. be able to. That is, by using the titanium layer 25 as a resist material, the resist material application process, the curing process, and the peeling process can be omitted, and the etching process S03 can be performed efficiently.
  • the copper layer formation process S05 which joins a copper plate (metal member) on the titanium layer 25 formed in the circuit pattern shape, and forms the copper layer 22, it is a copper layer on the titanium layer 25. 22 can be formed in a circuit pattern. As described above, the circuit pattern can be accurately and efficiently formed on the circuit layer 20 in which the aluminum layer 21, the titanium layer 25, and the copper layer 22 are laminated.
  • the insulated circuit board which has a circuit pattern 10 can be manufactured efficiently.
  • the titanium layer cleaning process S04 which cleans the surface of the titanium layer 25 is provided before the copper layer formation process S05, the titanium layer 25 and the copper plate (Metal member) can be reliably joined, and the copper layer 22 can be reliably formed.
  • the aluminum plates 51 and 61 contain Si within the range of 0.03 mass% or more and 1.0 mass% or less, the titanium layers 25 and 35 are included. Si is dissolved in Al 3 Ti at the bonding interface between the aluminum layers 21 and 31 and the Al—Ti—Si layers 26 and 36 described above are formed. Since the Al—Ti—Si layers 26 and 36 are relatively low in hardness, the occurrence of cracks in the circuit layer 20 and the metal layer 30 when a heat cycle is applied can be suppressed.
  • the Si concentration of the first Al—Ti—Si layers 26A, 36A formed on the titanium layers 25, 35 side is the Si concentration of the second Al—Ti—Si layers 26B, 36B formed on the aluminum layers 21, 31 side. Therefore, the first Al—Ti—Si layers 26A and 36A having a high Si concentration suppress the Ti atoms from diffusing toward the aluminum layers 21 and 31, thereby reducing the thickness of the Al—Ti—Si layers 26 and 36. Can be thinned. Further, by reducing the thickness of the Al—Ti—Si layers 26 and 36 in this way, cracks occur at the joints between the aluminum layers 21 and 31 and the copper layers 22 and 32 when a heat cycle is applied. This can be suppressed.
  • the Si concentration contained in the second Al—Ti—Si layers 26B and 36B formed on the aluminum layers 21 and 31 side is 1 at% or more and 10 at% or less, Al atoms are on the titanium layers 25 and 35 side. Excessive diffusion is suppressed, and the thickness of the second Al—Ti—Si layers 26B and 36B can be reduced.
  • the Si concentration in the second Al—Ti—Si layers 26B and 36B is more preferably 1 at% or more and 10 at% or less, but is not limited thereto.
  • the Si concentration contained in the first Al—Ti—Si layers 26A and 36A formed on the titanium layers 25 and 35 side is 10 at% or more and 30 at% or less, Ti atoms are on the aluminum layers 21 and 31 side. Therefore, the first Al—Ti—Si layers 26A and 36A can be reduced in thickness.
  • the Si concentration in the first Al—Ti—Si layers 26A and 36A is more preferably 10 at% or more and 30 at% or less, but is not limited thereto.
  • the copper layers 22 and 32 having a relatively large deformation resistance are formed on the surface of the circuit layer 20 and the metal layer 30, the circuit layer 20 and the metal layer when the heat cycle is applied. 30, the deformation of the surface of the first solder layer 2 that joins the semiconductor element 3 and the circuit layer 20 and the second solder layer 42 that joins the heat sink 41 and the metal layer 30 can be prevented from cracking. , The bonding reliability can be improved. Further, since the copper layers 22 and 32 having good thermal conductivity are formed on the surface of the circuit layer 20 and the metal layer 30, the heat from the semiconductor element 3 is spread in the surface direction and efficiently transmitted to the heat sink 41 side. can do.
  • FIG. 6 shows a power module 101 including an insulated circuit board 110 according to the second embodiment of the present invention.
  • the power module 101 includes an insulating circuit board 110, a semiconductor element 3 bonded to one surface (upper surface in FIG. 6) of the insulating circuit board 110 via a solder layer 2, and a lower side of the insulating circuit board 110.
  • a heat sink 141 bonded thereto.
  • the heat sink 141 is for dissipating heat on the insulated circuit board 110 side.
  • the heat sink 141 is made of aluminum or an aluminum alloy, and in this embodiment is made of an A6063 alloy.
  • the insulated circuit board 110 and the heat sink 141 are joined using a brazing material.
  • the insulating circuit substrate 110 is disposed on the ceramic substrate 11, the circuit layer 120 disposed on one surface of the ceramic substrate 11, and the other surface of the ceramic substrate 11. And a metal layer 130.
  • the circuit layer 120 is laminated with an aluminum layer 121 disposed on one surface of the ceramic substrate 11 and a titanium layer 125 on one surface of the aluminum layer 121. And a copper layer 122 (metal member layer).
  • the thickness of the aluminum layer 121 in the circuit layer 120 is set within a range of 0.1 mm or more and 1.0 mm or less, and is set to 0.6 mm in the present embodiment.
  • the thickness of the copper layer 122 in the circuit layer 120 is set within a range of 0.1 mm or more and 6.0 mm or less, and is set to 1.5 mm in the present embodiment.
  • a circuit pattern is formed as shown in FIG.
  • the aluminum layer 121 is formed by joining an aluminum plate 151 to one surface of the ceramic substrate 11.
  • the aluminum plate 151 to be the aluminum layer 121 is made of aluminum (2N aluminum) having a purity of 99 mass% or more.
  • the Si content is in the range of 0.03 mass% to 1.0 mass%.
  • the copper layer 122 is formed by bonding a copper plate (metal member) made of copper or a copper alloy to one surface of the aluminum layer 121 via a titanium layer 125.
  • the copper plate (metal member) constituting the copper layer 122 is an oxygen-free copper rolled plate.
  • Al—Ti—Si layer in which Si is dissolved in Al 3 Ti is formed as in the first embodiment.
  • Al 3 Ti is formed by the mutual diffusion of Al atoms in the aluminum layer 121 and Ti atoms in the titanium layer 125, and the Si in the aluminum layer 121 is formed by the Al 3 Ti. It is formed by solid solution.
  • the metal layer 130 is formed by bonding an aluminum plate 161 to one surface of the ceramic substrate 11 as shown in FIG.
  • the metal layer 130 is formed by joining rolled sheets of aluminum (4N aluminum) having a purity of 99.99 mass% or more.
  • the thickness of the aluminum plate 161 to be joined is set within a range of 0.1 mm to 1.0 mm, and is set to 0.6 mm in the present embodiment.
  • an aluminum plate 151 is laminated on one surface of the ceramic substrate 11 via an Al—Si based brazing foil (not shown). Further, an aluminum plate 161 is laminated on the other surface of the ceramic substrate 11 via a brazing material foil (not shown).
  • the laminated aluminum plate 151, ceramic substrate 11 and aluminum plate 161 are placed in a vacuum heating furnace and heated in a state of being pressurized (load 3 to 20 kgf / cm 2 ) in the lamination direction. As a result, the aluminum plate 151 and the ceramic substrate 11 and the ceramic substrate 11 and the aluminum plate 161 are joined to form the aluminum layer 121 and the metal layer 130.
  • the aluminum layer 121 can be cleaned, for example, using a 5 wt% to 10 wt% sulfuric acid aqueous solution or a 5 wt% to 10 wt% nitric acid aqueous solution at a temperature of 20 ° C. to 30 ° C. for a time of 30 seconds to 60 seconds.
  • a titanium material 155 is arranged in a circuit pattern on the surface of the aluminum layer 121.
  • a film forming method such as vapor deposition or ion plating may be applied.
  • the titanium material 155 can be arranged in a circuit pattern by forming a titanium film using a metal mask.
  • the titanium foil may be arranged in a circuit pattern.
  • the thickness of the titanium material 155 is preferably in the range of 7 ⁇ m or more and 20 ⁇ m or less.
  • Tianium layer forming step S104 Next, as shown in FIG. 8 and FIG. 9, with the titanium material 155 disposed on the surface of the aluminum layer 121, vacuum heating is performed in a state where these are pressed in the stacking direction (load 3 to 20 kgf / cm 2 ). Place in the furnace and heat.
  • the pressure in the vacuum heating furnace is set in the range of 10 ⁇ 6 Pa to 10 ⁇ 3 Pa
  • the heating temperature is set to 600 ° C. to 640 ° C.
  • the holding time is set in the range of 30 minutes to 180 minutes. It is preferable.
  • the aluminum layer 121 and the titanium material 155 are joined, and the titanium layer 125 is formed in a circuit pattern.
  • the Al—Ti—Si layer described above is formed at the bonding interface between the aluminum layer 121 and the titanium layer 125.
  • Tianium layer cleaning step S106 Next, as shown in FIG. 8, the surface of the titanium layer 125 on which the copper layer 122 is disposed is cleaned.
  • the cleaning of the titanium layer 125 can be performed as in the first embodiment.
  • a copper plate (metal member) is bonded to the surface of the titanium layer 125 formed in a circuit pattern to form the copper layer 122.
  • the solid phase diffusion bonding method may be applied or the brazing material may be bonded as in the first embodiment. .
  • a circuit pattern is formed on the circuit layer 120 in which the aluminum layer 121, the titanium layer 125, and the copper layer 122 are laminated, and the insulated circuit board 110 according to this embodiment is manufactured.
  • the titanium material disposing step S103, the titanium layer forming step S104, and the etching process step S105 as in the first embodiment.
  • the copper layer forming step S107 the circuit pattern can be accurately and efficiently formed on the circuit layer 120 in which the aluminum layer 121, the titanium layer 125, and the copper layer 122 are laminated. Can do.
  • the titanium layer 125 is used as a resist material in the etching process S105, the resist material application process and the peeling process can be omitted, and the etching process S105 can be performed efficiently.
  • thermoelectric conversion module 201 provided with the insulated circuit board 210 which concerns on 3rd embodiment of this invention is shown.
  • the thermoelectric conversion module 201 includes a thermoelectric element 203 and an insulating circuit board 210 disposed on one end side and the other end side of the thermoelectric element 203.
  • the thermoelectric element 203 is bonded to the circuit layer 220 of the insulating circuit board 210 via the bonding layer 202.
  • the bonding layer 202 is a fired body of silver paste containing silver particles.
  • the insulated circuit board 210 includes a ceramic substrate 11 and a circuit layer 220 disposed on one surface of the ceramic substrate 11.
  • the circuit layer 220 includes an aluminum layer 221 disposed on one surface of the ceramic substrate 11 and a titanium layer 225 formed on one surface of the aluminum layer 221.
  • the thickness of the aluminum layer 221 in the circuit layer 220 is set within a range of 0.1 mm to 1.0 mm, and is set to 0.6 mm in the present embodiment.
  • a circuit pattern is formed as shown in FIG.
  • the aluminum layer 221 is formed by bonding an aluminum plate 251 to one surface of the ceramic substrate 11.
  • the aluminum plate 251 serving as the aluminum layer 221 is made of aluminum (4N aluminum) having a purity of 99.99 mass% or more. Note that a Si concentrated layer in which the Si content is in the range of 0.03 mass% to 1.0 mass% is formed at the interface of the aluminum layer 221 on the titanium layer 225 side.
  • an Al—Ti—Si layer in which Si is dissolved in Al 3 Ti is formed at the bonding interface between the aluminum layer 221 and the titanium layer 225. Yes.
  • the Al-Ti-Si layer, and the Al atoms of the aluminum layer 221, together with the Al 3 Ti is formed by and the Ti atoms in the titanium layer 225 to interdiffusion, Si of Si concentrated layer, the Al 3 It is formed by dissolving in Ti.
  • Si concentrated layer forming step S201 First, a Si concentrated layer containing Si within a range of 0.03 mass% to 1.0 mass% on one surface of an aluminum plate 251 made of aluminum (4N aluminum) having a purity of 99.99 mass% or higher. Form. Specifically, a Si material 252 containing Si (for example, an Al—Si brazing material) is disposed on one surface of the aluminum plate 251 and heat-treated, so that Si of the Si material is moved to the aluminum plate 251 side. And the above-described Si concentrated layer is formed.
  • the Si concentration was obtained by measuring five points on the surface on which the titanium layer is formed by quantitative analysis using EPMA (electron beam microanalyzer), and taking the average value.
  • the Si concentration is the concentration when the total amount of Al and Si is 100.
  • a titanium material 255 is arranged in a circuit pattern on one surface of the aluminum plate 151 (the surface on which the Si concentrated layer is formed).
  • a film forming method such as vapor deposition or ion plating may be applied.
  • the titanium material 255 can be arranged in a circuit pattern.
  • the titanium foil may be arranged in a circuit pattern.
  • the thickness of the titanium material 255 is preferably in the range of 7 ⁇ m to 20 ⁇ m.
  • a titanium material 255 is disposed on the surface of the aluminum plate 251, and is placed in a vacuum heating furnace in a state of being pressurized in the stacking direction (load 3 to 20 kgf / cm 2 ). And heat.
  • the pressure in the vacuum heating furnace is set in the range of 10 ⁇ 6 Pa to 10 ⁇ 3 Pa
  • the heating temperature is set to 600 ° C. to 640 ° C.
  • the holding time is set in the range of 30 minutes to 180 minutes. It is preferable.
  • the aluminum plate 251 and the titanium material 255 are joined, and the titanium layer 225 is formed in a circuit pattern.
  • the Al—Ti—Si layer described above is formed at the bonding interface between the aluminum plate 251 and the titanium layer 225.
  • an aluminum plate 251 on which a titanium layer 225 is formed is laminated on one surface of the ceramic substrate 11 with an Al—Si based brazing foil (not shown). To do.
  • the laminated aluminum plate 251 and the ceramic substrate 11 are placed in a vacuum heating furnace and heated while being pressurized (load 3 to 20 kgf / cm 2 ) in the lamination direction. Thereby, the aluminum plate 251 and the ceramic substrate 11 are joined, and the aluminum layer 221 is formed.
  • a circuit pattern is formed on the circuit layer 220 in which the aluminum layer 221 and the titanium layer 225 are laminated, and the insulated circuit board 210 according to this embodiment is manufactured.
  • thermoelectric conversion module 201 shown in FIG. 10 is manufactured.
  • the aluminum layer A circuit pattern can be accurately and efficiently formed on the circuit layer 220 in which the layer 221 and the titanium layer 225 are stacked. Further, since the titanium layer 225 is used as a resist material in the etching process S205, the resist material application process and the peeling process can be omitted, and the etching process S205 can be performed efficiently.
  • the aluminum layer 221 of the circuit layer 220 is made of aluminum (4N aluminum) having a purity of 99.99 mass% or more.
  • an Al—Ti—Si layer can be formed between the aluminum layer 221 and the titanium layer 225 as in the first embodiment and the second embodiment.
  • the titanium layer 225 is formed on the surface of the aluminum layer 221 opposite to the ceramic substrate 11, so that the titanium layer 225 is diffused. It can function as a prevention layer. Therefore, diffusion of aluminum in the aluminum layer 221 into the thermoelectric element 203 mounted on the circuit layer 211 can be suppressed. Thereby, deterioration of the characteristics of the thermoelectric element 203 can be suppressed.
  • the solderability is good and the bonding reliability with a semiconductor element or a heat sink can be improved.
  • the nickel layer is formed by solid phase diffusion bonding, the masking process performed when forming the Ni plating film by electroless plating or the like is unnecessary, and thus the manufacturing cost can be reduced.
  • the thickness of the nickel layer be 1 ⁇ m or more and 30 ⁇ m or less. If the thickness of the nickel layer is less than 1 ⁇ m, the effect of improving the reliability of bonding to the semiconductor element or the heat sink may be lost. If the thickness exceeds 30 ⁇ m, the nickel layer becomes a thermal resistor and efficiently transfers heat. There is a risk that it will not be possible.
  • the nickel layer is formed by solid phase diffusion bonding, the solid phase diffusion bonding can be formed under the same conditions as when the copper layer is formed.
  • the silver oxide is reduced.
  • the silver layer are connected, that is, the same kind of metal is bonded to each other, so that the bonding reliability can be improved.
  • the thickness of the silver layer is desirably 1 ⁇ m or more and 20 ⁇ m or less. If the thickness of the silver layer is less than 1 ⁇ m, the effect of improving the bonding reliability with the semiconductor element or the heat sink may be lost.
  • the thickness exceeds 20 ⁇ m, the effect of improving the bonding reliability is not observed, and the cost is reduced. Incurs an increase.
  • the solid phase diffusion bonding can be formed under the same conditions as when the copper layer is formed.
  • an aluminum plate used as an aluminum layer it is 2N aluminum whose purity is 99 mass% or more, and Si content is the range of 0.03 mass% or more and 1.0 mass% or less.
  • the present invention is not limited to this, and other aluminum materials may be used.
  • an aluminum material that does not contain Si such as 4N aluminum having a purity of 99.99 mass% or more
  • a titanium layer is formed in advance in the aluminum material.
  • the surface Si concentration may be adjusted to 0.03 mass% to 1.0 mass%.
  • the Si concentration is an average value obtained by measuring the surface on which the titanium layer is formed at five points by quantitative analysis of EPMA.
  • the Si concentration is the concentration when the total amount of Al and Si is 100.
  • a circuit pattern can be accurately and efficiently formed on a circuit layer.
  • the insulated circuit board of this invention is suitable for semiconductor devices, such as LED and a power module, and a thermoelectric conversion module.

Abstract

A method for manufacturing insulated circuit board according to the present invention comprises: a ceramic/aluminum joining step for forming an aluminum layer by joining an aluminum material to a ceramic substrate; a titanium material arranging step for arranging a titanium material on the surface of the aluminum layer or the aluminum material in a circuit pattern shape; a titanium layer forming step for forming a titanium layer by performing heat treatment in the state of the titanium material being stacked on the surface of the aluminum layer or the aluminum material; and an etching step for etching the aluminum layer on which the titanium layer has been formed into a circuit pattern shape.

Description

絶縁回路基板の製造方法、絶縁回路基板、熱電変換モジュールInsulated circuit board manufacturing method, insulated circuit board, thermoelectric conversion module
　この発明は、セラミックス基板と、このセラミックス基板の一方の面に配設された回路パターンを有する回路層と、を備えた絶縁回路基板の製造方法、絶縁回路基板、熱電変換モジュールに関する。
　本願は、２０１６年６月２３日に日本に出願された特願２０１６－１２４６６７号、および２０１７年６月２１日に日本に出願された特願２０１７－１２１７４１号に基づき優先権を主張し、その内容をここに援用する。 The present invention relates to a method for manufacturing an insulated circuit board, a insulated circuit board, and a thermoelectric conversion module including a ceramic substrate and a circuit layer having a circuit pattern disposed on one surface of the ceramic substrate.
The present application claims priority based on Japanese Patent Application No. 2016-124667 filed in Japan on June 23, 2016, and Japanese Patent Application No. 2017-121741 filed in Japan on June 21, 2017. The contents are incorporated herein.
　ＬＥＤ、パワーモジュール等の半導体装置や、熱電変換モジュールは、導電材料からなる回路層の上に半導体素子又は熱電素子が接合された構造とされている。
　風力発電、電気自動車、ハイブリッド自動車等を制御するために用いられる大電力制御用のパワー半導体素子においては、発熱量が多いことから、これを搭載する基板としては、例えばＡｌＮ（窒化アルミ）、Ａｌ２Ｏ３（アルミナ）などからなるセラミックス基板と、このセラミックス基板の一方の面に導電性の優れた金属板を接合して形成した回路層と、を備えた絶縁回路基板が、従来から広く用いられている。なお、絶縁回路基板としては、セラミックス基板の他方の面に金属層を形成したものも提供されている。 Semiconductor devices such as LEDs and power modules and thermoelectric conversion modules have a structure in which a semiconductor element or a thermoelectric element is bonded on a circuit layer made of a conductive material.
In power semiconductor elements for large power control used to control wind power generation, electric vehicles, hybrid vehicles, etc., the amount of heat generated is large. Therefore, for example, AlN (aluminum nitride), Al 2. Description of the Related Art Conventionally, an insulating circuit board including a ceramic substrate made of 2 O 3 (alumina) and a circuit layer formed by bonding a metal plate having excellent conductivity to one surface of the ceramic substrate has been widely used. It has been. In addition, as an insulating circuit board, a ceramic substrate having a metal layer formed on the other surface is also provided.
　例えば、特許文献１に示すパワーモジュールは、セラミックス基板の一方の面及び他方の面にＡｌからなる回路層及び金属層が形成された絶縁回路基板と、この回路層上にはんだ材を介して接合された半導体素子と、を備えた構造とされている。
　そして、絶縁回路基板の他方の面側には、ヒートシンクが接合されており、半導体素子から絶縁回路基板側に伝達された熱を、ヒートシンクを介して外部へ放散する構成とされている。 For example, the power module shown in Patent Document 1 is bonded to an insulating circuit board in which a circuit layer and a metal layer made of Al are formed on one surface and the other surface of a ceramic substrate, and a solder material is bonded to the circuit layer. And a semiconductor device that has been manufactured.
A heat sink is bonded to the other surface side of the insulating circuit board, and the heat transmitted from the semiconductor element to the insulating circuit board side is dissipated to the outside through the heat sink.
　ところで、特許文献１に記載されたパワーモジュールのように、回路層及び金属層をＡｌで構成した場合には、表面にＡｌの酸化皮膜が形成されるため、はんだ材によっては半導体素子やヒートシンクを直接接合することができない。
　そこで、従来、例えば特許文献２に開示されているように、回路層及び金属層の表面に無電解めっき等によってＮｉめっき膜を形成した上で、半導体素子やヒートシンクをはんだ接合している。
　また、特許文献３には、はんだ材の代替として、酸化銀粒子と有機物からなる還元剤とを含む酸化銀ペーストを用いて、回路層と半導体素子、及び、金属層とヒートシンクとを接合する技術が提案されている。 By the way, when the circuit layer and the metal layer are made of Al as in the power module described in Patent Document 1, since an oxide film of Al is formed on the surface, depending on the solder material, a semiconductor element or a heat sink may be used. Cannot be joined directly.
Therefore, conventionally, as disclosed in, for example, Patent Document 2, a Ni plating film is formed on the surface of a circuit layer and a metal layer by electroless plating or the like, and then a semiconductor element and a heat sink are soldered.
Patent Document 3 discloses a technique for joining a circuit layer and a semiconductor element, and a metal layer and a heat sink by using a silver oxide paste containing silver oxide particles and a reducing agent made of an organic substance as an alternative to a solder material. Has been proposed.
　しかしながら、特許文献２に記載されたように、回路層表面及び金属層表面にＮｉめっき膜を形成した絶縁回路基板においては、半導体素子及びヒートシンクを接合するまでの過程においてＮｉめっき膜の表面が酸化等によって劣化し、はんだ材を介して接合した半導体素子及びヒートシンクとの接合信頼性が低下するおそれがあった。また、Ｎｉめっき工程では、不要な領域にＮｉめっきが形成されて電食等のトラブルが発生しないように、マスキング処理を行うことがある。このように、マスキング処理をした上でめっき処理をする場合、回路層表面及び金属層表面にＮｉめっき膜を形成する工程に多大な労力が必要となり、パワーモジュールの製造コストが大幅に増加してしまうといった問題があった。
　また、特許文献３に記載されたように、酸化銀ペーストを用いて回路層と半導体素子及び金属層とヒートシンクとを接合する場合には、Ａｌと酸化銀ペーストの焼成体との接合性が悪いために、予め回路層表面及び金属層表面にＡｇ下地層を形成する必要があった。 However, as described in Patent Document 2, in the insulated circuit board in which the Ni plating film is formed on the circuit layer surface and the metal layer surface, the surface of the Ni plating film is oxidized in the process until the semiconductor element and the heat sink are joined. There is a possibility that the reliability of bonding between the semiconductor element and the heat sink bonded via the solder material may be deteriorated due to the deterioration due to the above. Further, in the Ni plating process, masking may be performed so that Ni plating is formed in an unnecessary region and troubles such as electrolytic corrosion do not occur. As described above, when plating is performed after masking, a great amount of labor is required for the process of forming the Ni plating film on the surface of the circuit layer and the surface of the metal layer, which greatly increases the manufacturing cost of the power module. There was a problem such as.
In addition, as described in Patent Document 3, when a circuit layer, a semiconductor element, a metal layer, and a heat sink are bonded using a silver oxide paste, the bonding property between the sintered body of Al and the silver oxide paste is poor. Therefore, it is necessary to previously form an Ag underlayer on the circuit layer surface and the metal layer surface.
　そこで、特許文献４には、回路層を、アルミニウム層と、銅、ニッケル又は銀からなる金属部材層との積層構造とした絶縁回路基板が提案されている。この絶縁回路基板は、アルミニウム層と金属部材層とがチタン層を介して接合された構造とされている。 Therefore, Patent Document 4 proposes an insulated circuit board in which the circuit layer has a laminated structure of an aluminum layer and a metal member layer made of copper, nickel, or silver. This insulated circuit board has a structure in which an aluminum layer and a metal member layer are bonded via a titanium layer.
　また、熱電変換モジュールにおいては、回路層がアルミニウム等で構成されていた場合には、アルミニウムが熱電素子に拡散してしまい、熱電素子の特性が劣化してしまうおそれがあった。このため、アルミニウムが熱電素子に拡散することを防止するために、回路層の表面に、拡散防止層としてチタン層を形成することが考えられる。 Further, in the thermoelectric conversion module, when the circuit layer is made of aluminum or the like, aluminum diffuses into the thermoelectric element, which may deteriorate the characteristics of the thermoelectric element. For this reason, in order to prevent aluminum from diffusing into the thermoelectric element, it is conceivable to form a titanium layer as a diffusion preventing layer on the surface of the circuit layer.
特許第３１７１２３４号公報Japanese Patent No. 3171234 特開２００４－１７２３７８号公報JP 2004-172378 A 特開２００８－２０８４４２号公報JP 2008-208442 A 特許第５７２５０６０号公報Japanese Patent No. 5725060
　ところで、特許文献４に記載された絶縁回路基板や、回路層の表面にチタン層を形成した絶縁回路基板においては、回路層に回路パターンを形成するためにエッチング処理を行うことがある。
　ここで、銅やアルミニウムをエッチング処理する際に用いられるエッチング剤としては、例えば塩化第二鉄が用いられる。しかしながら、上述のエッチング剤においてはチタン層をエッチングすることができないため、チタン層を有する回路層をエッチング処理して回路パターンを形成することができないといった問題があった。 By the way, in the insulated circuit board described in Patent Document 4 and the insulated circuit board in which the titanium layer is formed on the surface of the circuit layer, an etching process may be performed to form a circuit pattern in the circuit layer.
Here, for example, ferric chloride is used as an etchant used when etching copper or aluminum. However, since the above-mentioned etching agent cannot etch the titanium layer, there is a problem that the circuit pattern having the titanium layer cannot be etched to form a circuit pattern.
　この発明は、前述した事情に鑑みてなされたものであって、セラミックス基板の一方の面に配設されたアルミニウム層と、このアルミニウム層の前記セラミックス基板とは反対側の面に形成されたチタン層とを有する回路層に対して、回路パターンを精度良く、かつ、効率良く形成することができる絶縁回路基板の製造方法、絶縁回路基板、および熱電変換モジュールを提供することを目的とする。 The present invention has been made in view of the circumstances described above, and includes an aluminum layer disposed on one surface of a ceramic substrate and titanium formed on the surface of the aluminum layer opposite to the ceramic substrate. An object of the present invention is to provide an insulating circuit board manufacturing method, an insulating circuit board, and a thermoelectric conversion module capable of forming a circuit pattern with high accuracy and efficiency with respect to a circuit layer having a layer.
　前述の課題を解決するために、本発明の絶縁回路基板の製造方法は、セラミックス基板と、このセラミックス基板の一方の面に配設された回路パターンを有する回路層と、を備えた絶縁回路基板の製造方法であって、前記回路層は、前記セラミックス基板の一方の面に配設されたアルミニウム層と、このアルミニウム層の前記セラミックス基板とは反対側の面に形成されたチタン層と、を有しており、アルミニウム材を前記セラミックス基板に接合してアルミニウム層を形成するセラミックス／アルミニウム接合工程と、前記アルミニウム層又は前記アルミニウム材の表面に、チタン層となるチタン材を、前記回路パターン状に配設するチタン材配設工程と、前記アルミニウム層又は前記アルミニウム材の表面に前記チタン材を積層した状態で熱処理を行い、前記チタン層を形成するチタン層形成工程と、前記チタン層が形成された前記アルミニウム層を前記回路パターン状にエッチングするエッチング処理工程と、を備えていることを特徴としている。 In order to solve the above-described problems, an insulating circuit board manufacturing method according to the present invention includes an insulating circuit board including a ceramic substrate and a circuit layer having a circuit pattern disposed on one surface of the ceramic substrate. The circuit layer includes an aluminum layer disposed on one surface of the ceramic substrate, and a titanium layer formed on a surface of the aluminum layer opposite to the ceramic substrate. A ceramic / aluminum bonding step in which an aluminum material is bonded to the ceramic substrate to form an aluminum layer, and a titanium material to be a titanium layer is formed on the surface of the aluminum layer or the aluminum material. The titanium material disposing step disposed on the surface, and the titanium layer laminated on the surface of the aluminum layer or the aluminum material In a heat treatment, a titanium layer forming step of forming the titanium layer, is characterized in that the aluminum layer wherein the titanium layer is formed and a, and an etching process for etching the circuit pattern.
　この構成の絶縁回路基板の製造方法によれば、チタン材配設工程及びチタン層形成工程を備えているので、アルミニウム層の表面にチタン層を回路パターン状に形成することができる。
　また、前記チタン層が回路パターン状に形成された前記アルミニウム層に対してエッチング処理を行うエッチング処理工程を備えているので、チタン層がレジスト材として作用し、アルミニウム層を回路パターン状にエッチングすることができる。
　このように、チタン層をレジスト材として使用することにより、レジスト材の塗布工程、硬化工程や剥離工程を省略することができ、エッチング処理工程を効率良く行うことができる。
　以上により、セラミックス基板の一方の面に配設されたアルミニウム層と、このアルミニウム層の前記セラミックス基板とは反対側の面に形成されたチタン層を有する回路層に対して、回路パターンを精度良く、かつ、効率良く形成することができる。 According to the method for manufacturing an insulated circuit board having this configuration, since the titanium material disposing step and the titanium layer forming step are provided, the titanium layer can be formed in a circuit pattern on the surface of the aluminum layer.
In addition, since the aluminum layer having the titanium layer formed into a circuit pattern is provided with an etching process step, the titanium layer acts as a resist material, and the aluminum layer is etched into a circuit pattern. be able to.
Thus, by using the titanium layer as a resist material, the resist material application process, the curing process and the peeling process can be omitted, and the etching process process can be performed efficiently.
As described above, the circuit pattern is accurately applied to the circuit layer having the aluminum layer disposed on one surface of the ceramic substrate and the titanium layer formed on the surface of the aluminum layer opposite to the ceramic substrate. And can be formed efficiently.
　ここで、本発明の絶縁回路基板の製造方法においては、前記回路層は、前記チタン層の前記アルミニウム層とは反対側の面に積層された銅、ニッケルまたは銀からなる金属部材層と、を有しており、前記エッチング処理工程後に、回路パターン状に形成された前記チタン層の表面に前記金属部材層を形成する金属部材層形成工程を備えていてもよい。
　なお、本発明において、金属部材層は、銅又は銅合金、ニッケル又はニッケル合金、もしくは銀又は銀合金で構成されている。 Here, in the method for manufacturing an insulated circuit board according to the present invention, the circuit layer includes a metal member layer made of copper, nickel, or silver laminated on a surface of the titanium layer opposite to the aluminum layer. And a metal member layer forming step of forming the metal member layer on the surface of the titanium layer formed in a circuit pattern after the etching treatment step.
In the present invention, the metal member layer is made of copper or copper alloy, nickel or nickel alloy, or silver or silver alloy.
　この場合、回路パターン状に形成された前記チタン層の上に前記金属部材層を形成する金属部材層形成工程を有しているので、チタン層の上に、銅、ニッケルまたは銀からなる金属部材層を形成することができる。
　以上により、セラミックス基板の一方の面に配設されたアルミニウム層と、このアルミニウム層の前記セラミックス基板とは反対側の面にチタン層を介して積層された銅、ニッケルまたは銀からなる金属部材層と、を有する回路層に対して、回路パターンを精度良く、かつ、効率良く形成することができる。 In this case, since it has the metal member layer formation process which forms the said metal member layer on the said titanium layer formed in the circuit pattern shape, the metal member which consists of copper, nickel, or silver on a titanium layer A layer can be formed.
As described above, an aluminum layer disposed on one surface of the ceramic substrate, and a metal member layer made of copper, nickel, or silver laminated on the surface of the aluminum layer opposite to the ceramic substrate via the titanium layer. The circuit pattern can be formed with high accuracy and efficiency with respect to the circuit layer having.
　また、本発明の絶縁回路基板の製造方法においては、前記金属部材層形成工程の前に、前記チタン層の表面を洗浄するチタン層洗浄工程を備えていることが好ましい。
　この場合、前記チタン層の表面を洗浄することにより、前記チタン層の上に金属部材層を確実に形成することができる。 Moreover, in the manufacturing method of the insulated circuit board of this invention, it is preferable to provide the titanium layer washing | cleaning process which wash | cleans the surface of the said titanium layer before the said metal member layer formation process.
In this case, the metal member layer can be reliably formed on the titanium layer by cleaning the surface of the titanium layer.
　さらに、本発明の絶縁回路基板の製造方法においては、前記セラミックス／アルミニウム接合工程の後に、前記チタン材配設工程及び前記チタン層形成工程を実施してもよい。
　この場合、セラミックス基板とアルミニウム板とを接合してアルミニウム層を形成した後に、このアルミニウム層の上にチタン層を回路パターン状に形成することができる。 Furthermore, in the manufacturing method of the insulated circuit board of this invention, you may implement the said titanium material arrangement | positioning process and the said titanium layer formation process after the said ceramics / aluminum joining process.
In this case, after a ceramic substrate and an aluminum plate are joined to form an aluminum layer, a titanium layer can be formed in a circuit pattern on the aluminum layer.
　また、本発明の絶縁回路基板の製造方法においては、前記チタン層形成工程の後に、前記セラミックス／アルミニウム接合工程を実施してもよい。
　この場合、アルミニウム板の上にチタン層を回路パターン状に形成した上で、アルミニウム板とセラミックス基板とを接合することができる。 Moreover, in the manufacturing method of the insulated circuit board of this invention, you may implement the said ceramics / aluminum joining process after the said titanium layer formation process.
In this case, the aluminum plate and the ceramic substrate can be joined after the titanium layer is formed in a circuit pattern on the aluminum plate.
　さらに、本発明の絶縁回路基板の製造方法においては、前記チタン層形成工程と、前記セラミックス／アルミニウム接合工程と、を同時に実施してもよい。
　この場合、前記チタン層形成工程と、前記セラミックス／アルミニウム接合工程と、を同時に実施することで、回路パターンを有する絶縁回路基板を効率良く製造することができる。 Furthermore, in the method for manufacturing an insulated circuit board of the present invention, the titanium layer forming step and the ceramic / aluminum bonding step may be performed simultaneously.
In this case, an insulated circuit board having a circuit pattern can be efficiently manufactured by simultaneously performing the titanium layer forming step and the ceramic / aluminum bonding step.
　また、本発明の絶縁回路基板の製造方法においては、前記チタン材配設工程の前に、前記アルミニウム層又は前記アルミニウム材の表面を洗浄するアルミニウム洗浄工程を備えていることが好ましい。
　この場合、前記アルミニウム層又は前記アルミニウム材の表面を洗浄することにより、前記アルミニウム層又は前記アルミニウム材とチタン材とを確実に接合してチタン層を形成することができる。 Moreover, in the manufacturing method of the insulated circuit board of this invention, it is preferable to provide the aluminum washing process which wash | cleans the surface of the said aluminum layer or the said aluminum material before the said titanium material arrangement | positioning process.
In this case, by cleaning the surface of the aluminum layer or the aluminum material, the aluminum layer or the aluminum material and the titanium material can be reliably bonded to form a titanium layer.
　また、本発明の絶縁回路基板の製造方法においては、前記チタン材配設工程の前に、前記アルミニウム層又は前記アルミニウム材のうち前記チタン層が形成される側の面に、Ｓｉを０．０３ｍａｓｓ％以上１．０ｍａｓｓ％以下の範囲内で含有するＳｉ濃化層を形成するＳｉ濃化層形成工程を備えていることが好ましい。
　この場合、前記アルミニウム層又は前記アルミニウム材のうち前記チタン層が形成される側の面に上述のＳｉ濃化層を形成することにより、チタン層とアルミニウム層との界面においてＡｌ３ＴｉにＳｉを固溶させることができ、硬いＡｌ３Ｔｉが必要以上に形成されることを抑制でき、チタン層とアルミニウム層との接合界面における割れの発生を抑制することができる。 Moreover, in the manufacturing method of the insulated circuit board of this invention, before the said titanium material arrangement | positioning process, 0.03 mass of Si is given to the surface by which the said titanium layer is formed among the said aluminum layer or the said aluminum material. It is preferable to include a Si concentrated layer forming step of forming a Si concentrated layer contained within a range of not less than% and not more than 1.0 mass%.
In this case, Si is added to Al 3 Ti at the interface between the titanium layer and the aluminum layer by forming the Si enriched layer on the surface of the aluminum layer or the aluminum material on the side where the titanium layer is formed. can be dissolved, hard Al 3 Ti can suppress the is formed more than necessary, it is possible to suppress the occurrence of cracks at the bonding interface between the titanium layer and an aluminum layer.
　本発明の絶縁回路基板は、セラミックス基板と、このセラミックス基板の一方の面に配設された回路パターンを有する回路層と、を備えた絶縁回路基板であって、前記回路層は、前記セラミックス基板の一方の面に配設されたアルミニウム層と、このアルミニウム層の前記セラミックス基板とは反対側の面に形成されたチタン層と、を有していることを特徴としている。
　この構成の絶縁回路基板においては、アルミニウム層の前記セラミックス基板とは反対側の面にチタン層が形成されているので、このチタン層を拡散防止層として機能させることができる。よって、回路層に搭載された素子に、アルミニウム層のアルミニウムが拡散することを抑制することができる。 The insulated circuit board of the present invention is an insulated circuit board comprising a ceramic substrate and a circuit layer having a circuit pattern disposed on one surface of the ceramic substrate, wherein the circuit layer is the ceramic substrate. It has the aluminum layer arrange | positioned by one side of this, and the titanium layer formed in the surface on the opposite side to the said ceramic substrate of this aluminum layer, It is characterized by the above-mentioned.
In the insulated circuit board having this configuration, since the titanium layer is formed on the surface of the aluminum layer opposite to the ceramic substrate, the titanium layer can function as a diffusion preventing layer. Therefore, diffusion of aluminum in the aluminum layer into the element mounted on the circuit layer can be suppressed.
　本発明の熱電変換モジュールは、上述の絶縁回路基板の前記回路層上に熱電素子が搭載されたことを特徴としている。
　この構成の熱電変換モジュールにおいては、アルミニウム層の前記セラミックス基板とは反対側の面に形成されたチタン層を形成した回路層上に熱電素子が搭載されているので、アルミニウム層のアルミニウムが熱電素子に拡散することを防止して、熱電素子の特性の劣化を抑制することができる。 The thermoelectric conversion module of the present invention is characterized in that a thermoelectric element is mounted on the circuit layer of the above-described insulated circuit board.
In the thermoelectric conversion module having this configuration, since the thermoelectric element is mounted on the circuit layer formed with the titanium layer formed on the surface of the aluminum layer opposite to the ceramic substrate, the aluminum of the aluminum layer is the thermoelectric element. And the deterioration of the thermoelectric element characteristics can be suppressed.
　本発明によれば、セラミックス基板の一方の面に配設されたアルミニウム層と、このアルミニウム層の前記セラミックス基板とは反対側の面に形成されたチタン層とを有する回路層に対して、回路パターンを精度良く、かつ、効率良く形成することができる絶縁回路基板の製造方法、絶縁回路基板、熱電変換モジュールを提供することが可能となる。 According to the present invention, a circuit is provided for a circuit layer having an aluminum layer disposed on one surface of a ceramic substrate and a titanium layer formed on the surface of the aluminum layer opposite to the ceramic substrate. It is possible to provide an insulating circuit board manufacturing method, an insulating circuit board, and a thermoelectric conversion module that can form a pattern with high accuracy and efficiency.
本発明の第一の実施形態に係る絶縁回路基板を備えたパワーモジュールの概略説明図である。It is a schematic explanatory drawing of the power module provided with the insulated circuit board which concerns on 1st embodiment of this invention. 本発明の第一の実施形態に係る絶縁回路基板の説明図である。It is explanatory drawing of the insulated circuit board which concerns on 1st embodiment of this invention. 本発明の第一の実施形態に係る絶縁回路基板におけるアルミニウム層とチタン層との接合界面の拡大説明図である。It is expansion explanatory drawing of the joining interface of the aluminum layer and titanium layer in the insulated circuit board concerning 1st embodiment of this invention. 本発明の第一の実施形態に係る絶縁回路基板の製造方法を説明するフロー図である。It is a flowchart explaining the manufacturing method of the insulated circuit board which concerns on 1st embodiment of this invention. 本発明の第一の実施形態に係る絶縁回路基板の製造方法の概略説明図である。It is a schematic explanatory drawing of the manufacturing method of the insulated circuit board which concerns on 1st embodiment of this invention. 本発明の第二の実施形態に係る絶縁回路基板を備えたパワーモジュールの概略説明図である。It is a schematic explanatory drawing of the power module provided with the insulated circuit board which concerns on 2nd embodiment of this invention. 本発明の第二の実施形態に係る絶縁回路基板の説明図である。It is explanatory drawing of the insulated circuit board which concerns on 2nd embodiment of this invention. 本発明の第二の実施形態に係る絶縁回路基板の製造方法を説明するフロー図である。It is a flowchart explaining the manufacturing method of the insulated circuit board which concerns on 2nd embodiment of this invention. 本発明の第二の実施形態に係る絶縁回路基板の製造方法の概略説明図である。It is a schematic explanatory drawing of the manufacturing method of the insulated circuit board which concerns on 2nd embodiment of this invention. 本発明の第三の実施形態に係る絶縁回路基板を備えた熱電変換モジュールの概略説明図である。It is a schematic explanatory drawing of the thermoelectric conversion module provided with the insulated circuit board which concerns on 3rd embodiment of this invention. 本発明の第三の実施形態に係る絶縁回路基板の説明図である。It is explanatory drawing of the insulated circuit board which concerns on 3rd embodiment of this invention. 本発明の第三の実施形態に係る絶縁回路基板の製造方法を説明するフロー図である。It is a flowchart explaining the manufacturing method of the insulated circuit board which concerns on 3rd embodiment of this invention. 本発明の第三の実施形態に係る絶縁回路基板の製造方法の概略説明図である。It is a schematic explanatory drawing of the manufacturing method of the insulated circuit board which concerns on 3rd embodiment of this invention.
　以下に、本発明の実施形態について、添付した図面を参照して説明する。なお、以下の説明において、「ろう材（ｂｒａｚｉｎｇ　ｆｉｌｌｅｒ　ｍａｔｅｒｉａｌ）」は必ずしも鉛を含む材料に限定されない。 Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. In the following description, “brazing filler material” is not necessarily limited to a material containing lead.
（第一の実施形態）
　図１に、本発明の第一の実施形態である絶縁回路基板１０を用いたパワーモジュール１を示す。
　このパワーモジュール１は、絶縁回路基板１０と、この絶縁回路基板１０の一方の面（図１において上面）に第１はんだ層２を介して接合された半導体素子３と、絶縁回路基板１０の下側に第２はんだ層４２を介して接合されたヒートシンク４１と、を備えている。 (First embodiment)
In FIG. 1, the power module 1 using the insulated circuit board 10 which is 1st embodiment of this invention is shown.
The power module 1 includes an insulating circuit board 10, a semiconductor element 3 bonded to one surface (the upper surface in FIG. 1) of the insulating circuit board 10 via a first solder layer 2, and a bottom of the insulating circuit board 10. And a heat sink 41 joined via a second solder layer 42 to the side.
　半導体素子３は、Ｓｉ等の半導体材料で構成されている。絶縁回路基板１０と半導体素子３とを接合する第１はんだ層２は、例えばＳｎ－Ａｇ系、Ｓｎ－Ｃｕ系、Ｓｎ－Ｉｎ系、若しくはＳｎ－Ａｇ－Ｃｕ系のはんだ材（いわゆる鉛フリーはんだ材）とされている。 The semiconductor element 3 is made of a semiconductor material such as Si. The first solder layer 2 that joins the insulating circuit board 10 and the semiconductor element 3 is, for example, a Sn—Ag, Sn—Cu, Sn—In, or Sn—Ag—Cu solder material (so-called lead-free solder). Material).
　ヒートシンク４１は、絶縁回路基板１０側の熱を放散するためのものである。ヒートシンク４１は、銅又は銅合金で構成されており、本実施形態では無酸素銅で構成されている。絶縁回路基板１０とヒートシンク４１とを接合する第２はんだ層４２は、例えばＳｎ－Ａｇ系、Ｓｎ－Ｃｕ系、Ｓｎ－Ｉｎ系、若しくはＳｎ－Ａｇ－Ｃｕ系のはんだ材（いわゆる鉛フリーはんだ材）とされている。 The heat sink 41 is for dissipating heat on the insulated circuit board 10 side. The heat sink 41 is made of copper or a copper alloy, and is made of oxygen-free copper in this embodiment. The second solder layer 42 that joins the insulating circuit board 10 and the heat sink 41 is, for example, a Sn—Ag, Sn—Cu, Sn—In, or Sn—Ag—Cu solder material (so-called lead-free solder material). ).
　そして、本実施形態に係る絶縁回路基板１０は、図１及び図２に示すように、セラミックス基板１１と、このセラミックス基板１１の一方の面（図１及び図２において上面）に配設された回路層２０と、セラミックス基板１１の他方の面（図１及び図２において下面）に配設された金属層３０と、を備えている。 As shown in FIGS. 1 and 2, the insulated circuit board 10 according to the present embodiment is disposed on the ceramic substrate 11 and one surface (the upper surface in FIGS. 1 and 2) of the ceramic substrate 11. A circuit layer 20 and a metal layer 30 disposed on the other surface (the lower surface in FIGS. 1 and 2) of the ceramic substrate 11 are provided.
　セラミックス基板１１は、絶縁性の高いＡｌＮ（窒化アルミニウム）、Ｓｉ３Ｎ４（窒化ケイ素）、Ａｌ２Ｏ３（アルミナ）等で構成されている。本実施形態では、強度に優れたＳｉ３Ｎ４（窒化ケイ素）で構成されている。また、セラミックス基板１１の厚さは、０．２～１．５ｍｍの範囲内に設定されており、本実施形態では、０．３２ｍｍに設定されている。 The ceramic substrate 11 is made of highly insulating AlN (aluminum nitride), Si 3 N 4 (silicon nitride), Al 2 O 3 (alumina), or the like. In the present embodiment, it is composed of Si 3 N 4 excellent in strength (silicon nitride). In addition, the thickness of the ceramic substrate 11 is set within a range of 0.2 to 1.5 mm, and in this embodiment is set to 0.32 mm.
　回路層２０は、図１及び図２に示すように、セラミックス基板１１の一方の面に配設されたアルミニウム層２１と、このアルミニウム層２１の一方の面にチタン層２５を介して積層された銅層２２（金属部材層）と、を有している。
　ここで、回路層２０におけるアルミニウム層２１の厚さは、０．１ｍｍ以上１．０ｍｍ以下の範囲内に設定されており、本実施形態では０．４ｍｍに設定されている。
　また、回路層２０における銅層２２の厚さは、０．１ｍｍ以上６．０ｍｍ以下の範囲内に設定されており、本実施形態では、１．０ｍｍに設定されている。
　そして、この回路層２０には、図２に示すように、回路パターンが形成されている。 As shown in FIGS. 1 and 2, the circuit layer 20 is laminated with an aluminum layer 21 disposed on one surface of the ceramic substrate 11 and a titanium layer 25 on one surface of the aluminum layer 21. And a copper layer 22 (metal member layer).
Here, the thickness of the aluminum layer 21 in the circuit layer 20 is set within a range of 0.1 mm or more and 1.0 mm or less, and is set to 0.4 mm in the present embodiment.
Further, the thickness of the copper layer 22 in the circuit layer 20 is set within a range of 0.1 mm or more and 6.0 mm or less, and is set to 1.0 mm in the present embodiment.
In the circuit layer 20, a circuit pattern is formed as shown in FIG.
　金属層３０は、図１及び図２に示すように、セラミックス基板１１の他方の面に配設されたアルミニウム層３１と、このアルミニウム層３１の他方の面にチタン層３５を介して積層された銅層３２（金属部材層）と、を有している。
　ここで、金属層３０におけるアルミニウム層３１の厚さは、０．１ｍｍ以上３．０ｍｍ以下の範囲内に設定されており、本実施形態では０．４ｍｍに設定されている。
　また、金属層３０における銅層３２の厚さは、０．１ｍｍ以上６．０ｍｍ以下の範囲内に設定されており、本実施形態では、１．０ｍｍに設定されている。 As shown in FIGS. 1 and 2, the metal layer 30 is laminated with an aluminum layer 31 disposed on the other surface of the ceramic substrate 11 and a titanium layer 35 on the other surface of the aluminum layer 31. And a copper layer 32 (metal member layer).
Here, the thickness of the aluminum layer 31 in the metal layer 30 is set within a range of 0.1 mm to 3.0 mm, and is set to 0.4 mm in the present embodiment.
Moreover, the thickness of the copper layer 32 in the metal layer 30 is set within a range of 0.1 mm or more and 6.0 mm or less, and is set to 1.0 mm in the present embodiment.
　ここで、アルミニウム層２１、３１は、図５に示すように、セラミックス基板１１の一方の面及び他方の面に、アルミニウム板５１、６１が接合されることにより形成されている。
　また、アルミニウム層２１，３１となるアルミニウム板５１、６１は、純度が９９ｍａｓｓ％以上のアルミニウム（２Ｎアルミニウム）で構成されている。なお、Ｓｉの含有量は０．０３ｍａｓｓ％以上１．０ｍａｓｓ％以下の範囲内とされている。 Here, as shown in FIG. 5, the aluminum layers 21 and 31 are formed by bonding aluminum plates 51 and 61 to one surface and the other surface of the ceramic substrate 11.
The aluminum plates 51 and 61 to be the aluminum layers 21 and 31 are made of aluminum (2N aluminum) having a purity of 99 mass% or more. Note that the Si content is in the range of 0.03 mass% to 1.0 mass%.
　銅層２２、３２は、アルミニウム層２１、３１の一方の面及び他方の面に、チタン層２５、３５を介して銅又は銅合金からなる銅板（金属部材）が接合されることにより形成されている。本実施形態においては、銅層２２、３２を構成する銅板（金属部材）は、無酸素銅の圧延板とされている。 The copper layers 22 and 32 are formed by bonding a copper plate (metal member) made of copper or a copper alloy to one surface and the other surface of the aluminum layers 21 and 31 via the titanium layers 25 and 35. Yes. In this embodiment, the copper plates (metal members) constituting the copper layers 22 and 32 are oxygen-free copper rolled plates.
　そして、アルミニウム層２１、３１とチタン層２５、３５との接合界面には、図３に示すように、Ａｌ－Ｔｉ－Ｓｉ層２６、３６が形成されている。
　このＡｌ－Ｔｉ－Ｓｉ層２６、３６は、アルミニウム層２１、３１のＡｌ原子と、チタン層２５、３５のＴｉ原子とが相互拡散することによって形成されたＡｌ３Ｔｉに、アルミニウム層２１、３１のＳｉが固溶することにより形成される。
　Ａｌ－Ｔｉ－Ｓｉ層２６、３６の厚さは、０．５μｍ以上１０μｍ以下に設定されており、本実施形態においては３μｍとされている。 As shown in FIG. 3, Al—Ti—Si layers 26 and 36 are formed at the bonding interfaces between the aluminum layers 21 and 31 and the titanium layers 25 and 35.
The Al—Ti—Si layers 26, 36 are formed on Al 3 Ti formed by mutual diffusion of Al atoms in the aluminum layers 21, 31 and Ti atoms in the titanium layers 25, 35. This is formed by solid solution of Si.
The thickness of the Al—Ti—Si layers 26 and 36 is set to 0.5 μm or more and 10 μm or less, and is 3 μm in this embodiment.
　このＡｌ－Ｔｉ－Ｓｉ層２６、３６は、図３に示すように、チタン層２５、３５側に形成された第１Ａｌ－Ｔｉ－Ｓｉ層２６Ａ、３６Ａと、アルミニウム層２１，３１側に形成された第２Ａｌ－Ｔｉ－Ｓｉ層２６Ｂ、３６Ｂと、を備えている。すなわち、アルミニウム層２１、３１と銅層２２、３２との接合部には、チタン層２５、３５と、第１Ａｌ－Ｔｉ－Ｓｉ層２６Ａ、３６Ａと、第２Ａｌ－Ｔｉ－Ｓｉ層２６Ｂ、３６Ｂとが形成されている。 As shown in FIG. 3, the Al—Ti—Si layers 26, 36 are formed on the first Al—Ti—Si layers 26 A, 36 A formed on the titanium layers 25, 35 side and the aluminum layers 21, 31 side. Second Al—Ti—Si layers 26B and 36B. That is, at the junction between the aluminum layers 21 and 31 and the copper layers 22 and 32, the titanium layers 25 and 35, the first Al—Ti— Si layers 26A and 36A, the second Al—Ti—Si layers 26B and 36B, Is formed.
　これら、第１Ａｌ－Ｔｉ－Ｓｉ層２６Ａ、３６Ａと第２Ａｌ－Ｔｉ－Ｓｉ層２６Ｂ、３６Ｂは、上述のようにＡｌ３ＴｉにＳｉが固溶したＡｌ－Ｔｉ－Ｓｉ相からなり、第２Ａｌ－Ｔｉ－Ｓｉ層２６Ｂ、３６ＢのＳｉ濃度が、第１Ａｌ－Ｔｉ－Ｓｉ層２６Ａ、３６ＡのＳｉ濃度よりも低くなっている。なお、本実施形態において、第１Ａｌ－Ｔｉ－Ｓｉ層２６Ａ、３６Ａ及び第２Ａｌ－Ｔｉ－Ｓｉ層２６Ｂ、３６Ｂに含まれるＳｉは、後述するようにアルミニウム層２１、３１に拡散されたＳｉがＡｌ－Ｔｉ－Ｓｉ層２６、３６中に拡散し、濃化したものである。
　第１Ａｌ－Ｔｉ－Ｓｉ層２６Ａ、３６ＡのＳｉ濃度は、１０ａｔ％以上３０ａｔ％以下とされており、本実施形態では２０ａｔ％とされている。第２Ａｌ－Ｔｉ－Ｓｉ層２６Ｂ、３６ＢのＳｉ濃度は、１ａｔ％以上１０ａｔ％以下とされており、本実施形態では３ａｔ％とされている。 The first Al—Ti— Si layers 26A and 36A and the second Al—Ti—Si layers 26B and 36B are made of an Al—Ti—Si phase in which Si is dissolved in Al 3 Ti as described above. The Si concentration of the Ti—Si layers 26B and 36B is lower than the Si concentration of the first Al—Ti— Si layers 26A and 36A. In the present embodiment, Si contained in the first Al—Ti— Si layers 26A and 36A and the second Al—Ti—Si layers 26B and 36B is composed of Si diffused in the aluminum layers 21 and 31 as described later. Diffusion and concentration in the Ti-Si layers 26 and 36.
The Si concentration of the first Al—Ti— Si layers 26A and 36A is 10 at% or more and 30 at% or less, and is 20 at% in the present embodiment. The Si concentration of the second Al—Ti—Si layers 26B and 36B is 1 at% or more and 10 at% or less, and is 3 at% in this embodiment.
　次に、本実施形態である絶縁回路基板１０の製造方法について、図４及び図５を参照して説明する。 Next, a method for manufacturing the insulated circuit board 10 according to the present embodiment will be described with reference to FIGS.
（チタン材配設工程Ｓ０１）
　図４及び図５に示すように、アルミニウム板５１、６１の表面にチタン材５５、６５を配設する。このとき、回路層２０となるアルミニウム板５１の表面には、チタン材５５を回路パターン状に配設する。ここで、チタン材５５を回路パターン状に配設する際には、蒸着やイオンプレーティング等の成膜法を適用してもよい。この場合、メタルマスクを用いてチタン膜を成膜することで、チタン材５５を回路パターン状に配設することができる。また、チタン箔を回路パターン状に配設してもよい。
　なお、金属層３０となるアルミニウム板６１の表面にチタン材６５を配設する場合には、チタン箔を配設することが好ましい。
　ここで、チタン材５５、６５の厚さは７μｍ以上２０μｍ以下の範囲内とすることが好ましい。 (Titanium material disposing step S01)
As shown in FIGS. 4 and 5, titanium materials 55 and 65 are disposed on the surfaces of the aluminum plates 51 and 61. At this time, the titanium material 55 is arranged in a circuit pattern on the surface of the aluminum plate 51 to be the circuit layer 20. Here, when the titanium material 55 is arranged in a circuit pattern, a film forming method such as vapor deposition or ion plating may be applied. In this case, the titanium material 55 can be arranged in a circuit pattern by forming a titanium film using a metal mask. Further, the titanium foil may be arranged in a circuit pattern.
When the titanium material 65 is disposed on the surface of the aluminum plate 61 that becomes the metal layer 30, it is preferable to dispose a titanium foil.
Here, the thickness of the titanium materials 55 and 65 is preferably in the range of 7 μm to 20 μm.
（チタン層形成工程及びセラミックス／アルミニウム接合工程Ｓ０２）
　次いで、図４及び図５に示すように、セラミックス基板１１の一方の面にアルミニウム板５１及びチタン材５５を配設し、セラミックス基板１１の他方の面にアルミニウム板６１とチタン材６５とを配設する。このとき、アルミニウム板５１とセラミックス基板１１、アルミニウム板６１とセラミックス基板１１の間には、Ａｌ－Ｓｉろう材を介在させる。
　そして、これらを積層方向に加圧（荷重３～２０ｋｇｆ／ｃｍ２（０．２９～１．９６ＭＰａ））した状態で真空加熱炉内に配置し加熱する。ここで、真空加熱炉内の圧力は１０－６Ｐａ以上１０－３Ｐａ以下の範囲内に、加熱温度は６００℃以上６４０℃以下、保持時間は３０分以上１８０分以下の範囲内に設定されることが好ましい。 (Titanium layer forming step and ceramic / aluminum bonding step S02)
Next, as shown in FIGS. 4 and 5, an aluminum plate 51 and a titanium material 55 are disposed on one surface of the ceramic substrate 11, and an aluminum plate 61 and a titanium material 65 are disposed on the other surface of the ceramic substrate 11. Set up. At this time, an Al—Si brazing material is interposed between the aluminum plate 51 and the ceramic substrate 11 and between the aluminum plate 61 and the ceramic substrate 11.
These are placed in a vacuum heating furnace in a state where they are pressurized in the stacking direction (load: 3 to 20 kgf / cm 2 (0.29 to 1.96 MPa)) and heated. Here, the pressure in the vacuum heating furnace is set in the range of 10 −6 Pa to 10 −3 Pa, the heating temperature is set to 600 ° C. to 640 ° C., and the holding time is set in the range of 30 minutes to 180 minutes. It is preferable.
　これにより、アルミニウム板５１とセラミックス基板１１及びセラミックス基板１１とアルミニウム板６１を接合する（セラミックス／アルミニウム接合工程）。
　そして、アルミニウム板５１とチタン材５５、アルミニウム板６１とチタン材６５を接合し、チタン層２５、３５を形成する（チタン層形成工程）。このとき、アルミニウム板５１とチタン材５５、アルミニウム板６１とチタン材６５との接合界面にはＡｌ３Ｔｉが形成される。なお、アルミニウム板５１、６１がＳｉを０．０３ｍａｓｓ％以上１．０ｍａｓｓ％以下の範囲で含有しているので、Ａｌ３ＴｉにＳｉが固溶し、上述のＡｌ－Ｔｉ－Ｓｉ層２６、３６が形成される。
　なお、回路層２０となるアルミニウム板５１にはチタン層２５が回路パターン状に形成される。 Thereby, the aluminum plate 51 and the ceramic substrate 11 and the ceramic substrate 11 and the aluminum plate 61 are joined (ceramic / aluminum joining step).
And the aluminum plate 51 and the titanium material 55, the aluminum plate 61, and the titanium material 65 are joined, and the titanium layers 25 and 35 are formed (titanium layer formation process). At this time, Al 3 Ti is formed at the bonding interface between the aluminum plate 51 and the titanium material 55 and between the aluminum plate 61 and the titanium material 65. Since the aluminum plates 51 and 61 contain Si in the range of 0.03 mass% to 1.0 mass%, Si is dissolved in Al 3 Ti, and the Al—Ti—Si layers 26, 36 described above are dissolved. Is formed.
A titanium layer 25 is formed in a circuit pattern on the aluminum plate 51 to be the circuit layer 20.
（エッチング処理工程Ｓ０３）
　次に、図４及び図５に示すように、チタン層２５が回路パターン状に形成されたアルミニウム層２１に対してエッチング処理を行う。このとき、エッチング剤としては、塩化第二鉄を使用する。例えば、エッチング剤（エッチング液）の塩化第二鉄の濃度は３５ｗｔ％～６０ｗｔ％とし、エッチング温度４０℃～６０℃で２分～２０分の条件でエッチングを行うことができる。
　ここで、チタン層２５は、塩化第二鉄によってほとんどエッチングされないことから、チタン層２５がレジスト材として作用する。すなわち、チタン層２５が形成された部分はエッチングされず、チタン層２５が形成されていない部分のみがエッチングされる。これにより、アルミニウム層２１についても回路パターン状に形成される。 (Etching process S03)
Next, as shown in FIGS. 4 and 5, an etching process is performed on the aluminum layer 21 in which the titanium layer 25 is formed in a circuit pattern. At this time, ferric chloride is used as an etching agent. For example, the concentration of ferric chloride in the etching agent (etching solution) is 35 wt% to 60 wt%, and etching can be performed at an etching temperature of 40 ° C. to 60 ° C. for 2 minutes to 20 minutes.
Here, since the titanium layer 25 is hardly etched by ferric chloride, the titanium layer 25 acts as a resist material. That is, the portion where the titanium layer 25 is formed is not etched, and only the portion where the titanium layer 25 is not formed is etched. Thereby, the aluminum layer 21 is also formed in a circuit pattern.
（チタン層洗浄工程Ｓ０４）
　次に、図４に示すように、チタン層２５、３５のうち銅層２２、３２が配設される面を洗浄する。ここで、チタン層２５、３５の洗浄には、アンモニアと過酸化水素との混合液を用いる。例えば、アンモニア１０ｗｔ％、過酸化水素３ｗｔ％、ＥＤＴＡ（エチレンジアミン四酢酸）１２ｗｔ％の水溶液を用いることができる。洗浄の条件として、温度４０℃～５０℃、１０分～３０分で洗浄を行うとよい。 (Titanium layer cleaning step S04)
Next, as shown in FIG. 4, the surfaces of the titanium layers 25 and 35 on which the copper layers 22 and 32 are disposed are cleaned. Here, a mixed liquid of ammonia and hydrogen peroxide is used for cleaning the titanium layers 25 and 35. For example, an aqueous solution of 10 wt% ammonia, 3 wt% hydrogen peroxide, and 12 wt% EDTA (ethylenediaminetetraacetic acid) can be used. As a cleaning condition, the cleaning may be performed at a temperature of 40 ° C. to 50 ° C. for 10 minutes to 30 minutes.
（銅層形成工程Ｓ０５）
　次に、チタン層２５、３５の表面に銅板（金属部材）を接合し、銅層２２、３２を形成する。このとき、チタン層２５、３５と銅板（金属部材）とを接合する際には、固相拡散接合法を適用してもよいし、ろう材を用いて接合してもよい。
　例えば、固相拡散接合を適用する場合、チタン層２５、３５と銅板（金属部材）とを積層し、積層方向に加圧（荷重３～２０ｋｇｆ／ｃｍ２）した状態で、真空加熱炉内の圧力は１０－６Ｐａ以上１０－３Ｐａ以下の範囲内に、加熱温度は６００℃以上６５０℃以下、より好ましくは６２０℃以上６４３℃以下、保持時間は３０分以上１８０分以下、より好ましくは６０分以上１２０分以下の範囲内で接合するとよい。 (Copper layer forming step S05)
Next, a copper plate (metal member) is joined to the surfaces of the titanium layers 25 and 35 to form the copper layers 22 and 32. At this time, when the titanium layers 25 and 35 and the copper plate (metal member) are bonded, a solid phase diffusion bonding method may be applied or a brazing material may be used for bonding.
For example, in the case of applying solid phase diffusion bonding, titanium layers 25 and 35 and a copper plate (metal member) are stacked and pressed in the stacking direction (load 3 to 20 kgf / cm 2 ) in a vacuum heating furnace. The pressure is in the range of 10 −6 Pa to 10 −3 Pa, the heating temperature is 600 ° C. to 650 ° C., more preferably 620 ° C. to 643 ° C., and the holding time is 30 minutes to 180 minutes, more preferably It is good to join within the range of 60 minutes or more and 120 minutes or less.
　ろう材を用いて接合する場合、Ｃｕ－Ｐ－Ｓｎろう材、Ｃｕ－Ｐ－Ｓｎ－Ｎｉ系ろう材、Ｃｕ－Ｐ－Ｓｎ－Ｆｅ系ろう材、Ｃｕ－Ｐ－Ｓｎ－Ｍｎ系ろう材、Ｃｕ－Ｐ－Ｓｎ－Ｃｒ系ろう材などのろう材箔を、チタン層２５、３５と銅板（金属部材）との間に配置し、積層方向に加圧（荷重３～２０ｋｇｆ／ｃｍ２）した状態で、真空加熱炉内の圧力は１０－６Ｐａ以上１０－３Ｐａ以下の範囲内に、加熱温度は６００℃以上６５０℃以下、より好ましくは６２０℃以上６４３℃以下、保持時間は１５分以上１２０分以下、より好ましくは３０分以上９０分以下の範囲内で接合するとよい。
　このとき、回路層２０側においては、回路パターン状に形成されたチタン層２５の上に、銅板（金属部材）を配設して接合する。 When joining using a brazing material, a Cu—P—Sn brazing material, a Cu—P—Sn—Ni based brazing material, a Cu—P—Sn—Fe based brazing material, a Cu—P—Sn—Mn based brazing material, A brazing foil such as a Cu—P—Sn—Cr brazing filler metal was disposed between the titanium layers 25 and 35 and the copper plate (metal member) and pressed in the stacking direction (load 3 to 20 kgf / cm 2 ). In this state, the pressure in the vacuum heating furnace is in the range of 10 −6 Pa to 10 −3 Pa, the heating temperature is 600 ° C. to 650 ° C., more preferably 620 ° C. to 643 ° C., and the holding time is 15 minutes. It is good to join within 120 minutes or less, More preferably within the range of 30 minutes or more and 90 minutes or less.
At this time, on the circuit layer 20 side, a copper plate (metal member) is disposed and bonded on the titanium layer 25 formed in a circuit pattern.
　上述の工程により、アルミニウム層２１とチタン層２５と銅層２２とが積層されてなる回路層２０に回路パターンが形成され、本実施形態である絶縁回路基板１０が製造される。 Through the above-described steps, a circuit pattern is formed on the circuit layer 20 in which the aluminum layer 21, the titanium layer 25, and the copper layer 22 are laminated, and the insulated circuit board 10 according to this embodiment is manufactured.
　以上のような構成とされた本実施形態に係る絶縁回路基板１０の製造方法によれば、アルミニウム板５１の表面にチタン層２５となるチタン材５５を回路パターン状に配設するチタン材配設工程Ｓ０１を備えているので、その後のチタン層形成工程及びセラミックス／アルミニウム接合工程Ｓ０２により、アルミニウム層２１の表面にチタン層２５を回路パターン状に形成することができる。 According to the manufacturing method of the insulated circuit board 10 according to the present embodiment configured as described above, the titanium material arrangement in which the titanium material 55 to be the titanium layer 25 is arranged in a circuit pattern on the surface of the aluminum plate 51. Since the process S01 is provided, the titanium layer 25 can be formed in a circuit pattern on the surface of the aluminum layer 21 by the subsequent titanium layer forming process and the ceramic / aluminum bonding process S02.
　次に、チタン層２５が形成されたアルミニウム層２１に対してエッチング処理を行うエッチング処理工程Ｓ０３を備えているので、チタン層２５がレジスト材として作用し、アルミニウム層２１を回路パターン状にエッチングすることができる。すなわち、チタン層２５をレジスト材として使用することにより、レジスト材の塗布工程、硬化工程及び剥離工程を省略することができ、エッチング処理工程Ｓ０３を効率良く行うことができる。 Next, since the etching process step S03 for performing an etching process on the aluminum layer 21 on which the titanium layer 25 is formed is provided, the titanium layer 25 acts as a resist material, and the aluminum layer 21 is etched into a circuit pattern. be able to. That is, by using the titanium layer 25 as a resist material, the resist material application process, the curing process, and the peeling process can be omitted, and the etching process S03 can be performed efficiently.
　そして、回路パターン状に形成されたチタン層２５の上に銅板（金属部材）を接合して銅層２２を形成する銅層形成工程Ｓ０５を有しているので、チタン層２５の上に銅層２２を回路パターン状に形成することができる。
　以上により、アルミニウム層２１とチタン層２５と銅層２２とが積層されてなる回路層２０に対して、回路パターンを精度良く、かつ、効率良く形成することができる。 And since it has the copper layer formation process S05 which joins a copper plate (metal member) on the titanium layer 25 formed in the circuit pattern shape, and forms the copper layer 22, it is a copper layer on the titanium layer 25. 22 can be formed in a circuit pattern.
As described above, the circuit pattern can be accurately and efficiently formed on the circuit layer 20 in which the aluminum layer 21, the titanium layer 25, and the copper layer 22 are laminated.
　また、本実施形態においては、チタン層形成工程と、セラミックス／アルミニウム接合工程と、を同時に実施するチタン層形成工程及びセラミックス／アルミニウム接合工程Ｓ０２を有しているので、回路パターンを有する絶縁回路基板１０を効率良く製造することができる。 Moreover, in this embodiment, since it has the titanium layer formation process and ceramics / aluminum joining process S02 which perform a titanium layer formation process and a ceramics / aluminum joining process simultaneously, the insulated circuit board which has a circuit pattern 10 can be manufactured efficiently.
　また、本実施形態である絶縁回路基板１０の製造方法においては、銅層形成工程Ｓ０５の前に、チタン層２５の表面を洗浄するチタン層洗浄工程Ｓ０４を備えているので、チタン層２５と銅板（金属部材）とを確実に接合でき、銅層２２を確実に形成することができる。 Moreover, in the manufacturing method of the insulated circuit board 10 which is this embodiment, since the titanium layer cleaning process S04 which cleans the surface of the titanium layer 25 is provided before the copper layer formation process S05, the titanium layer 25 and the copper plate (Metal member) can be reliably joined, and the copper layer 22 can be reliably formed.
　さらに、本実施形態である絶縁回路基板１０の製造方法においては、アルミニウム板５１、６１がＳｉを０．０３ｍａｓｓ％以上１．０ｍａｓｓ％以下の範囲内で含有しているので、チタン層２５、３５とアルミニウム層２１、３１との接合界面において、Ａｌ３ＴｉにＳｉが固溶し、上述のＡｌ－Ｔｉ－Ｓｉ層２６、３６が形成される。このＡｌ－Ｔｉ－Ｓｉ層２６、３６は、比較的硬さが低いため、ヒートサイクルが負荷された際に、回路層２０及び金属層３０にクラックが発生することを抑制することができる。 Furthermore, in the manufacturing method of the insulated circuit board 10 which is this embodiment, since the aluminum plates 51 and 61 contain Si within the range of 0.03 mass% or more and 1.0 mass% or less, the titanium layers 25 and 35 are included. Si is dissolved in Al 3 Ti at the bonding interface between the aluminum layers 21 and 31 and the Al—Ti—Si layers 26 and 36 described above are formed. Since the Al—Ti—Si layers 26 and 36 are relatively low in hardness, the occurrence of cracks in the circuit layer 20 and the metal layer 30 when a heat cycle is applied can be suppressed.
　さらに、チタン層２５、３５側に形成された第１Ａｌ－Ｔｉ－Ｓｉ層２６Ａ，３６ＡのＳｉ濃度が、アルミニウム層２１、３１側に形成された第２Ａｌ－Ｔｉ－Ｓｉ層２６Ｂ、３６ＢのＳｉ濃度よりも高いので、Ｓｉ濃度が高い第１Ａｌ－Ｔｉ－Ｓｉ層２６Ａ，３６ＡによってＴｉ原子がアルミニウム層２１、３１側に拡散することが抑制され、Ａｌ－Ｔｉ－Ｓｉ層２６、３６の厚さを薄くすることができる。そして、このようにＡｌ－Ｔｉ－Ｓｉ層２６、３６の厚さを薄くすることで、ヒートサイクルが負荷された際にアルミニウム層２１、３１と銅層２２，３２との接合部に割れが発生することを抑制可能となる。 Further, the Si concentration of the first Al—Ti—Si layers 26A, 36A formed on the titanium layers 25, 35 side is the Si concentration of the second Al—Ti—Si layers 26B, 36B formed on the aluminum layers 21, 31 side. Therefore, the first Al—Ti— Si layers 26A and 36A having a high Si concentration suppress the Ti atoms from diffusing toward the aluminum layers 21 and 31, thereby reducing the thickness of the Al—Ti—Si layers 26 and 36. Can be thinned. Further, by reducing the thickness of the Al—Ti—Si layers 26 and 36 in this way, cracks occur at the joints between the aluminum layers 21 and 31 and the copper layers 22 and 32 when a heat cycle is applied. This can be suppressed.
　また、アルミニウム層２１、３１側に形成された第２Ａｌ－Ｔｉ－Ｓｉ層２６Ｂ、３６Ｂに含まれるＳｉ濃度が１ａｔ％以上１０ａｔ％以下とされているので、Ａｌ原子がチタン層２５，３５側に過剰に拡散することが抑制され、第２Ａｌ－Ｔｉ－Ｓｉ層２６Ｂ、３６Ｂの厚さを薄くすることができる。第２Ａｌ－Ｔｉ－Ｓｉ層２６Ｂ、３６ＢにおけるＳｉ濃度は１ａｔ％以上１０ａｔ％以下がより好ましいが、これに限定されない。
　さらには、チタン層２５、３５側に形成された第１Ａｌ－Ｔｉ－Ｓｉ層２６Ａ，３６Ａに含まれるＳｉ濃度が１０ａｔ％以上３０ａｔ％以下とされているので、Ｔｉ原子がアルミニウム層２１、３１側に過剰に拡散することが抑制され、第１Ａｌ－Ｔｉ－Ｓｉ層２６Ａ，３６Ａの厚さを薄くすることができる。第１Ａｌ－Ｔｉ－Ｓｉ層２６Ａ、３６ＡにおけるＳｉ濃度は１０ａｔ％以上３０ａｔ％以下がより好ましいが、これに限定されない。 Further, since the Si concentration contained in the second Al—Ti—Si layers 26B and 36B formed on the aluminum layers 21 and 31 side is 1 at% or more and 10 at% or less, Al atoms are on the titanium layers 25 and 35 side. Excessive diffusion is suppressed, and the thickness of the second Al—Ti—Si layers 26B and 36B can be reduced. The Si concentration in the second Al—Ti—Si layers 26B and 36B is more preferably 1 at% or more and 10 at% or less, but is not limited thereto.
Furthermore, since the Si concentration contained in the first Al—Ti— Si layers 26A and 36A formed on the titanium layers 25 and 35 side is 10 at% or more and 30 at% or less, Ti atoms are on the aluminum layers 21 and 31 side. Therefore, the first Al—Ti— Si layers 26A and 36A can be reduced in thickness. The Si concentration in the first Al—Ti— Si layers 26A and 36A is more preferably 10 at% or more and 30 at% or less, but is not limited thereto.
　さらに、本実施形態では、回路層２０及び金属層３０の表面に、比較的変形抵抗の大きい銅層２２，３２が形成されているので、ヒートサイクルが負荷された際に回路層２０及び金属層３０の表面の変形が抑制され、半導体素子３と回路層２０とを接合する第１はんだ層２及びヒートシンク４１と金属層３０とを接合する第２はんだ層４２にクラック等が生じることを抑制でき、接合信頼性を向上できる。
　また、熱伝導率の良好な銅層２２，３２が回路層２０及び金属層３０の表面に形成されているので、半導体素子３からの熱を面方向に拡げて効率的にヒートシンク４１側に伝達することができる。 Further, in the present embodiment, since the copper layers 22 and 32 having a relatively large deformation resistance are formed on the surface of the circuit layer 20 and the metal layer 30, the circuit layer 20 and the metal layer when the heat cycle is applied. 30, the deformation of the surface of the first solder layer 2 that joins the semiconductor element 3 and the circuit layer 20 and the second solder layer 42 that joins the heat sink 41 and the metal layer 30 can be prevented from cracking. , The bonding reliability can be improved.
Further, since the copper layers 22 and 32 having good thermal conductivity are formed on the surface of the circuit layer 20 and the metal layer 30, the heat from the semiconductor element 3 is spread in the surface direction and efficiently transmitted to the heat sink 41 side. can do.
（第二の実施形態）
　次に、本発明の第二の実施形態について説明する。なお、第一の実施形態と同一の構成のものについては、同一の符号を付して記載し、詳細な説明を省略する。
　図６に、本発明の第二の実施形態に係る絶縁回路基板１１０を備えたパワーモジュール１０１を示す。
　このパワーモジュール１０１は、絶縁回路基板１１０と、この絶縁回路基板１１０の一方の面（図６において上面）にはんだ層２を介して接合された半導体素子３と、絶縁回路基板１１０の下側に接合されたヒートシンク１４１と、を備えている。 (Second embodiment)
Next, a second embodiment of the present invention will be described. In addition, about the thing of the same structure as 1st embodiment, the same code | symbol is attached | subjected and described, and detailed description is abbreviate | omitted.
FIG. 6 shows a power module 101 including an insulated circuit board 110 according to the second embodiment of the present invention.
The power module 101 includes an insulating circuit board 110, a semiconductor element 3 bonded to one surface (upper surface in FIG. 6) of the insulating circuit board 110 via a solder layer 2, and a lower side of the insulating circuit board 110. A heat sink 141 bonded thereto.
　ヒートシンク１４１は、絶縁回路基板１１０側の熱を放散するためのものである。ヒートシンク１４１は、アルミニウム又はアルミニウム合金で構成されており、本実施形態ではＡ６０６３合金で構成されている。絶縁回路基板１１０とヒートシンク１４１は、ろう材を用いて接合されている。 The heat sink 141 is for dissipating heat on the insulated circuit board 110 side. The heat sink 141 is made of aluminum or an aluminum alloy, and in this embodiment is made of an A6063 alloy. The insulated circuit board 110 and the heat sink 141 are joined using a brazing material.
　絶縁回路基板１１０は、図６及び図７に示すように、セラミックス基板１１と、このセラミックス基板１１の一方の面に配設された回路層１２０と、セラミックス基板１１の他方の面に配設された金属層１３０と、を備えている。 As shown in FIGS. 6 and 7, the insulating circuit substrate 110 is disposed on the ceramic substrate 11, the circuit layer 120 disposed on one surface of the ceramic substrate 11, and the other surface of the ceramic substrate 11. And a metal layer 130.
　回路層１２０は、図６及び図７に示すように、セラミックス基板１１の一方の面に配設されたアルミニウム層１２１と、このアルミニウム層１２１の一方の面にチタン層１２５を介して積層された銅層１２２（金属部材層）と、を有している。
　ここで、回路層１２０におけるアルミニウム層１２１の厚さは、０．１ｍｍ以上１．０ｍｍ以下の範囲内に設定されており、本実施形態では０．６ｍｍに設定されている。
　また、回路層１２０における銅層１２２の厚さは、０．１ｍｍ以上６．０ｍｍ以下の範囲内に設定されており、本実施形態では、１．５ｍｍに設定されている。
　そして、この回路層１２０には、図７に示すように、回路パターンが形成されている。 As shown in FIGS. 6 and 7, the circuit layer 120 is laminated with an aluminum layer 121 disposed on one surface of the ceramic substrate 11 and a titanium layer 125 on one surface of the aluminum layer 121. And a copper layer 122 (metal member layer).
Here, the thickness of the aluminum layer 121 in the circuit layer 120 is set within a range of 0.1 mm or more and 1.0 mm or less, and is set to 0.6 mm in the present embodiment.
Further, the thickness of the copper layer 122 in the circuit layer 120 is set within a range of 0.1 mm or more and 6.0 mm or less, and is set to 1.5 mm in the present embodiment.
In the circuit layer 120, a circuit pattern is formed as shown in FIG.
　ここで、アルミニウム層１２１は、図９に示すように、セラミックス基板１１の一方の面にアルミニウム板１５１が接合されることにより形成されている。
　ここで、アルミニウム層１２１となるアルミニウム板１５１は、純度が９９ｍａｓｓ％以上のアルミニウム（２Ｎアルミニウム）で構成されている。なお、Ｓｉの含有量は０．０３ｍａｓｓ％以上１．０ｍａｓｓ％以下の範囲内とされている。 Here, as shown in FIG. 9, the aluminum layer 121 is formed by joining an aluminum plate 151 to one surface of the ceramic substrate 11.
Here, the aluminum plate 151 to be the aluminum layer 121 is made of aluminum (2N aluminum) having a purity of 99 mass% or more. Note that the Si content is in the range of 0.03 mass% to 1.0 mass%.
　銅層１２２は、図９に示すように、アルミニウム層１２１の一方の面に、チタン層１２５を介して銅又は銅合金からなる銅板（金属部材）が接合されることにより形成されている。本実施形態においては、銅層１２２を構成する銅板（金属部材）は、無酸素銅の圧延板とされている。 As shown in FIG. 9, the copper layer 122 is formed by bonding a copper plate (metal member) made of copper or a copper alloy to one surface of the aluminum layer 121 via a titanium layer 125. In the present embodiment, the copper plate (metal member) constituting the copper layer 122 is an oxygen-free copper rolled plate.
　そして、アルミニウム層１２１とチタン層１２５との接合界面には、第一の実施形態と同様に、Ａｌ３ＴｉにＳｉが固溶したＡｌ－Ｔｉ－Ｓｉ層が形成されている。このＡｌ－Ｔｉ－Ｓｉ層は、アルミニウム層１２１のＡｌ原子と、チタン層１２５のＴｉ原子とが相互拡散することによってＡｌ３Ｔｉが形成されるとともに、アルミニウム層１２１のＳｉが、このＡｌ３Ｔｉに固溶することで形成されている。 At the bonding interface between the aluminum layer 121 and the titanium layer 125, an Al—Ti—Si layer in which Si is dissolved in Al 3 Ti is formed as in the first embodiment. In the Al—Ti—Si layer, Al 3 Ti is formed by the mutual diffusion of Al atoms in the aluminum layer 121 and Ti atoms in the titanium layer 125, and the Si in the aluminum layer 121 is formed by the Al 3 Ti. It is formed by solid solution.
　金属層１３０は、図９に示すように、セラミックス基板１１の一方の面にアルミニウム板１６１が接合されることにより形成されている。本実施形態において、金属層１３０は、純度９９．９９ｍａｓｓ％以上のアルミニウム（４Ｎアルミニウム）の圧延板を接合することで形成されている。なお、接合されるアルミニウム板１６１の厚さは０．１ｍｍ以上１．０ｍｍ以下の範囲内に設定されており、本実施形態では、０．６ｍｍに設定されている。 The metal layer 130 is formed by bonding an aluminum plate 161 to one surface of the ceramic substrate 11 as shown in FIG. In the present embodiment, the metal layer 130 is formed by joining rolled sheets of aluminum (4N aluminum) having a purity of 99.99 mass% or more. In addition, the thickness of the aluminum plate 161 to be joined is set within a range of 0.1 mm to 1.0 mm, and is set to 0.6 mm in the present embodiment.
　次に、本実施形態である絶縁回路基板１１０の製造方法について、図８、図９を参照して説明する。 Next, a method for manufacturing the insulated circuit board 110 according to the present embodiment will be described with reference to FIGS.
（セラミックス／アルミニウム接合工程Ｓ１０１）
　まず、図８及び図９に示すように、セラミックス基板１１の一方の面に、Ａｌ－Ｓｉ系のろう材箔（図示なし）を介してアルミニウム板１５１を積層する。また、セラミックス基板１１の他方の面にろう材箔（図示なし）を介してアルミニウム板１６１を積層する。
　次いで、積層したアルミニウム板１５１、セラミックス基板１１及びアルミニウム板１６１を、積層方向に加圧（荷重３～２０ｋｇｆ／ｃｍ２）した状態で真空加熱炉内に配置し加熱する。
　これにより、アルミニウム板１５１とセラミックス基板１１及びセラミックス基板１１とアルミニウム板１６１を接合し、アルミニウム層１２１及び金属層１３０を形成する。 (Ceramic / Aluminum Joining Step S101)
First, as shown in FIGS. 8 and 9, an aluminum plate 151 is laminated on one surface of the ceramic substrate 11 via an Al—Si based brazing foil (not shown). Further, an aluminum plate 161 is laminated on the other surface of the ceramic substrate 11 via a brazing material foil (not shown).
Next, the laminated aluminum plate 151, ceramic substrate 11 and aluminum plate 161 are placed in a vacuum heating furnace and heated in a state of being pressurized (load 3 to 20 kgf / cm 2 ) in the lamination direction.
As a result, the aluminum plate 151 and the ceramic substrate 11 and the ceramic substrate 11 and the aluminum plate 161 are joined to form the aluminum layer 121 and the metal layer 130.
（アルミニウム洗浄工程Ｓ１０２）
　次に、図８に示すように、アルミニウム層１２１のうちチタン材１５５が配設される側の面を洗浄する。なお、アルミニウム層１２１の洗浄は、例えば、硫酸５ｗｔ％～１０ｗｔ％水溶液又は硝酸５ｗｔ％～１０ｗｔ％水溶液を用い、温度２０℃～３０℃、時間３０秒～６０秒で行うことができる。 (Aluminum cleaning step S102)
Next, as shown in FIG. 8, the surface of the aluminum layer 121 on the side where the titanium material 155 is disposed is cleaned. The aluminum layer 121 can be cleaned, for example, using a 5 wt% to 10 wt% sulfuric acid aqueous solution or a 5 wt% to 10 wt% nitric acid aqueous solution at a temperature of 20 ° C. to 30 ° C. for a time of 30 seconds to 60 seconds.
（チタン材配設工程Ｓ１０３）
　次に、図８及び図９に示すように、アルミニウム層１２１の表面にチタン材１５５を回路パターン状に配設する。ここで、チタン材１５５を回路パターン状に配設する際には、蒸着やイオンプレーティング等の成膜法を適用してもよい。この場合、メタルマスクを用いてチタン膜を成膜することで、チタン材１５５を回路パターン状に配設することができる。また、チタン箔を回路パターン状に配設してもよい。
　ここで、チタン材１５５の厚さは７μｍ以上２０μｍ以下の範囲内とすることが好ましい。 (Titanium material disposing step S103)
Next, as shown in FIGS. 8 and 9, a titanium material 155 is arranged in a circuit pattern on the surface of the aluminum layer 121. Here, when the titanium material 155 is arranged in a circuit pattern, a film forming method such as vapor deposition or ion plating may be applied. In this case, the titanium material 155 can be arranged in a circuit pattern by forming a titanium film using a metal mask. Further, the titanium foil may be arranged in a circuit pattern.
Here, the thickness of the titanium material 155 is preferably in the range of 7 μm or more and 20 μm or less.
（チタン層形成工程Ｓ１０４）
　次に、図８及び図９に示すように、アルミニウム層１２１の表面にチタン材１５５を配設した状態で、これらを積層方向に加圧（荷重３～２０ｋｇｆ／ｃｍ２）した状態で真空加熱炉内に配置し加熱する。ここで、真空加熱炉内の圧力は１０－６Ｐａ以上１０－３Ｐａ以下の範囲内に、加熱温度は６００℃以上６４０℃以下、保持時間は３０分以上１８０分以下の範囲内に設定されることが好ましい。
　これにより、アルミニウム層１２１とチタン材１５５とが接合され、チタン層１２５が回路パターン状に形成される。このとき、アルミニウム層１２１とチタン層１２５との接合界面には上述のＡｌ－Ｔｉ－Ｓｉ層が形成される。 (Titanium layer forming step S104)
Next, as shown in FIG. 8 and FIG. 9, with the titanium material 155 disposed on the surface of the aluminum layer 121, vacuum heating is performed in a state where these are pressed in the stacking direction (load 3 to 20 kgf / cm 2 ). Place in the furnace and heat. Here, the pressure in the vacuum heating furnace is set in the range of 10 −6 Pa to 10 −3 Pa, the heating temperature is set to 600 ° C. to 640 ° C., and the holding time is set in the range of 30 minutes to 180 minutes. It is preferable.
Thereby, the aluminum layer 121 and the titanium material 155 are joined, and the titanium layer 125 is formed in a circuit pattern. At this time, the Al—Ti—Si layer described above is formed at the bonding interface between the aluminum layer 121 and the titanium layer 125.
（エッチング処理工程Ｓ１０５）
　次に、図８及び図９に示すように、チタン層１２５が回路パターン状に形成されたアルミニウム層１２１に対してエッチング処理を行う。エッチング剤としては、塩化第二鉄を使用する。このとき、チタン層１２５をレジスト膜として作用させることにより、アルミニウム層１２１を回路パターン状にエッチングする。 (Etching process S105)
Next, as shown in FIGS. 8 and 9, an etching process is performed on the aluminum layer 121 in which the titanium layer 125 is formed in a circuit pattern. As an etchant, ferric chloride is used. At this time, the aluminum layer 121 is etched into a circuit pattern by using the titanium layer 125 as a resist film.
（チタン層洗浄工程Ｓ１０６）
　次に、図８に示すように、チタン層１２５のうち銅層１２２が配設される面を洗浄する。ここで、チタン層１２５の洗浄は、第一実施形態と同様に行うことができる。 (Titanium layer cleaning step S106)
Next, as shown in FIG. 8, the surface of the titanium layer 125 on which the copper layer 122 is disposed is cleaned. Here, the cleaning of the titanium layer 125 can be performed as in the first embodiment.
（銅層形成工程Ｓ１０７）
　次に、回路パターン状に形成されたチタン層１２５の表面に銅板（金属部材）を接合し、銅層１２２を形成する。このとき、チタン層１２５と銅板（金属部材）を接合する際には、第一実施形態と同様に、固相拡散接合法を適用してもよいし、ろう材を用いて接合してもよい。 (Copper layer forming step S107)
Next, a copper plate (metal member) is bonded to the surface of the titanium layer 125 formed in a circuit pattern to form the copper layer 122. At this time, when the titanium layer 125 and the copper plate (metal member) are bonded, the solid phase diffusion bonding method may be applied or the brazing material may be bonded as in the first embodiment. .
　上述の工程により、アルミニウム層１２１とチタン層１２５と銅層１２２とが積層されてなる回路層１２０に回路パターンが形成され、本実施形態である絶縁回路基板１１０が製造される。 Through the above-described steps, a circuit pattern is formed on the circuit layer 120 in which the aluminum layer 121, the titanium layer 125, and the copper layer 122 are laminated, and the insulated circuit board 110 according to this embodiment is manufactured.
　以上のような構成とされた本実施形態に係る絶縁回路基板１１０の製造方法によれば、第一の実施形態と同様に、チタン材配設工程Ｓ１０３とチタン層形成工程Ｓ１０４とエッチング処理工程Ｓ１０５と銅層形成工程Ｓ１０７とを備えているので、アルミニウム層１２１とチタン層１２５と銅層１２２とが積層されてなる回路層１２０に対して、回路パターンを精度良く、かつ、効率良く形成することができる。また、エッチング処理工程Ｓ１０５においてチタン層１２５をレジスト材として使用しているので、レジスト材の塗布工程や剥離工程を省略することができ、エッチング処理工程Ｓ１０５を効率良く行うことができる。 According to the manufacturing method of the insulated circuit board 110 according to the present embodiment configured as described above, the titanium material disposing step S103, the titanium layer forming step S104, and the etching process step S105, as in the first embodiment. And the copper layer forming step S107, the circuit pattern can be accurately and efficiently formed on the circuit layer 120 in which the aluminum layer 121, the titanium layer 125, and the copper layer 122 are laminated. Can do. In addition, since the titanium layer 125 is used as a resist material in the etching process S105, the resist material application process and the peeling process can be omitted, and the etching process S105 can be performed efficiently.
（第三の実施形態）
　次に、本発明の第三の実施形態について説明する。なお、第一の実施形態及び第二の実施形態と同一の構成のものについては、同一の符号を付して記載し、詳細な説明を省略する。
　図１０に、本発明の第三の実施形態に係る絶縁回路基板２１０を備えた熱電変換モジュール２０１を示す。 (Third embodiment)
Next, a third embodiment of the present invention will be described. In addition, about the thing of the same structure as 1st embodiment and 2nd embodiment, the same code | symbol is attached | subjected and described, and detailed description is abbreviate | omitted.
In FIG. 10, the thermoelectric conversion module 201 provided with the insulated circuit board 210 which concerns on 3rd embodiment of this invention is shown.
　この熱電変換モジュール２０１は、熱電素子２０３と、この熱電素子２０３の一端側及び他端側にそれぞれ配設された絶縁回路基板２１０と、を備えている。
　熱電素子２０３は、絶縁回路基板２１０の回路層２２０に対して接合層２０２を介して接合されている。ここで、接合層２０２は、銀粒子を含有する銀ペーストの焼成体とされている。 The thermoelectric conversion module 201 includes a thermoelectric element 203 and an insulating circuit board 210 disposed on one end side and the other end side of the thermoelectric element 203.
The thermoelectric element 203 is bonded to the circuit layer 220 of the insulating circuit board 210 via the bonding layer 202. Here, the bonding layer 202 is a fired body of silver paste containing silver particles.
　絶縁回路基板２１０は、図１０及び図１１に示すように、セラミックス基板１１と、このセラミックス基板１１の一方の面に配設された回路層２２０と、を備えている。 As shown in FIGS. 10 and 11, the insulated circuit board 210 includes a ceramic substrate 11 and a circuit layer 220 disposed on one surface of the ceramic substrate 11.
　回路層２２０は、図１０及び図１１に示すように、セラミックス基板１１の一方の面に配設されたアルミニウム層２２１と、このアルミニウム層２２１の一方の面に形成されたチタン層２２５と、を有している。
　ここで、回路層２２０におけるアルミニウム層２２１の厚さは、０．１ｍｍ以上１．０ｍｍ以下の範囲内に設定されており、本実施形態では０．６ｍｍに設定されている。
　そして、この回路層２２０には、図１１に示すように、回路パターンが形成されている。 As shown in FIGS. 10 and 11, the circuit layer 220 includes an aluminum layer 221 disposed on one surface of the ceramic substrate 11 and a titanium layer 225 formed on one surface of the aluminum layer 221. Have.
Here, the thickness of the aluminum layer 221 in the circuit layer 220 is set within a range of 0.1 mm to 1.0 mm, and is set to 0.6 mm in the present embodiment.
In the circuit layer 220, a circuit pattern is formed as shown in FIG.
　ここで、アルミニウム層２２１は、図１３に示すように、セラミックス基板１１の一方の面にアルミニウム板２５１が接合されることにより形成されている。
　アルミニウム層２２１となるアルミニウム板２５１は、純度が９９．９９ｍａｓｓ％以上のアルミニウム（４Ｎアルミニウム）で構成されている。なお、アルミニウム層２２１のチタン層２２５側の界面には、Ｓｉの含有量が０．０３ｍａｓｓ％以上１．０ｍａｓｓ％以下の範囲内とされたＳｉ濃化層が形成されている。 Here, as shown in FIG. 13, the aluminum layer 221 is formed by bonding an aluminum plate 251 to one surface of the ceramic substrate 11.
The aluminum plate 251 serving as the aluminum layer 221 is made of aluminum (4N aluminum) having a purity of 99.99 mass% or more. Note that a Si concentrated layer in which the Si content is in the range of 0.03 mass% to 1.0 mass% is formed at the interface of the aluminum layer 221 on the titanium layer 225 side.
　そして、アルミニウム層２２１とチタン層２２５との接合界面には、第一の実施形態及び第二の実施形態と同様に、Ａｌ３ＴｉにＳｉが固溶したＡｌ－Ｔｉ－Ｓｉ層が形成されている。このＡｌ－Ｔｉ－Ｓｉ層は、アルミニウム層２２１のＡｌ原子と、チタン層２２５のＴｉ原子とが相互拡散することによってＡｌ３Ｔｉが形成されるとともに、Ｓｉ濃化層のＳｉが、このＡｌ３Ｔｉに固溶することで形成されている。 As in the first and second embodiments, an Al—Ti—Si layer in which Si is dissolved in Al 3 Ti is formed at the bonding interface between the aluminum layer 221 and the titanium layer 225. Yes. The Al-Ti-Si layer, and the Al atoms of the aluminum layer 221, together with the Al 3 Ti is formed by and the Ti atoms in the titanium layer 225 to interdiffusion, Si of Si concentrated layer, the Al 3 It is formed by dissolving in Ti.
　次に、本実施形態である絶縁回路基板２１０の製造方法について、図１２、図１３を参照して説明する。 Next, a method for manufacturing the insulated circuit board 210 according to the present embodiment will be described with reference to FIGS.
（Ｓｉ濃化層形成工程Ｓ２０１）
　まず、純度が９９．９９ｍａｓｓ％以上のアルミニウム（４Ｎアルミニウム）で構成されたアルミニウム板２５１の一方の面に、Ｓｉを０．０３ｍａｓｓ％以上１．０ｍａｓｓ％以下の範囲内で含有するＳｉ濃化層を形成する。
　具体的には、アルミニウム板２５１の一方の面にＳｉを含有するＳｉ材２５２（例えばＡｌ－Ｓｉろう材等）を配設して加熱処理することにより、Ｓｉ材のＳｉをアルミニウム板２５１側へと拡散させることで、上述のＳｉ濃化層を形成する。
　ここで、Ｓｉ濃度は、チタン層が形成される表面をＥＰＭＡ（電子線マイクロアナライザ）の定量分析で５点測定し、その平均値とした。なお、Ｓｉ濃度はＡｌとＳｉの合計量を１００とした時の濃度とする。 (Si concentrated layer forming step S201)
First, a Si concentrated layer containing Si within a range of 0.03 mass% to 1.0 mass% on one surface of an aluminum plate 251 made of aluminum (4N aluminum) having a purity of 99.99 mass% or higher. Form.
Specifically, a Si material 252 containing Si (for example, an Al—Si brazing material) is disposed on one surface of the aluminum plate 251 and heat-treated, so that Si of the Si material is moved to the aluminum plate 251 side. And the above-described Si concentrated layer is formed.
Here, the Si concentration was obtained by measuring five points on the surface on which the titanium layer is formed by quantitative analysis using EPMA (electron beam microanalyzer), and taking the average value. The Si concentration is the concentration when the total amount of Al and Si is 100.
（チタン材配設工程Ｓ２０２）
　次に、図１２及び図１３に示すように、アルミニウム板１５１の一方の面（Ｓｉ濃化層が形成された面）にチタン材２５５を回路パターン状に配設する。ここで、チタン材２５５を回路パターン状に配設する際には、蒸着やイオンプレーティング等の成膜法を適用してもよい。この場合、メタルマスクを用いてチタン膜を成膜することで、チタン材２５５を回路パターン状に配設することができる。また、チタン箔を回路パターン状に配設してもよい。
　ここで、チタン材２５５の厚さは７μｍ以上２０μｍ以下の範囲内とすることが好ましい。 (Titanium material disposing step S202)
Next, as shown in FIGS. 12 and 13, a titanium material 255 is arranged in a circuit pattern on one surface of the aluminum plate 151 (the surface on which the Si concentrated layer is formed). Here, when the titanium material 255 is arranged in a circuit pattern, a film forming method such as vapor deposition or ion plating may be applied. In this case, by forming a titanium film using a metal mask, the titanium material 255 can be arranged in a circuit pattern. Further, the titanium foil may be arranged in a circuit pattern.
Here, the thickness of the titanium material 255 is preferably in the range of 7 μm to 20 μm.
（チタン層形成工程Ｓ２０３）
　次に、図１２及び図１３に示すように、アルミニウム板２５１の表面にチタン材２５５を配設し、積層方向に加圧（荷重３～２０ｋｇｆ／ｃｍ２）した状態で真空加熱炉内に配置し加熱する。ここで、真空加熱炉内の圧力は１０－６Ｐａ以上１０－３Ｐａ以下の範囲内に、加熱温度は６００℃以上６４０℃以下、保持時間は３０分以上１８０分以下の範囲内に設定されることが好ましい。
　これにより、アルミニウム板２５１とチタン材２５５とが接合され、チタン層２２５が回路パターン状に形成される。このとき、アルミニウム板２５１とチタン層２２５との接合界面には上述のＡｌ－Ｔｉ－Ｓｉ層が形成される。 (Titanium layer forming step S203)
Next, as shown in FIGS. 12 and 13, a titanium material 255 is disposed on the surface of the aluminum plate 251, and is placed in a vacuum heating furnace in a state of being pressurized in the stacking direction (load 3 to 20 kgf / cm 2 ). And heat. Here, the pressure in the vacuum heating furnace is set in the range of 10 −6 Pa to 10 −3 Pa, the heating temperature is set to 600 ° C. to 640 ° C., and the holding time is set in the range of 30 minutes to 180 minutes. It is preferable.
Thereby, the aluminum plate 251 and the titanium material 255 are joined, and the titanium layer 225 is formed in a circuit pattern. At this time, the Al—Ti—Si layer described above is formed at the bonding interface between the aluminum plate 251 and the titanium layer 225.
（セラミックス／アルミニウム接合工程Ｓ２０４）
　次に、図１２及び図１３に示すように、セラミックス基板１１の一方の面に、Ａｌ－Ｓｉ系のろう材箔（図示なし）を介して、チタン層２２５が形成されたアルミニウム板２５１を積層する。
　次いで、積層したアルミニウム板２５１、セラミックス基板１１を、積層方向に加圧（荷重３～２０ｋｇｆ／ｃｍ２）した状態で真空加熱炉内に配置し加熱する。
　これにより、アルミニウム板２５１とセラミックス基板１１を接合し、アルミニウム層２２１を形成する。 (Ceramics / Aluminum Joining Step S204)
Next, as shown in FIGS. 12 and 13, an aluminum plate 251 on which a titanium layer 225 is formed is laminated on one surface of the ceramic substrate 11 with an Al—Si based brazing foil (not shown). To do.
Next, the laminated aluminum plate 251 and the ceramic substrate 11 are placed in a vacuum heating furnace and heated while being pressurized (load 3 to 20 kgf / cm 2 ) in the lamination direction.
Thereby, the aluminum plate 251 and the ceramic substrate 11 are joined, and the aluminum layer 221 is formed.
（エッチング処理工程Ｓ２０５）
　次に、図１２及び図１３に示すように、チタン層２２５が回路パターン状に形成されたアルミニウム層２２１に対してエッチング処理を行う。エッチング剤としては、塩化第二鉄を使用する。このとき、チタン層２２５をレジスト膜として作用させることにより、アルミニウム層２２１を回路パターン状にエッチングする。 (Etching process S205)
Next, as shown in FIGS. 12 and 13, an etching process is performed on the aluminum layer 221 in which the titanium layer 225 is formed in a circuit pattern. As an etchant, ferric chloride is used. At this time, the aluminum layer 221 is etched into a circuit pattern by using the titanium layer 225 as a resist film.
　上述の工程により、アルミニウム層２２１とチタン層２２５とが積層されてなる回路層２２０に回路パターンが形成され、本実施形態である絶縁回路基板２１０が製造される。 Through the above-described steps, a circuit pattern is formed on the circuit layer 220 in which the aluminum layer 221 and the titanium layer 225 are laminated, and the insulated circuit board 210 according to this embodiment is manufactured.
　そして、熱電素子２０３の一端側及び他端側に、銀ペーストを介して、それぞれ絶縁回路基板２１０を、回路層２２０が熱電素子２０３側を向くように積層し、加熱することにより、熱電素子２０３の一端側及び他端側にそれぞれ絶縁回路基板２１０を接合する。これにより、図１０に示す熱電変換モジュール２０１が製造される。 Then, the insulating circuit board 210 is laminated on one end side and the other end side of the thermoelectric element 203 so that the circuit layer 220 faces the thermoelectric element 203 side through silver paste, and is heated, whereby the thermoelectric element 203 is heated. Insulated circuit boards 210 are bonded to one end side and the other end side of each. Thereby, the thermoelectric conversion module 201 shown in FIG. 10 is manufactured.
　以上のような構成とされた本実施形態に係る絶縁回路基板２１０の製造方法によれば、チタン材配設工程Ｓ２０２とチタン層形成工程Ｓ２０３とエッチング処理工程Ｓ２０５とを備えているので、アルミニウム層２２１とチタン層２２５とが積層されてなる回路層２２０に対して、回路パターンを精度良く、かつ、効率良く形成することができる。また、エッチング処理工程Ｓ２０５においてチタン層２２５をレジスト材として使用しているので、レジスト材の塗布工程や剥離工程を省略することができ、エッチング処理工程Ｓ２０５を効率良く行うことができる。 According to the manufacturing method of the insulated circuit board 210 according to the present embodiment configured as described above, since the titanium material disposing step S202, the titanium layer forming step S203, and the etching processing step S205 are provided, the aluminum layer A circuit pattern can be accurately and efficiently formed on the circuit layer 220 in which the layer 221 and the titanium layer 225 are stacked. Further, since the titanium layer 225 is used as a resist material in the etching process S205, the resist material application process and the peeling process can be omitted, and the etching process S205 can be performed efficiently.
　また、本実施形態においては、純度９９．９９ｍａｓｓ％以上のアルミニウム（４Ｎアルミニウム）からなるアルミニウム板２５１のチタン層２２５が形成される側の面に、Ｓｉを０．０３ｍａｓｓ％以上１．０ｍａｓｓ％以下の範囲内で含有するＳｉ濃化層を形成するＳｉ濃化層形成工程Ｓ２０１を有しているので、回路層２２０のアルミニウム層２２１を純度９９．９９ｍａｓｓ％以上のアルミニウム（４Ｎアルミニウム）で構成しても、アルミニウム層２２１とチタン層２２５との間に、第一の実施形態及び第二の実施形態と同様にＡｌ－Ｔｉ－Ｓｉ層を形成させることが可能となる。 Moreover, in this embodiment, 0.03 mass% or more and 1.0 mass% or less of Si is formed on the surface on the side where the titanium layer 225 of the aluminum plate 251 made of aluminum (4N aluminum) having a purity of 99.99 mass% or more is formed. Therefore, the aluminum layer 221 of the circuit layer 220 is made of aluminum (4N aluminum) having a purity of 99.99 mass% or more. However, an Al—Ti—Si layer can be formed between the aluminum layer 221 and the titanium layer 225 as in the first embodiment and the second embodiment.
　また、本実施形態に係る絶縁回路基板２１０及び熱電変換モジュール２０１によれば、アルミニウム層２２１のセラミックス基板１１とは反対側の面にチタン層２２５が形成されているので、このチタン層２２５を拡散防止層として機能させることができる。よって、回路層２１１に搭載された熱電素子２０３に、アルミニウム層２２１のアルミニウムが拡散することを抑制することが可能となる。これにより、熱電素子２０３の特性の劣化を抑制することができる。 Moreover, according to the insulated circuit board 210 and the thermoelectric conversion module 201 according to the present embodiment, the titanium layer 225 is formed on the surface of the aluminum layer 221 opposite to the ceramic substrate 11, so that the titanium layer 225 is diffused. It can function as a prevention layer. Therefore, diffusion of aluminum in the aluminum layer 221 into the thermoelectric element 203 mounted on the circuit layer 211 can be suppressed. Thereby, deterioration of the characteristics of the thermoelectric element 203 can be suppressed.
　以上、本発明の実施形態について説明したが、本発明はこれに限定されることはなく、その発明の技術的思想を逸脱しない範囲で適宜変更可能である。
　例えば、上記実施の形態では、アルミニウム層と、金属部材層として銅からなる銅層とが接合される場合について説明したが、銅層に代えて、ニッケル又はニッケル合金からなるニッケル層、もしくは銀又は銀合金からなる銀層が接合されても良い。 As mentioned above, although embodiment of this invention was described, this invention is not limited to this, It can change suitably in the range which does not deviate from the technical idea of the invention.
For example, in the above embodiment, the case where an aluminum layer and a copper layer made of copper as a metal member layer are joined has been described, but instead of the copper layer, a nickel layer made of nickel or a nickel alloy, or silver or A silver layer made of a silver alloy may be bonded.
　銅層に代えてニッケル層を形成した場合には、はんだ付け性が良好となり、半導体素子やヒートシンクとの接合信頼性を向上できる。さらに、固相拡散接合によってニッケル層を形成する場合には、無電解めっき等でＮｉめっき膜を形成する際に行われるマスキング処理が不要なので、製造コストを低減できる。この場合、ニッケル層の厚さは１μｍ以上３０μｍ以下とすることが望ましい。ニッケル層の厚さが１μｍ未満の場合には半導体素子やヒートシンクとの接合信頼性の向上の効果が無くなるおそれがあり、３０μｍを超える場合にはニッケル層が熱抵抗体となり効率的に熱を伝達できなくなるおそれがある。また、固相拡散接合によってニッケル層を形成する場合、固相拡散接合は、銅層を形成する場合と同様の条件で形成することができる。 When a nickel layer is formed instead of the copper layer, the solderability is good and the bonding reliability with a semiconductor element or a heat sink can be improved. Further, when the nickel layer is formed by solid phase diffusion bonding, the masking process performed when forming the Ni plating film by electroless plating or the like is unnecessary, and thus the manufacturing cost can be reduced. In this case, it is desirable that the thickness of the nickel layer be 1 μm or more and 30 μm or less. If the thickness of the nickel layer is less than 1 μm, the effect of improving the reliability of bonding to the semiconductor element or the heat sink may be lost. If the thickness exceeds 30 μm, the nickel layer becomes a thermal resistor and efficiently transfers heat. There is a risk that it will not be possible. When the nickel layer is formed by solid phase diffusion bonding, the solid phase diffusion bonding can be formed under the same conditions as when the copper layer is formed.
　銅層に代えて銀層を形成した場合には、例えば酸化銀粒子と有機物からなる還元剤とを含む酸化銀ペーストを用いて半導体素子やヒートシンクを接合する際に、酸化銀が還元された銀と銀層とが接続される、即ち同種の金属同士の接合となるため、接合信頼性を向上させることができる。さらには、熱伝導率の良好な銀層が形成されるので、熱を面方向に拡げて効率的に伝達することができる。この場合、銀層の厚さは１μｍ以上２０μｍ以下とすることが望ましい。銀層の厚さが１μｍ未満の場合には半導体素子やヒートシンクとの接合信頼性の向上の効果が無くなるおそれがあり、２０μｍを超える場合には接合信頼性向上の効果が観られなくなり、コストの増加を招く。また、固相拡散接合によって銀層を形成する場合、固相拡散接合は、銅層を形成する場合と同様の条件で形成することができる。 When a silver layer is formed instead of the copper layer, for example, when silver oxide particles containing silver oxide particles and a reducing agent made of an organic material are used to join a semiconductor element or a heat sink, the silver oxide is reduced. And the silver layer are connected, that is, the same kind of metal is bonded to each other, so that the bonding reliability can be improved. Furthermore, since a silver layer with good thermal conductivity is formed, heat can be spread efficiently by spreading in the surface direction. In this case, the thickness of the silver layer is desirably 1 μm or more and 20 μm or less. If the thickness of the silver layer is less than 1 μm, the effect of improving the bonding reliability with the semiconductor element or the heat sink may be lost. If the thickness exceeds 20 μm, the effect of improving the bonding reliability is not observed, and the cost is reduced. Incurs an increase. When the silver layer is formed by solid phase diffusion bonding, the solid phase diffusion bonding can be formed under the same conditions as when the copper layer is formed.
　また、第一の実施形態及び第二の実施形態では、アルミニウム層となるアルミニウム板として、純度が９９ｍａｓｓ％以上の２ＮアルミニウムであってＳｉ含有量が０．０３ｍａｓｓ％以上１．０ｍａｓｓ％以下の範囲内のものを例に挙げて説明したが、これに限定されることはなく、他のアルミニウム材を用いてもよい。
　ここで、純度９９．９９ｍａｓｓ％以上の４Ｎアルミニウム等のようにＳｉを含有しないアルミニウム材を用いる場合には、第三の実施形態で示したように、事前にアルミニウム材のうちチタン層が形成される表面のＳｉ濃度を０．０３ｍａｓｓ％～１．０ｍａｓｓ％に調整してもよい。ここで、Ｓｉ濃度は、チタン層が形成される表面をＥＰＭＡの定量分析で５点測定し、その平均値とする。なお、Ｓｉ濃度はＡｌとＳｉの合計量を１００とした時の濃度とする。 Moreover, in 1st embodiment and 2nd embodiment, as an aluminum plate used as an aluminum layer, it is 2N aluminum whose purity is 99 mass% or more, and Si content is the range of 0.03 mass% or more and 1.0 mass% or less. Although the above was described as an example, the present invention is not limited to this, and other aluminum materials may be used.
Here, when using an aluminum material that does not contain Si, such as 4N aluminum having a purity of 99.99 mass% or more, as shown in the third embodiment, a titanium layer is formed in advance in the aluminum material. The surface Si concentration may be adjusted to 0.03 mass% to 1.0 mass%. Here, the Si concentration is an average value obtained by measuring the surface on which the titanium layer is formed at five points by quantitative analysis of EPMA. The Si concentration is the concentration when the total amount of Al and Si is 100.
　本発明に係る絶縁回路基板の製造方法によれば、回路層に対して回路パターンを精度良く、かつ、効率良く形成することができる。また、本発明の絶縁回路基板は、ＬＥＤ、パワーモジュール等の半導体装置や、熱電変換モジュールに好適である。 According to the method for manufacturing an insulated circuit board according to the present invention, a circuit pattern can be accurately and efficiently formed on a circuit layer. Moreover, the insulated circuit board of this invention is suitable for semiconductor devices, such as LED and a power module, and a thermoelectric conversion module.
１０、１１０、２１０　絶縁回路基板
１１　セラミックス基板
２０、１２０、２２０　回路層
３０，１３０　金属層
２１、１２１、２２１　アルミニウム層
２２、１２２　銅層（金属部材層）
５１、１５１、２５１　アルミニウム板（アルミニウム材）
２５、１２５、２２５　チタン層
５５、１５５、２５５　チタン材
２０１　熱電変換モジュール
２０３　熱電素子 10, 110, 210 Insulated circuit substrate 11 Ceramic substrate 20, 120, 220 Circuit layer 30, 130 Metal layer 21, 121, 221 Aluminum layer 22, 122 Copper layer (metal member layer)
51, 151, 251 Aluminum plate (aluminum material)
25, 125, 225 Titanium layer 55, 155, 255 Titanium material 201 Thermoelectric conversion module 203 Thermoelectric element

Claims (10)

  1. 　セラミックス基板と、このセラミックス基板の一方の面に配設された回路パターンを有する回路層と、を備えた絶縁回路基板の製造方法であって、
    　前記回路層は、前記セラミックス基板の一方の面に配設されたアルミニウム層と、このアルミニウム層の前記セラミックス基板とは反対側の面に形成されたチタン層と、を有しており、
    　アルミニウム材を前記セラミックス基板に接合してアルミニウム層を形成するセラミックス／アルミニウム接合工程と、
    　前記アルミニウム層又は前記アルミニウム材の表面に、チタン層となるチタン材を、前記回路パターン状に配設するチタン材配設工程と、
    　前記アルミニウム層又は前記アルミニウム材の表面に前記チタン材を積層した状態で熱処理を行い、前記チタン層を形成するチタン層形成工程と、
    　前記チタン層が形成された前記アルミニウム層を前記回路パターン状にエッチングするエッチング処理工程と、
    　を備えていることを特徴とする絶縁回路基板の製造方法。     A method of manufacturing an insulated circuit board comprising a ceramic substrate and a circuit layer having a circuit pattern disposed on one surface of the ceramic substrate,
    The circuit layer has an aluminum layer disposed on one surface of the ceramic substrate, and a titanium layer formed on the surface of the aluminum layer opposite to the ceramic substrate,
    A ceramic / aluminum bonding step of bonding an aluminum material to the ceramic substrate to form an aluminum layer;
    A titanium material disposing step of disposing a titanium material to be a titanium layer on the surface of the aluminum layer or the aluminum material in the circuit pattern;
    A titanium layer forming step of performing heat treatment in a state where the titanium material is laminated on the surface of the aluminum layer or the aluminum material, and forming the titanium layer;
    Etching process for etching the aluminum layer on which the titanium layer is formed into the circuit pattern,
    A method for producing an insulated circuit board, comprising:
  2. 　前記回路層は、前記チタン層の前記アルミニウム層とは反対側の面に積層された銅、ニッケルまたは銀からなる金属部材層と、を有しており、
    　前記エッチング処理工程後に、回路パターン状に形成された前記チタン層の表面に前記金属部材層を形成する金属部材層形成工程を備えていることを特徴とする絶縁回路基板の製造方法。     The circuit layer has a metal member layer made of copper, nickel, or silver laminated on a surface of the titanium layer opposite to the aluminum layer,
    A method of manufacturing an insulated circuit board, comprising: a metal member layer forming step of forming the metal member layer on a surface of the titanium layer formed in a circuit pattern after the etching treatment step.
  3. 　前記金属部材層形成工程の前に、前記チタン層の表面を洗浄するチタン層洗浄工程を備えていることを特徴とする請求項２に記載の絶縁回路基板の製造方法。 3. The method for manufacturing an insulated circuit board according to claim 2, further comprising a titanium layer cleaning step for cleaning a surface of the titanium layer before the metal member layer forming step.
  4. 　前記セラミックス／アルミニウム接合工程の後に、前記チタン材配設工程及び前記チタン層形成工程を実施することを特徴とする請求項１から請求項３のいずれか一項に記載の絶縁回路基板の製造方法。 The method for manufacturing an insulated circuit board according to any one of claims 1 to 3, wherein the titanium material disposing step and the titanium layer forming step are performed after the ceramic / aluminum bonding step. .
  5. 　前記チタン層形成工程の後に、前記セラミックス／アルミニウム接合工程を実施することを特徴とする請求項１から請求項３のいずれか一項に記載の絶縁回路基板の製造方法。 The method for manufacturing an insulated circuit board according to any one of claims 1 to 3, wherein the ceramic / aluminum bonding step is performed after the titanium layer forming step.
  6. 　前記チタン層形成工程と、前記セラミックス／アルミニウム接合工程と、を同時に実施することを特徴とする請求項１から請求項３のいずれか一項に記載の絶縁回路基板の製造方法。 The method for manufacturing an insulated circuit board according to any one of claims 1 to 3, wherein the titanium layer forming step and the ceramic / aluminum bonding step are simultaneously performed.
  7. 　前記チタン材配設工程の前に、前記アルミニウム層又は前記アルミニウム材の表面を洗浄するアルミニウム洗浄工程を備えていることを特徴とする請求項１から請求項６のいずれか一項に記載の絶縁回路基板の製造方法。 The insulation according to any one of claims 1 to 6, further comprising an aluminum cleaning step for cleaning the surface of the aluminum layer or the aluminum material before the titanium material disposing step. A method of manufacturing a circuit board.
  8. 　前記チタン材配設工程の前に、前記アルミニウム層又は前記アルミニウム材のうち前記チタン層が形成される側の面に、Ｓｉを０．０３ｍａｓｓ％以上１．０ｍａｓｓ％以下の範囲内で含有するＳｉ濃化層を形成するＳｉ濃化層形成工程を備えていることを特徴とする請求項１から請求項７のいずれか一項に記載の絶縁回路基板の製造方法。 Before the titanium material disposing step, Si containing 0.03 mass% or more and 1.0 mass% or less of Si on the surface of the aluminum layer or the aluminum material on the side where the titanium layer is formed. The method for manufacturing an insulated circuit board according to claim 1, further comprising a Si concentrated layer forming step of forming the concentrated layer.
  9. 　セラミックス基板と、このセラミックス基板の一方の面に配設された回路パターンを有する回路層と、を備えた絶縁回路基板であって、
    　前記回路層は、前記セラミックス基板の一方の面に配設されたアルミニウム層と、このアルミニウム層の前記セラミックス基板とは反対側の面に形成されたチタン層と、を有していることを特徴とする絶縁回路基板。     An insulating circuit board comprising a ceramic substrate and a circuit layer having a circuit pattern disposed on one surface of the ceramic substrate,
    The circuit layer includes an aluminum layer disposed on one surface of the ceramic substrate, and a titanium layer formed on a surface of the aluminum layer opposite to the ceramic substrate. Insulated circuit board.
  10. 　請求項９に記載の絶縁回路基板の前記回路層上に熱電素子が搭載されたことを特徴とする熱電変換モジュール。 A thermoelectric conversion module, wherein a thermoelectric element is mounted on the circuit layer of the insulated circuit board according to claim 9.
PCT/JP2017/023272 2016-06-23 2017-06-23 Method for manufacturing insulated circuit board, insulated circuit board, and thermoelectric conversion module WO2017222061A1 (en)

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US16/306,708 US10798824B2 (en) 2016-06-23 2017-06-23 Method for manufacturing insulated circuit board, insulated circuit board, and thermoelectric conversion module
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