JP2003077757A - Chip capacitor and method of manufacturing the same - Google Patents
Chip capacitor and method of manufacturing the sameInfo
- Publication number
- JP2003077757A JP2003077757A JP2001269486A JP2001269486A JP2003077757A JP 2003077757 A JP2003077757 A JP 2003077757A JP 2001269486 A JP2001269486 A JP 2001269486A JP 2001269486 A JP2001269486 A JP 2001269486A JP 2003077757 A JP2003077757 A JP 2003077757A
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- Prior art keywords
- chip capacitor
- dielectric layer
- electrode
- layer
- dielectric
- Prior art date
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Abstract
Description
【０００１】[0001]
【発明が属する技術分野】本発明は、高周波数帯域（Ｕ
ＨＦ帯以上）に用いられる、高周波用の損失の少ないチ
ップコンデンサに関する。TECHNICAL FIELD The present invention relates to a high frequency band (U
The present invention relates to a chip capacitor used in the HF band or higher) for high frequency with less loss.
【０００２】[0002]
【従来の技術】近年の、携帯電話や無線ＬＡＮなどの無
線通信の高周波数化に伴い、通信機器を構成する電子部
品、なかんずく信号系受動部品の高周波特性の向上が求
められている。たとえば、移動体通信機や基地局の送信
出力増幅回路に用いられるコンデンサに損失があると、
送信電力が低下して遠距離まで電波が届かないことにな
るので、損失を補正するために送信電力を上げる必要が
あり、それだけ電源電力が消耗する。 ことさら、電池
を電源とする携帯用無線通信機の場合は、通話可能時間
が短縮されることになる。2. Description of the Related Art With the recent increase in frequency of wireless communication such as mobile phones and wireless LANs, improvement in high frequency characteristics of electronic parts constituting communication equipment, especially signal system passive parts is required. For example, if there is a loss in the capacitor used in the transmission output amplification circuit of a mobile communication device or base station,
Since the transmission power decreases and radio waves cannot reach a long distance, it is necessary to increase the transmission power to correct the loss, and the power supply power is consumed accordingly. Especially, in the case of a portable wireless communication device that uses a battery as a power source, the callable time is shortened.
【０００３】従来のチップコンデンサを、図２の斜視図
に示す。 内部構造は、図２のＡ−Ａ断面図のように誘
電体層１と、厚み；１０μｍ以下の薄い内層電極層２が
交互に積層され、１層おきの内層電極２が左右の端面に
引き出され外部電極３に、接合部４で接続されている。
基板への実装は、基板のストリップライン端部の、は
んだペーストを塗布した接続ランドに、チップコンデン
サの外部電極３を当接させ、最高温度２５０℃前後のリ
フロー炉に流して、はんだ付けされる。A conventional chip capacitor is shown in the perspective view of FIG. The internal structure is such that the dielectric layers 1 and the thin inner electrode layers 2 having a thickness of 10 μm or less are alternately laminated as shown in the AA cross-sectional view of FIG. 2, and the inner layer electrodes 2 every other layer are drawn out to the left and right end faces. The external electrode 3 is connected to the external electrode 3 at a joint 4.
For mounting on a board, the external electrode 3 of the chip capacitor is brought into contact with the connection land coated with the solder paste at the end of the stripline of the board, and is flown in a reflow furnace at a maximum temperature of about 250 ° C. for soldering. .
【０００４】誘電体の損失をゼロと仮定すると、チップ
コンデンサの等価回路は図３に示すように、無損失コン
デンサ１８と、内層電極と外部電極は、コイル１６と抵
抗１７の直列接続で表わされる。無損失コンデンサ１８
の静電容量値をＣ，コイル１６のインダクタンスをＬと
すると、自己共振周波数は、Ｆ＝１／２π√（ＬＣ）で
表わされ、インダクタンス（Ｌ）が大きいと自己共振周
波数が低くなる。Assuming that the loss of the dielectric is zero, the equivalent circuit of the chip capacitor is represented by a lossless capacitor 18, the inner layer electrode and the outer electrode are connected in series with a coil 16 and a resistor 17, as shown in FIG. . Lossless capacitor 18
Where C is the capacitance value of L and L is the inductance of the coil 16, the self-resonance frequency is represented by F = 1 / 2π√ (LC), and the larger the inductance (L), the lower the self-resonance frequency.
【０００５】一般的に、正常なコンデンサとしての挙動
は、自己共振周波数の１／３以下の周波数帯域であり、
高周波で用いるためにはコンデンサの自己共振周波数を
高くすることが必要である。すなわち、内層電極および
外部電極のインダクタンス（Ｌ）を下げることが重要で
ある。Generally, the behavior as a normal capacitor is a frequency band of 1/3 or less of the self-resonant frequency,
To use at high frequency, it is necessary to increase the self-resonant frequency of the capacitor. That is, it is important to reduce the inductance (L) of the inner layer electrode and the outer electrode.
【０００６】また、図３に示す等価回路の抵抗１７の抵
抗値をＲとすると、コンデンサの損失（Ｄ）は、Ｄ＝２
πｆＣＲ で表わさられる。（π；円周率、ｆ；周波数
Ｈｚ）所定の静電容量値（Ｃ）において、コンデンサの
損失（Ｄ）は、抵抗値（Ｒ）に比例して増加するので、
抵抗１７の抵抗値（Ｒ）を低減させることが重要であ
る。 高電力送信機の送信出力段に使用した場合、前記
損失によるコンデンサの発熱により、コンデンサの実装
基板が焼損する事故が、しばしば発生していた。このた
め、複数のコンデンサを直列および並列接続して、１個
当たりのコンデンサの負荷電力を軽減させる必要があっ
た。When the resistance value of the resistor 17 of the equivalent circuit shown in FIG. 3 is R, the loss (D) of the capacitor is D = 2.
It is represented by πfCR. (Π; circular constant, f; frequency Hz) At a given capacitance value (C), the loss (D) of the capacitor increases in proportion to the resistance value (R).
It is important to reduce the resistance value (R) of the resistor 17. When used in the transmission output stage of a high-power transmitter, the heat generated in the capacitor due to the loss often causes the capacitor mounting board to burn out. Therefore, it is necessary to connect a plurality of capacitors in series and in parallel to reduce the load power of each capacitor.
【０００７】前記の抵抗値は、主に内層電極および外部
電極の導電度と電極層の厚みに依存し、また、製造にお
ける燒結時に内層電極が内部に収縮して、外部電極との
接合が疎になり、図２に示す内層電極と外部電極との接
合部４の接合抵抗が増加される。 さらに、前記の内層
電極および外部電極の抵抗値（Ｒ）およびインダクタン
ス（Ｌ）は、内層電極および外部電極を通過する電流経
路の長さに比例するため、該電流経路長を短縮すること
が重要となる。The above-mentioned resistance value mainly depends on the conductivity of the inner and outer electrodes and the thickness of the electrode layer, and the inner layer electrode shrinks inward during sintering during the manufacturing process, resulting in a loose connection with the outer electrode. Therefore, the bonding resistance of the bonding portion 4 between the inner layer electrode and the outer electrode shown in FIG. 2 is increased. Further, since the resistance value (R) and the inductance (L) of the inner layer electrode and the outer electrode are proportional to the length of the current path passing through the inner layer electrode and the outer electrode, it is important to shorten the current path length. Becomes
【０００８】また、コンデンサの損失による自己発熱の
放熱は表面からの放熱もあるが、誘電体の熱伝導率は低
いため、内部発熱は熱の良導体である内層電極に伝熱し
て、外部電極に伝わり外部電極から放熱、あるいは、は
んだ付けされた基板の配線パターンに伝熱される。 こ
の場合の熱抵抗についても、前記の電気抵抗と同様に、
１０μｍ以下と薄い（即ち、伝熱抵抗の大きい）内層電
極および外部電極を伝熱する伝熱経路の長さに比例する
ため、該伝熱経路長を短縮すること、および電極厚みを
増やすことが重要となる。Further, although heat generated by self-heating due to the loss of the capacitor may be radiated from the surface, since the thermal conductivity of the dielectric is low, the internal heat is transferred to the inner layer electrode, which is a good conductor of heat, to the outer electrode. The heat is transferred from the external electrodes or transferred to the wiring pattern of the soldered board. Regarding the thermal resistance in this case as well as the electrical resistance described above,
Since it is proportional to the length of the heat transfer path that transfers heat to the inner layer electrode and the outer electrode that are as thin as 10 μm or less (that is, have high heat transfer resistance), it is possible to shorten the heat transfer path length and increase the electrode thickness. It becomes important.
【０００９】[0009]
【発明が解決しようとする課題】本発明の課題は、前記
図３のチップコンデンサの等価回路における、内層電極
と外部電極の有する、コイル１６のインダクタンス
（Ｌ）と抵抗１７の抵抗値（Ｒ）を限りなくゼロに近
い、高周波特性に優れたチップコンデンサと、その製造
方法を提供することである。The object of the present invention is to provide the inductance (L) of the coil 16 and the resistance value (R) of the resistor 17 which the inner layer electrode and the outer electrode have in the equivalent circuit of the chip capacitor of FIG. It is an object of the present invention to provide a chip capacitor having excellent high frequency characteristics, which is as close to zero as possible, and a manufacturing method thereof.
【００１０】[0010]
【課題を解決するための手段】上記課題を解決するため
に、本発明は誘電体層の両面にコンデンサとしての対向
電極を接合し、該対向電極に外部接続端子機能を備えさ
せる。 すなわち、図１に示すように、誘電体層１の両
面にコンデンサとしての対向電極と外部接続端子の両者
の機能を備える一体化電極５を接合させる。 また前記
チップコンデンサを、誘電体層が実装基板に垂直になる
ように搭載した場合に、少なくとも底面に自立する厚み
を備えて自立させ、信号電流の経路を短縮させる。 ま
た、前記チップコンデンサの誘電体層の両面に、電極層
を放電プラズマ燒結技術（ＳＰＳ法）を用いて燒結接合
し、個片に分割する。In order to solve the above-mentioned problems, the present invention joins opposite electrodes as capacitors to both surfaces of a dielectric layer, and provides the opposite electrodes with an external connection terminal function. That is, as shown in FIG. 1, the integrated electrodes 5 having the functions of both the counter electrode as a capacitor and the external connection terminal are bonded to both surfaces of the dielectric layer 1. Further, when the chip capacitor is mounted so that the dielectric layer is vertical to the mounting substrate, the chip capacitor has at least a thickness to be self-supporting at the bottom surface to shorten the signal current path. Further, electrode layers are sintered and bonded on both surfaces of the dielectric layer of the chip capacitor by using a discharge plasma sintering technique (SPS method), and divided into individual pieces.
【００１１】また、前記チップコンデンサの誘電体層の
両面に接合される予定の一体化電極層面に予め誘電体層
を形成しておき、該誘電体層を内側にして直接接合、あ
るいは誘電体層を挟んで接合してチップコンデンサを形
成する。また、前記チップコンデンサの誘電体層両面の
電極層を、接着層を介して接着させる。さらに、前記誘
電体層と対向電極層のそれぞれに、絶縁性のグリーンシ
ートと、導電性のグリーンシートを用いて積層圧着し焼
成した後、個片に切断してチップコンデンサを形成す
る。Further, a dielectric layer is formed in advance on the surface of the integrated electrode layer to be bonded to both surfaces of the dielectric layer of the chip capacitor, and the dielectric layer is placed inside to directly bond or the dielectric layer. A chip capacitor is formed by sandwiching and joining. Further, the electrode layers on both surfaces of the dielectric layer of the chip capacitor are adhered via an adhesive layer. Further, an insulating green sheet and a conductive green sheet are laminated and pressure-bonded on each of the dielectric layer and the counter electrode layer, baked, and then cut into individual pieces to form a chip capacitor.
【００１２】無機あるいは有機材料からなる図１に示す
誘電体層１の両面に、コンデンサとしての対向電極と外
部接続端子の、両者の機能を備える一体化電極５を接合
させる。 これにより、図２の従来のチップコンデンサ
Ａ−Ａ断面図に示すように、信号電流が内層電極２の面
に沿って流れることなく、本発明のチップコンデンサは
断面方向に信号電流が短距離で通過できるので、インダ
クタンス（Ｌ）および抵抗値（Ｒ）が低減され、また、
内層電極２と外部電極３の接合部４が存在しないので接
合抵抗がなくなる。このため、本発明のチップコンデン
サの、前記の自己共振周波数がさらに高くなり、また損
失も低減される。An integrated electrode 5 having both functions of a counter electrode as a capacitor and an external connection terminal is bonded to both surfaces of a dielectric layer 1 shown in FIG. 1 made of an inorganic or organic material. As a result, the signal current does not flow along the surface of the inner-layer electrode 2 as shown in the conventional chip capacitor AA cross-sectional view of FIG. Since it can pass, the inductance (L) and resistance value (R) are reduced, and
Since there is no joint 4 between the inner layer electrode 2 and the outer electrode 3, there is no joint resistance. Therefore, the self-resonant frequency of the chip capacitor of the present invention is further increased and the loss is reduced.
【００１３】また本発明は、図１に示す、誘電体層１の
両面に対向電極と外部端子機能を備えた一体化電極５を
接合してなることを特徴とするチップコンデンサにおい
て、前記チップコンデンサを、誘電体層が実装基板に垂
直になるように搭載した場合に、少なくとも底面に自立
できる厚みを備えたチップコンデンサを構成する。Further, the present invention relates to a chip capacitor as shown in FIG. 1, characterized in that an opposing electrode and an integrated electrode 5 having an external terminal function are joined to both surfaces of the dielectric layer 1 in the chip capacitor. Is mounted so that the dielectric layer is perpendicular to the mounting substrate, a chip capacitor having a thickness capable of standing at least on the bottom surface is formed.
【００１４】誘電体層を実装基板に垂直になるように搭
載した場合に、チップコンデンサが自立しているので、
その状態でリフロー炉に流して、はんだ付けされる。チ
ップコンデンサを流れる信号電流は、誘電体層の略垂直
方向に通過することになり、信号電流の通過経路が短縮
されるので、前記インダクタンス（Ｌ）と抵抗値（Ｒ）
も減少する。 このとき、図１に示す、一体化電極層５
のそれぞれの厚みは、図２に示す従来のチップコンデン
サの内層電極２のように薄すぎると、前記インダクタン
ス（Ｌ）と抵抗値（Ｒ）が小さくならず、また、厚すぎ
ると信号電流の経路が長くなるので、少なくとも底面に
搭載基板上に自立できる最小の厚みを備えることが好ま
しい。Since the chip capacitor is self-supporting when the dielectric layer is mounted vertically on the mounting substrate,
In that state, it is poured into a reflow furnace and soldered. The signal current flowing through the chip capacitor will pass in a direction substantially perpendicular to the dielectric layer, and the passage of the signal current will be shortened, so that the inductance (L) and the resistance value (R) will be obtained.
Also decreases. At this time, the integrated electrode layer 5 shown in FIG.
If the thickness of each of the above is too thin like the inner layer electrode 2 of the conventional chip capacitor shown in FIG. 2, the inductance (L) and the resistance value (R) do not become small. Therefore, it is preferable that at least the bottom surface has a minimum thickness that can stand on the mounting substrate.
【００１５】また本発明は、前記チップコンデンサの誘
電体層の両面に一体化電極層を放電プラズマ燒結技術
（ＳＰＳ法）を用いて燒結接合し、個片に分割して形成
してなることを特徴とするチップコンデンサ、およびそ
の製造方法である。According to the present invention, the integrated electrode layers are sintered and bonded to each other on both sides of the dielectric layer of the chip capacitor by using a discharge plasma sintering technique (SPS method), and are formed by dividing into individual pieces. A characteristic chip capacitor and a method for manufacturing the same.
【００１６】前記チップコンデンサの誘電体層の両面に
一体化電極層を放電プラズマ燒結技術（ＳＰＳ法）を用
いて燒結接合することで、出発原料の粒成長を抑制で
き、超微細材料を超微細サイズのままバルク化でき、さ
らに短時間で緻密な燒結体が得られるので電気特性に優
れた、接合強度の大きいチップコンデンサが得られ 図
５に示すように、燒結用下型１１の中に、多数個取り用
の一体化電極板１４と、多数個取り用の誘電体凝固粉末
体１５を図示の順に入れ、上から燒結用上型１０で押さ
えて放電プラズマ燒結機にセットし、加圧状態でプラズ
マ放電させて、多数個取り用の燒結板を得た。 つい
で、図６に示すように多数個取り用の燒結板１３を切断
線１２に沿ってダイシングソウで個片に切断し、多数の
チップコンデンサに分割した。By sintering and joining the integrated electrode layers on both surfaces of the dielectric layer of the chip capacitor by using the discharge plasma sintering technique (SPS method), it is possible to suppress the grain growth of the starting material and to make the ultrafine material ultrafine. Since the size can be made into bulk, and a dense sintered body can be obtained in a shorter time, a chip capacitor having excellent electrical characteristics and high bonding strength can be obtained, and as shown in FIG. The multi-cavity integrated electrode plate 14 and the multi-cavity dielectric solidified powder body 15 are put in the order shown in the figure, and are pressed by the sintering upper die 10 from above and set in the discharge plasma sintering machine, and are pressed. Plasma discharge was carried out in order to obtain a sintered plate for taking a large number of pieces. Next, as shown in FIG. 6, the sintered plate 13 for taking a large number of pieces was cut along the cutting line 12 into individual pieces with a dicing saw, and divided into a large number of chip capacitors.
【００１７】また本発明は、前記チップコンデンサの誘
電体層の両面に接合される予定の一体化電極層面に予め
誘電体層を形成しておき、該誘電体層を内側にして直接
接合、あるいは誘電体層を挟んで接合してなることを特
徴とするチップコンデンサ、およびその製造方法であ
る。Further, according to the present invention, a dielectric layer is previously formed on the surface of the integrated electrode layer to be bonded to both surfaces of the dielectric layer of the chip capacitor, and the dielectric layer is placed inside and directly bonded, or A chip capacitor, characterized by being joined with a dielectric layer sandwiched therebetween, and a manufacturing method thereof.
【００１８】誘電体層と一体化電極層の接合は、誘電体
材料と電極材料の組み合わせにより、接合しにくい場合
がある。 この場合、あらかじめ電気特性にすぐれた誘
電体層を、真空蒸着、スパッタ技術などを用いて、薄く
電極板に形成しておき、該誘電体層を介して誘電体を接
合させることで、接合性が向上するまた、あらかじめコ
ンデンサ特性にすぐれた誘電体層を、電極板に塗布形成
しておき、該誘電体層どうしを直接接合して、焼成ある
いは加熱硬化させチップコンデンサを形成してもよい。The joining of the dielectric layer and the integrated electrode layer may be difficult depending on the combination of the dielectric material and the electrode material. In this case, a dielectric layer having excellent electrical characteristics is formed in advance on the electrode plate thinly by using vacuum deposition, sputtering technique, etc., and the dielectric is bonded through the dielectric layer to improve the bonding property. In addition, a dielectric layer having excellent capacitor characteristics may be formed by coating on the electrode plate in advance, and the dielectric layers may be directly bonded to each other and baked or heat-cured to form a chip capacitor.
【００１９】また本発明は、前記チップコンデンサの誘
電体層の両面と、一体化電極層の間に接着層を介して接
着してなることを特徴とするチップコンデンサ、および
その製造方法である。The present invention also provides a chip capacitor, characterized in that both surfaces of a dielectric layer of the chip capacitor are bonded to an integrated electrode layer via an adhesive layer, and a manufacturing method thereof.
【００２０】前記の、あらかじめ、薄く電極板に形成さ
れる誘電体層として、誘電体としての電気特性と共に、
接着性に優れた接着層を介して誘電体を接合させること
で、接合性に劣る材料の組み合わせの接合も可能とな
る。 特に、誘電体層がプラスチックなどの有機材料よ
りなる場合、電極板への直接接合は困難であるので、有
機接着材を介して接合させる。 なお、無機材料の場合
も、一体化電極の１面に塗布された低融点ガラス層を介
して誘電体層を積層し、加熱溶融させて接合させること
ができる。As the above-mentioned dielectric layer thinly formed on the electrode plate, together with the electric characteristics as a dielectric,
By joining the dielectrics via the adhesive layer having excellent adhesiveness, it is possible to join a combination of materials having poor adhesiveness. In particular, when the dielectric layer is made of an organic material such as plastic, it is difficult to directly bond it to the electrode plate, and therefore the organic material is used for bonding. In the case of an inorganic material, it is also possible to stack the dielectric layers via the low melting point glass layer coated on one surface of the integrated electrode, and heat and melt the layers for bonding.
【００２１】また本発明は、前記誘電体層と対向電極層
のそれぞれに、絶縁性のグリーンシートと、導電性のグ
リーンシートを用いて積層圧着し、焼成してなることを
特徴とするチップコンデンサ、およびその製造方法であ
る。Further, the present invention is characterized in that an insulating green sheet and a conductive green sheet are laminated and pressure-bonded to each of the dielectric layer and the counter electrode layer, and the chip capacitor is fired. , And a manufacturing method thereof.
【００２２】誘電体セラミックと有機バインダー、など
からなる誘電体グリーンシートの上下に、銀、銅、パラ
ジウムなどと有機バインダー他からなる導電体グリーン
シートを積層して、加圧後に焼成して、多数個取りのコ
ンデンサ板を形成し、個片に切断分離して、多数のチッ
プコンデンサを形成する。Conductor green sheets made of silver, copper, palladium, etc. and an organic binder are laminated on top and bottom of a dielectric green sheet made of a dielectric ceramic and an organic binder. A single capacitor plate is formed and cut into individual pieces to form a large number of chip capacitors.
【００２３】[0023]
【発明の実施の形態】誘電体層の両面に、コンデンサと
しての対向電極に、外部接続端子機能を備えさせた電極
を接合させる。 また、前記チップコンデンサを、誘電
体層が実装基板に垂直になるように搭載した場合に、該
コンデンサの少なくとも底面に、自立できる厚みを備え
させておく。 また、前記チップコンデンサの誘電体層
の両面に接合される予定の一体化電極層面に予め誘電体
層を形成しておき、該誘電体層を内側にして直接接合、
あるいは誘電体層を挟んで接合させる。 また、前記チ
ップコンデンサの誘電体層両面の一体化電極層を、接着
層を介して接着させる。さらに、前記誘電体層と対向電
極層のそれぞれに、絶縁性のグリーンシートと、導電性
のグリーンシートを用いて積層圧着し焼成した後、複数
の個片に切断してチップコンデンサを形成する。BEST MODE FOR CARRYING OUT THE INVENTION Electrodes having an external connection terminal function are joined to opposite electrodes as a capacitor on both surfaces of a dielectric layer. Further, when the chip capacitor is mounted so that the dielectric layer is perpendicular to the mounting substrate, at least the bottom surface of the capacitor is provided with a thickness capable of standing up. Further, a dielectric layer is previously formed on the surface of the integrated electrode layer to be bonded to both surfaces of the dielectric layer of the chip capacitor, and the dielectric layer is placed inside and directly bonded,
Alternatively, the dielectric layers are sandwiched and bonded. Further, the integrated electrode layers on both surfaces of the dielectric layer of the chip capacitor are adhered via an adhesive layer. Further, an insulating green sheet and a conductive green sheet are laminated and pressure-bonded on each of the dielectric layer and the counter electrode layer, baked, and then cut into a plurality of pieces to form a chip capacitor.
【００２４】[0024]
【実施例１】純度９７％のアルミナフィルム燒結体の、
５０ｍｍ角で厚み；１００μｍのシートの両面に、銀ペ
ーストを全面スクリーン印刷した後、ピーク温度８５０
℃で焼き付け処理を行った後、ダイシングソウで３．０
ｍｍ角のコンデンサ素子に切断した。Example 1 A sintered alumina film having a purity of 97%,
After the silver paste is screen-printed on both sides of a sheet of 50 mm square and a thickness of 100 μm, the peak temperature is 850.
After baking at ℃, 3.0 with dicing saw
The capacitor element was cut into mm square.
【００２５】つぎに、Ｌの字型に曲げた厚さ；０．３ｍ
ｍの銀板をコンデンサ素子の両面に、ウレタン系の導電
性樹脂ペーストで接合させ、２００℃、３０分間の加熱
処理を施して、図７に示すチップコンデンサを作成し
た。 なお、銀を焼き付けた５０ｍｍ角のシートを、
３．０ｍｍ幅の短冊に切断し、同じく３．０ｍｍ幅で長
さが５０ｍｍの、Ｌの字型に曲げた厚さ；０．３ｍｍの
銀板をコンデンサ素子の両面に接合してから、幅３．０
ｍｍの個片に切断してもよい。Next, the thickness bent into an L shape: 0.3 m
A silver plate of m was bonded to both surfaces of the capacitor element with a urethane-based conductive resin paste, and heat treatment was performed at 200 ° C. for 30 minutes to prepare a chip capacitor shown in FIG. 7. In addition, a 50 mm square sheet baked with silver
Cut into 3.0 mm wide strips, the thickness is also 3.0 mm wide and 50 mm long, bent into an L-shape; 0.3 mm silver plates are joined to both sides of the capacitor element, and then the width 3.0
It may be cut into mm pieces.
【００２６】[0026]
【実施例２】実施例１と同様に、純度９７％のアルミナ
フィルム燒結体の、５０ｍｍ角で厚み；１００μｍのシ
ートの両面に、銀ペーストを全面スクリーン印刷した
後、ピーク温度８５０℃で焼き付け処理を行った後、ダ
イシングソウで３．０ｍｍ角のコンデンサ素子に切断し
た。つぎに、銀メッキされた厚さ；０．２ｍｍの銅板を
コの字型に曲げ、コンデンサ素子の両面に、ウレタン系
の導電性樹脂ペーストで接合させ、２００℃、３０分間
の加熱処理を施して、図８に示すチップコンデンサを作
成した。[Example 2] Similar to Example 1, a silver paste sintered body having a purity of 97% and a thickness of 50 mm square and a sheet of 100 µm was screen-printed with silver paste on both sides, and then baked at a peak temperature of 850 ° C. After that, it was cut into a 3.0 mm square capacitor element with a dicing saw. Next, a silver-plated; 0.2 mm thick copper plate is bent into a U-shape, bonded to both sides of the capacitor element with a urethane-based conductive resin paste, and subjected to heat treatment at 200 ° C. for 30 minutes. Then, the chip capacitor shown in FIG. 8 was prepared.
【００２７】[0027]
【実施例３】出発原料として、おおよそ２〜３μｍの銀
粉末をプレス金型に入れ、１平方ｃｍあたり約５トンを
加圧プレスして、厚み；１．４ｍｍ、直径３０ｍｍΦ、
の円板に成形した。その後、ボックス炉に入れ、ピーク
温度約９００℃で銀の焼成をおこない銀電極板を形成し
た。 得られた銀電極の１面に、真空技術（ＣＶＤ法）
を用いて、アルミナをスパッタさせ、厚み約１０μｍの
誘電体膜を形成した後に、同様に低融点ガラス膜をスパ
ッタ形成した。 その後、真空チャンバーより取り出
し、２枚の電極板の成膜面を対向させて積層し加圧状態
で加熱して、前記低融点ガラスを再溶融させて接合させ
た後、ワイヤーソウで３ｍｍ角のチップコンデンサに切
断した。Example 3 As a starting material, silver powder of about 2 to 3 μm was put into a press die, and about 5 tons per 1 cm 2 was pressure-pressed to obtain a thickness of 1.4 mm and a diameter of 30 mmΦ.
Formed into a circular plate. Then, it was put in a box furnace and silver was baked at a peak temperature of about 900 ° C. to form a silver electrode plate. On one surface of the obtained silver electrode, vacuum technology (CVD method)
Using, the alumina was sputtered to form a dielectric film having a thickness of about 10 μm, and then a low melting point glass film was similarly sputtered. Then, it was taken out from the vacuum chamber, and the film-forming surfaces of the two electrode plates were laminated so as to face each other and heated in a pressurized state to remelt the low melting glass and bond them together, and then use a wire saw to measure 3 mm square. Cut into chip capacitors.
【００２８】また、銀電極の１面に、真空技術（ＣＶＤ
法）を用いて、アルミナをスパッタさせ、厚み約１０μ
ｍの誘電体膜を形成した銀電極板２個づつを、誘電体膜
の形成面が対向するようにして、シリコーン系の無機接
着材で接合させ、本発明のチップコンデンサを形成し
た。In addition, a vacuum technique (CVD
Method) is used to sputter alumina to obtain a thickness of about 10 μm.
Two silver electrode plates each having a dielectric film of m formed thereon were joined with a silicone-based inorganic adhesive so that the surfaces on which the dielectric films were formed faced to each other to form the chip capacitor of the present invention.
【００２９】[0029]
【実施例４】実施例２と同様に、出発原料として、おお
よそ２〜３μｍの銀粉末をプレス金型に入れ、１平方ｃ
ｍあたり約５トンを加圧プレスして、厚み；１．４ｍ
ｍ、直径３０ｍｍΦ、の円板に成形した。その後、ボッ
クス炉に入れ、ピーク温度約９００℃で焼成して銀電極
板を形成し、ワイヤーソウで３ｍｍ角の個片に切断し
た。他方、主機能としての誘電体層を形成するべく、純
度９７％のアルミナ燒結体の、３０ｍｍ角、厚み；１０
０μｍのシート両面に、銀ペーストをスクリーン印刷し
た後、ピーク温度；８５０℃で焼付けをした。その後、
ダイシングソウを用い、２．５ｍｍ角の個片に切断し、
コンデンサ素子を形成した。 つぎに、コンデンサ素子
の両面に、前記の個片銀電極をウレタン系の導電性樹脂
ペーストで接合させ、２００℃、３０分間の加熱処理を
施して、本発明によるチップコンデンサを作成した。Example 4 Similar to Example 2, silver powder of about 2 to 3 μm was put into a press die as a starting material, and 1 square c
Pressing about 5 tons per meter, thickness: 1.4m
It was molded into a disk having a diameter of m and a diameter of 30 mmΦ. Then, it was put in a box furnace, baked at a peak temperature of about 900 ° C. to form a silver electrode plate, and cut into pieces of 3 mm square with a wire saw. On the other hand, in order to form a dielectric layer as a main function, an alumina sintered body having a purity of 97%, 30 mm square, thickness; 10
A silver paste was screen-printed on both sides of the 0 μm sheet, and then baked at a peak temperature of 850 ° C. afterwards,
Using a dicing saw, cut into 2.5 mm square pieces,
A capacitor element was formed. Next, the individual silver electrodes described above were bonded to both surfaces of the capacitor element with a urethane-based conductive resin paste, and heat treatment was performed at 200 ° C. for 30 minutes to prepare a chip capacitor according to the present invention.
【００３０】[0030]
【実施例５】出発原料として、アルミナ（Ａｌ２Ｏ３）
と、ホウケイ酸ガラス（ＺｎＯ．ＳｉＯ２．Ｂ２Ｏ３）
粉末を、５０；５０の等重量比で秤量して混合し、純水
を加え１６時間ジルコニアボールを用いてボールミルに
かけて湿式混合した後、１２０℃で３時間乾燥してセラ
ミック粉末を得た つぎに、得られたセラミック粉末を
ライカイ機で粉砕した後、有機バインダー、可塑剤、分
散剤、および有機溶剤と共に、ジルコニアボールを用い
てボールミルにかけて湿式混合してスリップを得た。つ
いで、得られたスリップをドクターブレード装置にかけ
て、厚さ；１００μｍの誘電体グリーンシートに成形し
た。Example 5 Alumina (Al2O3) as a starting material
And borosilicate glass (ZnO.SiO2.B2O3)
The powders were weighed and mixed in an equal weight ratio of 50:50, added with pure water, wet-mixed in a ball mill using zirconia balls for 16 hours, and then dried at 120 ° C for 3 hours to obtain a ceramic powder. The obtained ceramic powder was pulverized by a liquor machine and then wet mixed with an organic binder, a plasticizer, a dispersant, and an organic solvent by using a zirconia ball in a ball mill to obtain a slip. Then, the obtained slip was applied to a doctor blade device to form a dielectric green sheet having a thickness of 100 μm.
【００３１】他方、前記同様に、銀粉末と有機バインダ
ー、可塑剤、分散剤、および有機溶剤と共に、ジルコニ
アボールを用いてボールミルにかけて湿式混合してスリ
ップを得た。 ついで、得られたスリップをドクターブ
レード装置にかけて、厚さ；１００μｍの導電体グリー
ンシートに成形した。次に、前記の１枚の誘電体グリー
ンシート上下に、それぞれ１７枚の導電体グリーンシー
トを積層し、静水圧加圧装置（ＣＩＰ機）を用いて圧着
させた積層体をダイシングソウで３．４ｍｍ角の個片に
切断後、コンベア炉に流して脱脂、焼成過程を経てチッ
プコンデンサを得た。On the other hand, in the same manner as described above, a silver powder, an organic binder, a plasticizer, a dispersant, and an organic solvent were wet mixed in a ball mill using zirconia balls to obtain a slip. Then, the obtained slip was applied to a doctor blade device to form a conductor green sheet having a thickness of 100 μm. Next, 17 conductor green sheets were laminated on each of the above-mentioned one dielectric green sheet and pressed by using a hydrostatic pressure device (CIP machine) to form a laminated body with a dicing saw. After being cut into 4 mm square pieces, they were passed through a conveyor furnace to be degreased and fired to obtain chip capacitors.
【００３２】得られたチップコンデンサと、比較例とし
て従来の２．０×１．２５ｍｍ角のを、Ｒｆ Ｉｍｐｅ
ａｄａｎｓｅ／ｍａｔｅｒｉａｌ ａｎａｌｙｚｅｒ；
ｈｐ４２９１Ａ（ヒューレットパッカード社製）を用い
て、１００ＭＨｚ〜１．８ＧＨｚ帯で、静電容量と、等
化直列抵抗（ＥＳＲ）の変化を測定した。測定結果は、
グラフ１に示す静電容量（Ｃａｐ）の周波数特性と、グ
ラフ２に示す等価直列抵抗の周波数特性より、実施例４
（２．８ｍｍ×２．８ｍｍ：Ａｇ電極品）のチップコン
デンサが、特に高周波数領域で優れていることは明白で
ある。The obtained chip capacitor and a conventional 2.0 × 1.25 mm square were used as a comparative example and Rf Impe
adanse / material analyzer;
Using hp4291A (manufactured by Hewlett-Packard Co.), changes in capacitance and equalization series resistance (ESR) were measured in the 100 MHz to 1.8 GHz band. The measurement result is
From the frequency characteristic of the capacitance (Cap) shown in Graph 1 and the frequency characteristic of the equivalent series resistance shown in Graph 2, Example 4
It is clear that the chip capacitor of (2.8 mm × 2.8 mm: Ag electrode product) is excellent especially in the high frequency region.
【グラフ１】 [Graph 1]
【グラフ２】 [Graph 2]
【００３３】[0033]
【発明の効果】本発明により、図３のチップコンデンサ
の等価回路における、内層電極と外部電極の有する、コ
イル１６のインダクタンス（Ｌ）と抵抗１７の抵抗値
（Ｒ）を限りなくゼロに近くした、高周波特性に優れた
チップコンデンサと、その製造方法を提供できる。According to the present invention, the inductance (L) of the coil 16 and the resistance value (R) of the resistor 17 which the inner layer electrode and the outer electrode have in the equivalent circuit of the chip capacitor of FIG. It is possible to provide a chip capacitor having excellent high frequency characteristics and a manufacturing method thereof.
【００３４】[0034]
【図１】本発明のチップコンデンサ例を示す。FIG. 1 shows an example of a chip capacitor of the present invention.
【図２】従来のチップコンデンサ例を示す。FIG. 2 shows an example of a conventional chip capacitor.
【図３】チップコンデンサの等価回路図を示す。FIG. 3 shows an equivalent circuit diagram of a chip capacitor.
【図４】本発明のチップコンデンサを基板搭載した側面
図を示す。FIG. 4 is a side view showing the chip capacitor of the present invention mounted on a substrate.
【図５】放電プラズマ燒結技術（ＳＰＳ法）の加圧型へ
の装着説明図を示す。FIG. 5 is an explanatory view of mounting the discharge plasma sintering technology (SPS method) on a pressure mold.
【図６】個片への切断説明図を示す。FIG. 6 shows an explanatory view of cutting into individual pieces.
【図７】実施例１のチップコンデンサの斜視図を示す。FIG. 7 shows a perspective view of the chip capacitor of the first embodiment.
【図８】実施例１のチップコンデンサの斜視図を示す。FIG. 8 shows a perspective view of the chip capacitor of the first embodiment.
【符号の説明】 １ 誘電体層 ２ 内層電極 ３ 外部電極 ４ 内層電極と外装電極の接合部 ５ 一体化電極 ６ 本発明のチップコンデンサ ７ はんだヒュレット ８ 基板の配線パターン ９ 配線基板 １０ 放電プラズマ燒結用上型 １１ 放電プラズマ燒結用下型 １２ 切断線 １３ 多数個取り用燒結板 １４ 多数個取り用一体化電極板 １５ 多数個取り用一体化誘電体凝固粉末体 １６ コイル １７ 抵抗 １８ 無損失コンデンサ[Explanation of symbols] 1 Dielectric layer 2 Inner layer electrode 3 external electrodes 4 Joint between inner layer electrode and outer electrode 5 integrated electrodes 6 Chip capacitor of the present invention 7 Solder hulet 8 Board wiring pattern 9 wiring board 10 Upper mold for sintering spark plasma 11 Discharge plasma sintering lower mold 12 cutting lines 13 Sintered plate for multiple pieces 14 Multi-piece integrated electrode plate 15 Integrated dielectric solidified powder body for multi-cavity production 16 coils 17 Resistance 18 lossless capacitors
Claims (6)
対向電極を接合し、該対向電極に外部接続端子機能を備
えさせたことを特徴とするチップコンデンサ。1. A chip capacitor comprising a counter electrode as a capacitor joined to both surfaces of a dielectric layer, and the counter electrode having an external connection terminal function.
いて、前記誘電体層の両面に、外部接続端子機能を備え
る対向電極が接合されたチップコンデンサを、誘電体層
が実装基板に垂直になるように搭載した場合に、少なく
とも底面に、自立する厚みを備えることを特徴とするチ
ップコンデンサ。2. The chip capacitor according to claim 1, wherein a counter electrode having an external connection terminal function is bonded to both surfaces of the dielectric layer so that the dielectric layer is perpendicular to the mounting substrate. A chip capacitor having a thickness such that it is self-supporting at least on the bottom surface when mounted on a chip capacitor.
ップコンデンサにおいて、該チップコンデンサの誘電体
層の両面に、電極層を放電プラズマ燒結技術（ＳＰＳ
法）を用いて燒結接合し、個片に分割してなることを特
徴とするチップコンデンサ、およびその製造方法。3. The chip capacitor according to claim 1, wherein an electrode layer is formed on both surfaces of a dielectric layer of the chip capacitor by a discharge plasma sintering technique (SPS).
Method) is used for sintering and joining, and divided into individual pieces, and a manufacturing method thereof.
ップコンデンサにおいて、前記チップコンデンサの誘電
体層の両面に接合される予定の一体化電極層面に予め誘
電体層を形成しておき、該誘電体層を内側にして直接接
合、あるいは誘電体層を挟んで接合してなることを特徴
とするチップコンデンサ、およびその製造方法。4. The chip capacitor according to claim 1, wherein a dielectric layer is previously formed on an integrated electrode layer surface to be bonded to both surfaces of the dielectric layer of the chip capacitor, A chip capacitor, which is directly bonded with the dielectric layer inside, or is bonded with a dielectric layer sandwiched therebetween, and a manufacturing method thereof.
ップコンデンサにおいて、該チップコンデンサの誘電体
層両面の電極層が、接着層を介して接着してなることを
特徴とするチップコンデンサ、およびその製造方法。5. The chip capacitor according to claim 1, wherein the electrode layers on both surfaces of the dielectric layer of the chip capacitor are adhered via an adhesive layer, And its manufacturing method.
ップコンデンサにおいて、前記誘電体層と対向電極層の
それぞれに、絶縁性のグリーンシートと、導電性のグリ
ーンシートを用いて積層圧着し、焼成してなることを特
徴とするチップコンデンサ、およびその製造方法。6. The chip capacitor according to claim 1, wherein an insulating green sheet and a conductive green sheet are laminated and pressure-bonded to each of the dielectric layer and the counter electrode layer. A chip capacitor characterized by being baked, and a manufacturing method thereof.
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|---|---|---|---|
| JP2001269486A JP2003077757A (en) | 2001-09-05 | 2001-09-05 | Chip capacitor and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001269486A JP2003077757A (en) | 2001-09-05 | 2001-09-05 | Chip capacitor and method of manufacturing the same |
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| Publication Number | Publication Date |
|---|---|
| JP2003077757A true JP2003077757A (en) | 2003-03-14 |
Family
ID=19095297
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011193080A (en) * | 2010-03-12 | 2011-09-29 | Ube Industries Ltd | Branching filter |
| JP2016127290A (en) * | 2014-12-29 | 2016-07-11 | サムソン エレクトロ−メカニックス カンパニーリミテッド． | Circuit board and manufacturing method of the same |
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| JPH11260653A (en) * | 1998-03-16 | 1999-09-24 | Tdk Corp | Laminated electronic component and manufacturing method therefor |
| JP2000313661A (en) * | 1999-04-27 | 2000-11-14 | Sekisui Plastics Co Ltd | Discharge plasma sintered compact and its production |
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|---|---|---|---|---|
| JPH04239711A (en) * | 1991-01-23 | 1992-08-27 | Toshiba Corp | Laminated ceramic capacitor |
| JPH104029A (en) * | 1996-06-17 | 1998-01-06 | Tokin Corp | Thin film capacitor and method for manufacturing the same |
| JPH11260653A (en) * | 1998-03-16 | 1999-09-24 | Tdk Corp | Laminated electronic component and manufacturing method therefor |
| JP2000313661A (en) * | 1999-04-27 | 2000-11-14 | Sekisui Plastics Co Ltd | Discharge plasma sintered compact and its production |
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| JP2011193080A (en) * | 2010-03-12 | 2011-09-29 | Ube Industries Ltd | Branching filter |
| JP2016127290A (en) * | 2014-12-29 | 2016-07-11 | サムソン エレクトロ−メカニックス カンパニーリミテッド． | Circuit board and manufacturing method of the same |
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