CN114974895B - Multilayer ceramic binary capacitor based on MLCC and SLC and capacitor adjusting method - Google Patents
Multilayer ceramic binary capacitor based on MLCC and SLC and capacitor adjusting method Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G5/00—Capacitors in which the capacitance is varied by mechanical means, e.g. by turning a shaft; Processes of their manufacture
- H01G5/04—Capacitors in which the capacitance is varied by mechanical means, e.g. by turning a shaft; Processes of their manufacture using variation of effective area of electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G5/00—Capacitors in which the capacitance is varied by mechanical means, e.g. by turning a shaft; Processes of their manufacture
- H01G5/01—Details
- H01G5/011—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G5/00—Capacitors in which the capacitance is varied by mechanical means, e.g. by turning a shaft; Processes of their manufacture
- H01G5/01—Details
- H01G5/013—Dielectrics
- H01G5/0134—Solid dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G5/00—Capacitors in which the capacitance is varied by mechanical means, e.g. by turning a shaft; Processes of their manufacture
- H01G5/16—Capacitors in which the capacitance is varied by mechanical means, e.g. by turning a shaft; Processes of their manufacture using variation of distance between electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G5/00—Capacitors in which the capacitance is varied by mechanical means, e.g. by turning a shaft; Processes of their manufacture
- H01G5/38—Multiple capacitors, e.g. ganged
Abstract
A multilayer ceramic binary capacitor based on MLCC and SLC and a capacitance adjusting method belong to the field of binary capacitor design. The invention aims to solve the problems that the prior MLCC has single and non-adjustable capacitance value, small capacitance value of the prior binary capacitor, few types of capacitor combinations, difficult capacitance value adjustment and lower withstand voltage. The multilayer ceramic binary capacitor is laminated according to the surface raw porcelain belt, the capacitor part and the surface raw porcelain belt, wherein the capacitor part is formed by overlapping a dielectric layer printed with a plurality of electrodes and a dielectric layer printed with a grounding flat plate from top to bottom; the electrodes of the multilayer ceramic binary capacitor are arranged in a column corresponding to the upper and lower positions to form one or more electrode groups. The capacitance adjusting method comprises the following steps: the single-layer electrode area, the spacing between the electrodes and the adjacent grounding flat plates and the electrode layer number in different electrode groups are different, and the capacitance is changed by changing the connection of different electrode groups. The invention is used for multilayer ceramic binary capacitance and capacitance adjustment.
Description
Technical Field
The invention belongs to the field of binary capacitor design.
Background
The multilayer ceramic capacitor (Multi-layer Ceramic Capacitors, abbreviated as MLCC) is a multilayer laminated structure, which is a parallel body formed by combining a plurality of simple parallel plate capacitors, and is also called monolithic capacitor because ceramic dielectric films with printed electrodes (inner electrodes) are laminated in a staggered manner, ceramic chips are formed by one-time high-temperature sintering, and metal layers (outer electrodes) are sealed at two ends of the chips. The structure comprises three components: ceramic dielectric (ceramic body), metal inner electrode, metal end electrode.
The Single-layer capacitors (SLC) have the advantages of small size, thin thickness, low equivalent series resistance, low loss and the like, are applicable to frequencies of 100MHz-100GHz, and have wide application prospects in high-frequency, microwave, small-sized and miniaturized occasions. The single-layer ceramic capacitor is widely applied to microwave communication circuits, microwave power amplifiers, modules (Bluetooth modules, integrated circuit external elements, hybrid integrated circuit modules, mobile phone circuit modules and radio microwave communication modules), oscillating circuits, timing delay circuits, coupling circuits, balance filter circuits, high-frequency noise suppression circuits, radio frequency bypasses and microwave integrated circuits, and is a military and civil high-reliability product.
Single-layer ceramic capacitors are classified by surface electrode pattern structure, and there are several common types: (1) general type: the capacitor of the type has small main volume, large capacitance and excellent microwave performance; the weldability is good; for the single-layer capacitor with the edge reserved on the surface, the short circuit caused by glue overflow is prevented, the damage caused by tweezers is reduced, and the operation of an automatic machine is facilitated. The method is mainly applied to microwave integrated circuits and has the functions of direct current isolation, source bypass, impedance matching and the like. (2) a two-electrode chip capacitor: the capacitor of the type has unique structure and good performance consistency; can be surface-mounted, avoids the gold wire bonding process, is beneficial to mass production and improves the production efficiency. (3) array-type chip capacitors: this type of capacitor is simple to install, can be integrated in an IC package to reduce lead length, improve performance, and can reduce the cost of the capacitor as well as the cost of installation. The capacitor is mainly used for a monolithic microwave integrated circuit, a decoupling circuit and a radio frequency bypass. (4) binary multi-electrode chip capacitor: the capacitor of this type has small geometry and is suitable for microwave circuits; the layout capacitance of the capacitor array shows certain regular change, is convenient for accurate debugging and is beneficial to circuit matching and adjustment. The circuit is mainly applied to a matching network and provides convenient circuit adjustability. The structure of which is shown in figure 1.
The conventional binary multi-electrode chip has a single-layer ceramic structure, and has smaller size and more capacitance combination modes than single-electrode, double-electrode and array chips, but due to the limitation of the single-layer structure and the volume, the binary multi-electrode chip has small capacitance, few capacitance combination types, difficult capacitance adjustment, lower working voltage and easy breakdown under certain high-power conditions, and is difficult to meet certain fields requiring high density, miniaturization and high frequency and low loss.
Disclosure of Invention
The invention aims to solve the problems of single and non-adjustable capacitance value, small capacitance value, few capacitance combination types, difficult capacitance value adjustment and low withstand voltage of the existing MLCC, and further provides a multilayer ceramic binary capacitor based on the MLCC and the SLC and a capacitance adjustment method.
Multilayer ceramic binary capacitor based on MLCC and SLC, multilayer ceramic binary capacitor carries on lamination according to the way of surface layer raw porcelain belt-capacitor part-surface layer raw porcelain belt, the said capacitor part is formed by overlapping according to the dielectric layer printed with multiple electrodes and dielectric layer printed with grounded flat plate from top to bottom, the number of layers of dielectric layer printed with multiple electrodes in the said capacitor part is 2-80;
in the thickness direction of the multilayer ceramic binary capacitor, a column of electrodes corresponding to the upper and lower positions form one or more electrode groups, the area of each layer of electrodes in the same electrode group, the distance between the electrodes and the adjacent grounding flat plate are the same, and one or more of the area of a single layer of electrodes, the distance between the electrodes and the adjacent grounding flat plate and the number of electrode layers in different electrode groups are different.
A capacitance adjusting method of a multilayer ceramic binary capacitor based on MLCC and SLC is carried out according to the following steps:
in the multilayer ceramic binary capacitor based on the MLCC and the SLC, the capacitance value is changed by changing the access of different electrode groups due to the difference of one or more of the area of a single-layer electrode, the spacing between an electrode and an adjacent grounding plate and the electrode layer number in different electrode groups.
The beneficial effects of the invention are as follows:
1. the invention provides a brand new binary capacitor, which combines the characteristics of an MLCC and a single-layer binary multi-electrode chip capacitor, so that a single-layer electrode can reach a larger capacitance value under the condition of the same area, the comprehensive electrical property of the binary capacitor is improved, the device volume is reduced, and the binary capacitor is suitable for the fields with various high-precision and high-performance requirements.
2. The binary capacitor provided by the invention has more capacitor combinations. Compared with the existing single-layer binary multi-electrode chip capacitor, the capacitor can be adjusted by connecting electrode groups with different single-layer electrode areas, different electrode and adjacent grounding plate distances and different electrode layers by connecting electrode groups with different single-layer electrode areas, and the capacitor can be mutually combined in various modes to jointly adjust the capacitance, has various combination types and can meet the use requirements under different conditions.
3. The structure provided by the invention can be processed and manufactured in various processing modes, and comprises the following steps: LTCC, HTCC, PCB, etc., can be flexibly combined according to the use requirements, equipment conditions and cost factors, and can realize mass production and reduce the use cost.
4. The structure provided by the invention has the advantages of large capacity, multiple capacitance combination modes and convenience in adjustment, and is particularly suitable for the high-precision field of rapid adjustment of multiple frequency points such as frequency hopping communication.
5. The structure provided by the invention has the advantages of multilayer superposition, higher pressure resistance and better reliability.
Drawings
FIG. 1 is a schematic structural diagram of a conventional single-layer binary multi-electrode chip capacitor, wherein 1 is a surface electrode, 2 is a dielectric layer, and 3 is a ground plate;
FIG. 2 is a schematic structural diagram of a multilayer ceramic binary capacitor based on MLCC and SLC and a test substrate according to an embodiment, 1 is a multilayer ceramic binary capacitor based on MLCC and SLC, and 2 is a test substrate;
FIG. 3 is a schematic diagram of the overall structure of a multilayer ceramic binary capacitor based on MLCC and SLC according to the embodiment, wherein 1, 2, 3, 4 and 5 are electrode groups, and 6 is a ground plate;
FIG. 4 is a side view of a multilayer ceramic binary capacitor based on MLCC and SLC according to an embodiment, wherein 1 and 2 are electrode groups, 6 is a ground plate, and 7 is a dielectric layer;
fig. 5 is a schematic structural diagram of a tenth embodiment, in which electrode groups with different electrode areas are connected to change capacitance values, and 1 and 2 are electrode groups;
fig. 6 is a schematic structural diagram of a tenth embodiment, in which electrode groups with different electrode layers are connected to change capacitance values, and fig. 4 and 5 are electrode groups;
fig. 7 is a schematic structural diagram of a tenth embodiment, in which the capacitance value is changed by accessing an electrode group having a different pitch from an adjacent ground plate, and 3, 4, and 5 are electrode groups;
FIG. 8 is a schematic diagram of a multilayer ceramic binary capacitor and test substrate based on MLCC and SLC according to an embodiment;
fig. 9 is a schematic diagram of the overall structure of a multilayer ceramic binary capacitor based on MLCCs and SLCs according to an embodiment, and 1, 2, 3 and 4 are electrode groups.
Detailed Description
The first embodiment is as follows: referring to fig. 2 to 4, in the multilayer ceramic binary capacitor based on MLCCs and SLC in this embodiment, the multilayer ceramic binary capacitor is laminated according to a surface layer raw porcelain tape-capacitor portion-surface layer raw porcelain tape mode, the capacitor portion is formed by overlapping a dielectric layer printed with a plurality of electrodes and a dielectric layer printed with a ground plane from top to bottom, and the number of layers of the dielectric layer printed with a plurality of electrodes in the capacitor portion is 2 to 80;
in the thickness direction of the multilayer ceramic binary capacitor, a column of electrodes corresponding to the upper and lower positions form one or more electrode groups, the area of each layer of electrodes in the same electrode group, the distance between the electrodes and the adjacent grounding flat plate are the same, and one or more of the area of a single layer of electrodes, the distance between the electrodes and the adjacent grounding flat plate and the number of electrode layers in different electrode groups are different.
The specific implementation mode has the advantages of large capacitance value, multiple capacitance combination modes, simple and convenient capacitance value adjustment and capability of being combined with various manufacturing processes.
The structures 1, 2, 3, 4 and 5 in fig. 3 have the functions of forming a plurality of plate capacitors in parallel connection through a laminated structure, fully improving the capacitance value when the electrode area is fixed, and realizing the binary capacitance function by any combination of the plate capacitors; the structure 6 is grounded, so that each layer of metal flat plate can form a flat plate capacitor, and the capacitance is improved.
The beneficial effects of this embodiment are:
1. the embodiment provides a brand new binary capacitor, and by combining the characteristics of the MLCC and the single-layer binary multi-electrode chip capacitor, the single-layer electrode can reach a larger capacitance value under the condition of the same area, the comprehensive electrical property of the binary capacitor is improved, the device volume is reduced, and the binary capacitor is suitable for the fields with various high-precision and high-performance requirements.
2. The binary capacitor proposed in this embodiment has more capacitor combinations. Compared with the existing single-layer binary multi-electrode chip capacitor, the capacitor can be adjusted by connecting electrode groups with different single-layer electrode areas, different electrode and adjacent grounding plate distances and different electrode layers by connecting electrode groups with different single-layer electrode areas, and the capacitor can be mutually combined in various modes to jointly adjust the capacitance, has various combination types and can meet the use requirements under different conditions.
3. The structure proposed in this embodiment may be manufactured by a plurality of processing methods, including: LTCC, HTCC, PCB, etc., can be flexibly combined according to the use requirements, equipment conditions and cost factors, and can realize mass production and reduce the use cost.
4. The structure provided by the embodiment has large capacity, multiple capacitance combination modes and convenient adjustment, and is particularly suitable for the high-precision field of rapid adjustment of multi-frequency points such as frequency hopping communication.
5. The structure provided by the embodiment has the advantages of multilayer superposition, higher pressure resistance and better reliability.
The second embodiment is as follows: the first difference between this embodiment and the specific embodiment is that: the surface raw porcelain belt and the dielectric layer are made of ceramic dielectric materials; the dielectric constant of the ceramic dielectric material is 2-20000. The other is the same as in the first embodiment.
And a third specific embodiment: this embodiment differs from one or both of the embodiments in that: the upper surface area of the multilayer ceramic binary capacitor based on the MLCC and the SLC is 100 mu m 2 ～100cm 2 . The other is the same as the first or second embodiment.
The specific embodiment IV is as follows: this embodiment differs from one of the first to third embodiments in that: the layout mode of the electrodes in the dielectric layer printed with the plurality of electrodes is the same as that of the single-layer binary multi-electrode chip capacitor. The other embodiments are the same as those of the first to third embodiments.
Fifth embodiment: this embodiment differs from one to four embodiments in that: the dielectric layer is provided with a through hole, and the diameter of the through hole is 10-500 mu m; the electrode group is connected by filling holes with conductive metal slurry. The other embodiments are the same as those of the first to fifth embodiments.
Specific embodiment six: this embodiment differs from one of the first to fifth embodiments in that: one or more dielectric layers printed with a grounding plate are arranged between the adjacent dielectric layers printed with a plurality of electrodes. The other embodiments are the same as those of the first to fifth embodiments.
Seventh embodiment: this embodiment differs from one of the first to sixth embodiments in that: the distance between the electrode and the adjacent grounding plate is 10-3000 μm; the thickness of the electrode is 1-1000 mu m; the thickness of the grounding plate is 1-1000 mu m. The other embodiments are the same as those of the first to sixth embodiments.
Eighth embodiment: this embodiment differs from one of the first to seventh embodiments in that: multilayer ceramic binary capacitors based on MLCC and SLC are obtained by LTCC, HTCC or PCB processing methods. The other is the same as in embodiments one to seven.
The embodiment adopts LTCC/HTCC technology, can compress the volume to be very small, and the single-layer binary volume required to be used is far larger than the capacitor in the embodiment in order to achieve the same capacitance and capacitance combination quantity.
LTCC processing method comprises the following steps: ceramic dielectric materials with dielectric constants in the range of 2-20000 are selected, the sintering temperature of the ceramic materials is lower than 900 ℃, and the expansion coefficient is close to that of the used metal materials. Because of the low sintering temperature, silver and copper metals with high conductivity and low melting point can be selected as the metal materials. The processing process is that firstly, ceramic powder casting and slide glass are carried out to prepare a raw ceramic tape; punching holes on the green ceramic tape, filling the holes and printing electrodes; and finally, laminating, hydrostatic pressing and sintering the printed capacitor part and the unprinted surface raw porcelain tape together to prepare the multilayer ceramic binary capacitor.
HTCC processing method: HTCC must be subjected to glue removal treatment at a temperature below 900 ℃ and then sintered into a whole in a high-temperature environment of 1500-1600 ℃ with multiple laminated substrates, and the ceramic material is Al 2 O 3 AlN, etc. Because of the high sintering temperature, only metals such as tungsten, molybdenum, manganese and the like or noble metals with relatively high melting points but relatively poor electrical conductivity can be selected. The production process flow is similar to that of LTCC.
The PCB processing method comprises the following steps: the substrate material adopts a copper clad laminate, and the metal-based heat dissipation plate comprises an aluminum substrate, a copper substrate and an iron substrate. The number of the PCB layers is 1-64, the minimum plate thickness can reach 0.6mm, and the processing flow comprises cutting, grinding, film pasting, exposure, development, etching/electroplating, film stripping, browning, lamination, drilling, copper-clad plate plating, outer dry film plating, outer pattern plating, solder resist, silk screen character printing, surface treatment, molding, electrical measurement and final inspection.
Detailed description nine: the embodiment mode is a capacitance adjusting method of a multilayer ceramic binary capacitor based on MLCC and SLC, which comprises the following steps:
in the multilayer ceramic binary capacitor based on the MLCC and the SLC, the capacitance value is changed by changing the access of different electrode groups due to the difference of one or more of the area of a single-layer electrode, the spacing between an electrode and an adjacent grounding plate and the electrode layer number in different electrode groups.
Detailed description ten: the present embodiment differs from the ninth embodiment in the following description with reference to fig. 5 to 7: when the intervals between electrodes in different electrode groups and adjacent grounding plates are the same as the electrode layer number in the multilayer ceramic binary capacitor based on the MLCC and the SLC, and the single-layer electrode areas in different electrode groups are different, the capacitance value is changed by changing the access of different electrode groups;
when the single-layer electrode areas and the electrode layer numbers in different electrode groups are the same in the multilayer ceramic binary capacitor based on the MLCC and the SLC, and the distances between the electrodes in different electrode groups and the adjacent grounding flat plates are different, the capacitance value is changed by changing the access of different electrode groups and controlling the distances between the electrodes and the adjacent grounding flat plates;
when the single-layer electrode area and the electrode spacing between the adjacent grounding flat plates in different electrode groups are the same and the electrode layer number in different electrode groups is different in the multilayer ceramic binary capacitor based on the MLCC and the SLC, the capacitance value is changed by changing the access of different electrode groups and controlling the electrode layer number. The other is the same as in the ninth embodiment.
The electrodes can not be independently selected for access in different layers, but the capacitance value of the capacitor can be quickly adjusted by controlling the access condition of the electrodes, and the capacitance value can be accurately controlled according to the requirement. The specific implementation mode is as follows:
(1) The capacitance is changed by changing the area of the single-layer electrode in the access electrode group. In different electrode groups, under the condition that the distance between the electrode and the adjacent grounding flat plate (the distance between the electrode and the grounding flat plate, namely the thickness of the green ceramic tape) and the electrode layer number are the same, the capacitance value of the whole binary capacitor can be changed by connecting the electrode groups with different single-layer electrode areas, and the capacitance value is similar to that of the traditional single-layer binary capacitor. The schematic diagram is shown in fig. 5, fig. 5 is a schematic diagram of a structure in which the capacitance value is changed by connecting electrode groups with different electrode areas according to the embodiment, and 1 and 2 are electrode groups; the electrode layers of the electrode groups 1 and 2 and the distance between the electrodes and the adjacent grounding plate are identical, but the single-layer electrode areas in the electrode groups 1 and 2 are different (top view), so that the capacitance values of the electrode groups 1 and 2 are different, and the capacitance value of the whole capacitor can be changed when the electrode group 1 or 2 is selected.
(2) The capacitance value is changed by controlling the number of electrode layers. In different electrode groups, under the condition that the distance between the electrodes and the adjacent grounding flat plates is the same as the area of a single-layer electrode, one column of electrodes are arranged into two or more groups of electrode groups with different electrode layers in the thickness direction of the dielectric layer, and the size of the capacitance value of the binary capacitor can be controlled by selecting the electrode groups with different electrode layers. As shown in fig. 6, fig. 6 is a schematic structural diagram of an embodiment in which electrode groups with different electrode layers are connected to change capacitance values, and fig. 4 and 5 are electrode groups; the electrode is divided into 2 electrode groups with different electrode layers, so that the electrode layer number is changed under the condition that the distance between the electrode and an adjacent grounding plate is the same as the area of a single-layer electrode; as can be seen, the same electrode set is connected by filling holes with conductive paste, while no conductive paste is provided between the different electrode sets 4 and 5.
(3) The capacitance is changed by controlling the spacing between the electrode and the adjacent ground plate. In different electrode groups, under the condition that the area of a single-layer electrode and the number of electrode layers are the same, the capacitance value of the binary capacitor can be adjusted by adjusting the distance between the electrode and the adjacent grounding plate, as shown in fig. 7, fig. 7 is a schematic diagram of a structure in which the capacitance value is changed by accessing the electrode group with different distances between the electrode and the adjacent grounding plate in the specific embodiment, and 3, 4 and 5 are electrode groups; the electrode group 3 and the electrode group 4 have the same electrode area and the electrode layer number, but the electrode in the electrode group 3 and the electrode group 4 have different distances from the adjacent grounding flat plates, and 2 dielectric layers printed with the grounding flat plates are arranged between the dielectric layers printed with the electrodes in the electrode group 3.
The three methods for adjusting the capacitance value of the capacitor can be used independently or can be mutually combined, and the combination types are very various, so that different use requirements can be met.
The following examples are used to verify the benefits of the present invention:
embodiment one, specifically described with reference to fig. 8 and 9:
the multilayer ceramic binary capacitor is laminated according to a surface raw porcelain belt-capacitor part-surface raw porcelain belt mode, the capacitor part is formed by overlapping medium layers printed with 3 electrodes and medium layers printed with a grounding flat plate from top to bottom, and the number of layers of the medium layers printed with 3 electrodes in the capacitor part is 6; the number of the dielectric layers printed with the grounding plate in the capacitor part is 6;
in the thickness direction of the multilayer ceramic binary capacitor, a row of electrodes corresponding to the upper and lower positions form an electrode group 1, a row of electrodes form an electrode group 2, a row of electrodes form electrode groups 3 and 4, the electrode areas and the distances between electrodes and adjacent grounding plates in the same electrode group are the same, and relevant parameters of the electrode group 1, the electrode group 2 and the electrode groups 3 and 4 are shown in Table 1 in detail.
The surface raw porcelain belt and the dielectric layer are made of K14 ceramic materials.
The dielectric constant of the ceramic dielectric material is 13.5.
The size of the multilayer ceramic binary capacitor based on the MLCC and the SLC is 4mm multiplied by 1.44mm.
The layout mode of the electrodes in the dielectric layer printed with 3 electrodes is the same as that of the DCMS100J40 type single-layer binary multi-electrode chip capacitor.
The dielectric layer is provided with a through hole, and the diameter of the through hole is 100 mu m; the electrode group is connected by filling holes with silver paste.
The thickness of the electrode is 20 mu m; the thickness of the grounding plate is 20 mu m;
the electrode is made of silver metal; the grounding plate is made of silver metal.
The multilayer ceramic binary capacitor based on the MLCC and the SLC is obtained by an LTCC processing method, and the specific process is as follows:
1. casting: casting the K14 ceramic powder to obtain a raw ceramic membrane tape, and winding the raw ceramic membrane tape for standby;
2. slide glass: cutting the raw ceramic membrane strip from a roll shape to a single piece shape according to the size requirement to obtain a cut raw ceramic strip;
3. punching, hole filling and printing: punching holes at corresponding positions on the green ceramic tape after cutting, filling holes with silver paste on a screen printer and printing electrodes to obtain a dielectric layer printed with 3 electrodes, or filling holes with silver paste on the screen printer and printing a grounding flat plate to obtain a dielectric layer printed with the grounding flat plate;
4. lamination: the cut green porcelain tape is used as a surface green porcelain tape, and a dielectric layer printed with 3 electrodes, a dielectric layer printed with a grounding flat plate and the surface green porcelain tape are aligned, fixed and laminated to obtain a laminated green porcelain tape;
5. static pressure: packaging and evacuating the laminated raw porcelain belts, fixing the raw porcelain belts in a reinforced plastic bag, and then putting the reinforced plastic bag in hot water for pressure equalizing to obtain the raw porcelain belts after static pressure;
6. cutting and co-firing: cutting the green ceramic tape after static pressure into different modules according to design requirements, and placing the modules in a sintering furnace for sintering to finally obtain the multilayer ceramic binary capacitor based on the MLCC and the SLC.
Capacitance measurement and adjustment scheme analysis: the DCMS100J40 single-layer binary multi-electrode chip capacitor of the same material, same electrode area, same electrode and ground plane pitch was customized to set up as group 1, example one as group 2, and test comparison results are shown in the following table:
as can be seen from the data in the table, under the condition of the same single-layer electrode flat area, the embodiment has larger capacitance value, more capacitance combination modes, wider capacitance adjustment range and better pressure resistance than the traditional single-layer binary multi-electrode chip capacitor, has better comprehensive performance and can be suitable for certain fields requiring high density, miniaturization and high frequency and low loss.
Claims (9)
1. The multilayer ceramic binary capacitor based on the MLCC and the SLC is characterized in that the multilayer ceramic binary capacitor is laminated according to a surface layer raw porcelain tape-capacitor part-surface layer raw porcelain tape mode, the capacitor part is formed by overlapping a dielectric layer printed with a plurality of electrodes and a dielectric layer printed with a grounding flat plate from top to bottom, and the number of layers of the dielectric layer printed with the plurality of electrodes in the capacitor part is 2-80;
in the thickness direction of the multilayer ceramic binary capacitor, a column of electrodes corresponding to the upper and lower positions form one or more electrode groups, the area of each layer of electrode in the same electrode group, the distance between the electrode and an adjacent grounding plate are the same, and one or more of the area of a single layer of electrode, the distance between the electrode and the adjacent grounding plate and the number of electrode layers in different electrode groups are different;
the layout mode of the electrodes in the dielectric layer printed with the plurality of electrodes is the same as that of the single-layer binary multi-electrode chip capacitor.
2. The multilayer ceramic binary capacitor based on MLCC and SLC according to claim 1, wherein said surface green ceramic tape and dielectric layer are made of ceramic dielectric material; the dielectric constant of the ceramic dielectric material is 2-20000.
3. The multilayer ceramic binary capacitor based on MLCC and SLC according to claim 1, wherein the multilayer ceramic binary capacitor based on MLCC and SLC has an upper surface area of 100 μm 2 ~100cm 2 。
4. The multilayer ceramic binary capacitor based on the MLCC and the SLC, which is disclosed in claim 1, is characterized in that through holes are formed in the dielectric layers of the dielectric layers printed with a plurality of electrodes and the dielectric layers printed with the grounding plate, and the diameter of the through holes is 10 mu m-500 mu m; the electrode group is connected by filling holes with conductive metal slurry.
5. The multilayer ceramic binary capacitor based on the MLCC and the SLC according to claim 1, wherein one or more dielectric layers printed with a grounding plate are arranged between the adjacent dielectric layers printed with a plurality of electrodes.
6. The multilayer ceramic binary capacitor based on the MLCC and the SLC, which is characterized in that the distance between the electrode and the adjacent grounding plate is 10 mu m-3000 mu m; the thickness of the electrode is 1 mu m-1000 mu m; the thickness of the grounding plate is 1-1000 mu m.
7. The multilayer ceramic binary capacitor based on the MLCC and the SLC according to claim 1, wherein the multilayer ceramic binary capacitor based on the MLCC and the SLC is obtained by an LTCC, HTCC or PCB processing method.
8. The method for adjusting the capacitance of the multilayer ceramic binary capacitor based on the MLCC and the SLC as defined in claim 1, wherein the method is carried out by the following steps:
in the multilayer ceramic binary capacitor based on the MLCC and the SLC, the capacitance value is changed by changing the access of different electrode groups due to the difference of one or more of the area of a single-layer electrode, the spacing between an electrode and an adjacent grounding plate and the electrode layer number in different electrode groups.
9. The capacitance adjusting method of the multilayer ceramic binary capacitor based on the MLCC and the SLC according to claim 8, wherein when the spacing between electrodes in different electrode groups and adjacent grounding plates and the electrode layer number are the same and the single-layer electrode area in different electrode groups is different in the multilayer ceramic binary capacitor based on the MLCC and the SLC, the capacitance value is changed by changing the access of different electrode groups;
when the single-layer electrode areas and the electrode layer numbers in different electrode groups are the same in the multilayer ceramic binary capacitor based on the MLCC and the SLC, and the distances between the electrodes in different electrode groups and the adjacent grounding flat plates are different, the capacitance value is changed by changing the access of different electrode groups and controlling the distances between the electrodes and the adjacent grounding flat plates;
when the single-layer electrode area and the electrode spacing between the adjacent grounding flat plates in different electrode groups are the same and the electrode layer number in different electrode groups is different in the multilayer ceramic binary capacitor based on the MLCC and the SLC, the capacitance value is changed by changing the access of different electrode groups and controlling the electrode layer number.
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