JPH104029A - Thin film capacitor and method for manufacturing the same - Google Patents
Thin film capacitor and method for manufacturing the sameInfo
- Publication number
- JPH104029A JPH104029A JP15552696A JP15552696A JPH104029A JP H104029 A JPH104029 A JP H104029A JP 15552696 A JP15552696 A JP 15552696A JP 15552696 A JP15552696 A JP 15552696A JP H104029 A JPH104029 A JP H104029A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- thin film
- substrate
- film capacitor
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、表面実装部品であ
る薄膜チップ部品のうち薄膜コンデンサ、及びその製造
方法に属する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film capacitor among thin film chip components which are surface mount components, and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】従来の薄膜コンデンサの製造方法は、ま
ず図３（ａ）に示すように、薄膜チップとして、半導体
基板５１の表面に金属層（アルミニウム膜）５２、５３
によって誘電体膜５５を挟み込む。その後、図３（ｂ）
に示すように、半導体基板５１の両側端へ電極５６、５
７を引き出す。電極５６、５７の形成手段は、図３
（ｃ）に示すように、金属層５２、５３、誘電体膜５５
及び半導体基板５１を個々の素子に切断して分割した
後、キャリアに整列してディップ方式で導電性材料を塗
布、焼き付けするという方法が採用されている。2. Description of the Related Art In a conventional method of manufacturing a thin film capacitor, first, as shown in FIG. 3A, a metal layer (aluminum film) 52, 53 is formed on a surface of a semiconductor substrate 51 as a thin film chip.
The dielectric film 55 is interposed therebetween. After that, FIG.
As shown in FIG.
Pull out 7. The means for forming the electrodes 56 and 57 is shown in FIG.
As shown in (c), the metal layers 52 and 53, the dielectric film 55
In addition, a method of cutting and dividing the semiconductor substrate 51 into individual elements, aligning them with carriers, and applying and baking a conductive material in a dip method is adopted.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、従来の
薄膜コンデンサの方法では、個片化した後に各素子の両
側に導電材料を塗布、焼き付けしなければならず、この
作業は素子サイズが小さくなる程、作業性が悪くなると
いう問題がある。However, in the conventional thin film capacitor method, a conductive material must be applied and baked on both sides of each element after singulation. This operation is performed as the element size becomes smaller. However, there is a problem that workability deteriorates.
【０００４】それ故に本発明の課題は、作業性、生産性
の極めて良好な薄膜コンデンサ、及びその製造方法を提
供することにある。It is therefore an object of the present invention to provide a thin film capacitor having extremely good workability and productivity, and a method for manufacturing the same.
【０００５】[0005]
【課題を解決するための手段】本発明によれば、低抵抗
基板の表面に第１の溝を形成する工程と、該第１の溝に
絶縁性樹脂で埋込んで平坦化する工程と、前記表面に誘
電体膜を形成する工程と、前記第１の溝の内側に前記第
１の溝よりも幅寸法及び深さ寸法が小さい第２の溝を形
成する工程と、該第２の溝と前記基板の表裏面で位置が
整合するよう前記基板の裏面に前記第２の溝と略同形状
の第３の溝を形成する工程と、前記基板の両面に金属膜
を形成する工程と、さらに前記第２及び第３の溝で切断
する工程とを含むことを特徴とする薄膜コンデンサの製
造方法が得られる。According to the present invention, a step of forming a first groove in a surface of a low-resistance substrate, a step of embedding the first groove with an insulating resin, and a step of flattening the first groove; A step of forming a dielectric film on the surface, a step of forming a second groove having a smaller width and depth than the first groove inside the first groove, and a step of forming the second groove Forming a third groove having substantially the same shape as the second groove on the back surface of the substrate so that the position is aligned on the front and back surfaces of the substrate; and forming metal films on both surfaces of the substrate. And a step of cutting with the second and third grooves.
【０００６】また、本発明によれば、低抵抗基板の表裏
面で位置が整合するよう溝を形成する工程と、前記表裏
面に誘電体膜を形成する工程と、該誘電体膜上に金属膜
を形成する工程と、前記溝の中央部で切断する工程とを
含むことを特徴とする薄膜コンデンサの製造方法が得ら
れる。Further, according to the present invention, there is provided a step of forming a groove so that a position is aligned on the front and back surfaces of a low-resistance substrate, a step of forming a dielectric film on the front and back surfaces, and a step of forming a metal film on the dielectric film. A method for manufacturing a thin film capacitor is provided, which includes a step of forming a film and a step of cutting at the center of the groove.
【０００７】[0007]
【作用】薄膜コンデンサは、低抵抗基板の表面に選択エ
ッチング又はダイヤモンド刃による第１の溝を形成した
後、第１の溝を絶縁性樹脂で埋込んで平坦化し、スパッ
タリング法又は回転塗布法により誘電体膜を形成し、引
き続き第１の溝の内側に、第１の溝よりも幅及び深さが
小さい第２の溝を形成し、第２の溝と表裏で位置が整合
するように基板の裏面に第２の溝とほぼ同形状の第３の
溝を形成した後、基板の両面にアルミニウム、ニッケル
等の金属膜を形成し、さらに第２及び第３の溝の中央部
をダイシング切断することによって得られる。In the thin film capacitor, after a first groove is formed by selective etching or a diamond blade on the surface of a low-resistance substrate, the first groove is buried with an insulating resin to be flattened, and the thin film capacitor is formed by a sputtering method or a spin coating method. A dielectric film is formed, and a second groove having a smaller width and depth than the first groove is formed inside the first groove, and the substrate is aligned with the second groove on both sides. After a third groove having substantially the same shape as the second groove is formed on the back surface of the substrate, a metal film of aluminum, nickel, or the like is formed on both surfaces of the substrate, and the central portions of the second and third grooves are cut by dicing. It is obtained by doing.
【０００８】また、薄膜コンデンサは、低抵抗半導体基
板の表裏面で位置が整合するようにダイシングソー等に
よりＶ形状の溝を形成した後、熱酸化スパッター又は回
転塗布法等によりＳｉＯ2 等の誘電体膜を形成し、引き
続きアルミニウム、ニッケル等の金属膜を形成した後、
溝の中央部に沿ってダイシング切断することを特徴とす
る金属膜を形成することによって得られる。In the thin film capacitor, a V-shaped groove is formed by a dicing saw or the like so that the positions are aligned on the front and back surfaces of the low-resistance semiconductor substrate, and then a dielectric such as SiO 2 is formed by thermal oxidation sputtering or spin coating. After forming a body film and subsequently forming a metal film such as aluminum and nickel,
It is obtained by forming a metal film characterized by performing dicing cutting along the center of the groove.
【０００９】[0009]
【発明の実施の形態】以下、図面を参照して、本発明の
薄膜コンデンサ及びその製造方法の実施の形態例を説明
する。図１（ａ）〜図１（ｇ）は本発明の薄膜コンデン
サの製造方法の第１の実施の形態例を示している。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a thin film capacitor according to an embodiment of the present invention; 1A to 1G show a first embodiment of a method for manufacturing a thin film capacitor according to the present invention.
【００１０】本発明の薄膜コンデンサの製造方法では、
まず、図１（ａ）に示すように、低抵抗半導体基板（Ｓ
ｉ基板）１の表面に選択エッチング又はダイヤモンド刃
による第１の溝２を形成する。図１（ａ）に示す実施の
形態例では、比抵抗 ０．０２Ωｃｍ以下で、厚さ寸法
１．０ｍｍの低抵抗半導体基板１の表面に通常のフォ
トリソグラフィー手法によって深さ寸法１５０μ、幅寸
法１００ｍμの第１の溝２を形成した。第１の溝２はＨ
Ｆ：ＨＮＯ3 ＝２：４のシリコン用エッチャントで処理
した。In the method for manufacturing a thin film capacitor according to the present invention,
First, as shown in FIG. 1A, a low-resistance semiconductor substrate (S
A first groove 2 is formed on the surface of an i-substrate 1 by selective etching or a diamond blade. In the embodiment shown in FIG. 1A, a depth of 150 μm and a width of 100 mμ are formed on the surface of a low-resistance semiconductor substrate 1 having a specific resistance of 0.02 Ωcm or less and a thickness of 1.0 mm by ordinary photolithography. The first groove 2 was formed. The first groove 2 is H
F: treated with a silicon etchant of HNO 3 = 2: 4.
【００１１】その後、図１（ｂ）に示すように、第１の
溝２の中に絶縁性樹脂３として、例えば、ポリイミドを
埋め込んで平坦化する。After that, as shown in FIG. 1B, the first groove 2 is buried with, for example, polyimide as an insulating resin 3 to be flattened.
【００１２】第１の溝２を絶縁性樹脂３で埋込んで平坦
化した状態で、図１（ｃ）に示すように、基板１の表面
にスパッタリング法又は回転塗布法により誘電体膜４を
形成する。この実施の形態例では、表面にスパッター法
によって誘電体膜４としてＳｉ０2 を３０００オングス
トローム形成した。In a state where the first groove 2 is buried in the insulating resin 3 and flattened, as shown in FIG. 1C, a dielectric film 4 is formed on the surface of the substrate 1 by sputtering or spin coating. Form. In this embodiment, 3,000 angstroms of SiO 2 was formed as a dielectric film 4 on the surface by sputtering.
【００１３】引き続き、図１（ｄ）に示すように、第１
の溝２の内側には、第１の溝２よりも幅寸法及び深さ寸
法が小さい第２の溝６を形成する。例えば、第１の溝２
には深さ寸法１００μｍ、幅寸法５０ｍμの第２の溝６
をダイサーを用いて形成する。また、第２の溝６と表裏
で位置が整合するように基板の裏面に第２の溝６とほぼ
同形状の第３の溝７を形成する。この実施の形態例で
は、ダイサーの送り寸法で表裏を合わせた。Subsequently, as shown in FIG.
A second groove 6 having a smaller width and depth than the first groove 2 is formed inside the groove 2. For example, the first groove 2
Has a second groove 6 having a depth of 100 μm and a width of 50 μm.
Is formed using a dicer. In addition, a third groove 7 having substantially the same shape as the second groove 6 is formed on the back surface of the substrate so that the position of the second groove 6 is aligned with the front and back surfaces. In this embodiment, the front and back are matched by the feed size of the dicer.
【００１４】図１（ｅ）は、図１（ｄ）の状態のウエハ
ーの表裏面にＡｌ（アルミニウム膜）８、Ｎｉ（ニッケ
ル膜）９を２層連続でスパッター形成した状態を示して
いる。下地のアルミニウム膜８は３．０μｍ，ニッケル
膜９は２．５μｍの膜厚とした。FIG. 1 (e) shows a state in which two layers of Al (aluminum film) 8 and Ni (nickel film) 9 are continuously formed on the front and back surfaces of the wafer in the state of FIG. 1 (d) by sputtering. The underlying aluminum film 8 had a thickness of 3.0 μm, and the nickel film 9 had a thickness of 2.5 μm.
【００１５】図１（ｆ）は、図１（ｅ）に示した矢印方
向で示す第２及び第３の溝６、７の中央でダイサーによ
ってダイシング切断して完全切断した状態を示してい
る。このように、切断して完成した薄膜コンデンサは、
図１（ｇ）にも示すように、薄膜コンデンサの機構部が
あるＡ面（基板１の表面に相当）と対向電極Ｂ面（基板
１の裏面に相当）とは素子の両側の端子部に位置してい
る。FIG. 1F shows a state in which the dicing is performed by a dicer at the center of the second and third grooves 6, 7 shown in the direction of the arrow shown in FIG. In this way, the thin film capacitor cut and completed is
As shown in FIG. 1 (g), the surface A (corresponding to the front surface of the substrate 1) where the mechanism of the thin film capacitor is located and the surface B of the counter electrode (corresponding to the back surface of the substrate 1) positioned.
【００１６】次に、薄膜コンデンサの製造方法の第２の
実施例を説明する。Next, a second embodiment of the method for manufacturing a thin film capacitor will be described.
【００１７】第２の実施例における薄膜コンデンサの製
造方法は、まず、図２（ａ）に示すように、低抵抗半導
体基板２１の表裏面で位置が整合するようにダイシング
ソー等により角度付けされたＶ形状の第１及び第２の溝
２２、２３を形成する。第１の実施例と同様に、表裏面
の第１及び第２の溝２２、２３の位置は整合されてい
る。また、第１及び第２の溝２２、２３の角度は任意に
選ばれるが、この実施の形態例では、θ＝９０度で、深
さ寸法２００μｍで実施した。なお、図２（ａ）に示し
た第１及び第２の溝２２、２３の角度は、θ＝９０度よ
りも大きい角度の例を示している。In the method of manufacturing a thin film capacitor according to the second embodiment, first, as shown in FIG. 2A, an angle is set by a dicing saw or the like so that the positions are aligned on the front and back surfaces of the low-resistance semiconductor substrate 21. V-shaped first and second grooves 22 and 23 are formed. As in the first embodiment, the positions of the first and second grooves 22 and 23 on the front and back surfaces are aligned. Further, the angles of the first and second grooves 22 and 23 are arbitrarily selected. In this embodiment, the angle θ is 90 degrees and the depth is 200 μm. Note that the angle of the first and second grooves 22 and 23 shown in FIG. 2A is an example where the angle is larger than θ = 90 degrees.
【００１８】図２（ａ）の状態から図２（ｂ）に示すよ
うに、基板２１の表面に熱酸化スパッター又は回転塗布
法等によりＳｉＯ2 等の誘電体膜２４を形成する。この
実施例では、ウエハーを１１００℃×５分の熱酸化（ス
チーム）を実施し、２０００オングストロームの膜厚の
誘電体膜２４を得た。As shown in FIG. 2B from the state of FIG. 2A, a dielectric film 24 of SiO 2 or the like is formed on the surface of the substrate 21 by thermal oxidation sputtering or spin coating. In this example, the wafer was subjected to thermal oxidation (steam) at 1100 ° C. × 5 minutes to obtain a dielectric film 24 having a thickness of 2000 Å.
【００１９】引き続き、図２（ｃ）に示すように、ウエ
ハーの表裏面にＡｌ（アルミニウム膜）２５、Ｎｉ（ニ
ッケル膜）２６等の金属膜を連続的にスパッターにて形
成する。Subsequently, as shown in FIG. 2C, metal films such as Al (aluminum film) 25 and Ni (nickel film) 26 are continuously formed on the front and back surfaces of the wafer by sputtering.
【００２０】図２（ｄ）は、図２（ｃ）で矢印で示した
第１及び第２の溝２２、２３の中央部に沿ってダイシン
グ切断した状態を示している。切断して完成した薄膜コ
ンデンサでは、薄膜コンデンサの機構部があるＡ面（基
板２１の表面に相当）と対向電極Ｂ面（基板２１の裏面
に相当）とが素子の両側の端子部に位置している。最初
の第１及び第２の溝２２、２３が基板２１上で平面図的
にＸ軸、Ｙ軸共にＶ形状で形成すれば、図２（ｅ）に示
すようになるが、Ｘ軸のみ、Ｙ軸のみをＶ形状とした場
合は、完成品は図２（ｆ）のようになる。FIG. 2D shows a state in which dicing is cut along the center of the first and second grooves 22 and 23 indicated by arrows in FIG. 2C. In the thin film capacitor cut and completed, the surface A (corresponding to the front surface of the substrate 21) on which the mechanism of the thin film capacitor is located and the surface B of the counter electrode (corresponding to the back surface of the substrate 21) are located at terminal portions on both sides of the element. ing. If the first first and second grooves 22 and 23 are formed on the substrate 21 in plan view in a V shape for both the X axis and the Y axis, the result is as shown in FIG. When only the Y axis has a V shape, the finished product is as shown in FIG.
【００２１】即ち、第１及び第２の実施の形態例で説明
した薄膜コンデンサは、表裏面とも誘電体膜４、２４を
保持するコンデンサ構造であって、低抵抗半導体基板の
両面にコンデンサを保持した直列接続型である。また、
低抵抗半導体基板は、導体であってもよい。That is, the thin film capacitor described in the first and second embodiments has a capacitor structure that holds the dielectric films 4 and 24 on both the front and back surfaces, and holds the capacitor on both surfaces of the low-resistance semiconductor substrate. Series connection type. Also,
The low-resistance semiconductor substrate may be a conductor.
【００２２】さらに、薄膜コンデンサは、導体又は低抵
抗半導体によって誘電体膜４、２４が挟まれてなるコン
デンサ層が部品の側面に形成されている。Further, in the thin film capacitor, a capacitor layer in which the dielectric films 4, 24 are sandwiched by a conductor or a low-resistance semiconductor is formed on the side surface of the component.
【００２３】[0023]
【発明の効果】以上、実施の形態例によって説明したよ
うに、本発明の薄膜コンデンサ及びその製造方法による
と、ウエハー状態で電極形成まで完了でき、切断で個片
化した解きには素子が完成しているという極めて安定で
生産性の高い製造方法が得られる。As described above, according to the embodiment, according to the thin film capacitor of the present invention and the method of manufacturing the same, it is possible to complete the formation of the electrodes in the wafer state, and to complete the element by cutting into pieces by cutting. An extremely stable and highly productive manufacturing method can be obtained.
【００２４】また、従来の薄膜コンデンサが機能部を素
子の上面に位置付けて電極端子を側面両端に位置付けて
いるのに対し、本願では、機能部を片法の電極端子が兼
ねる形でなっているため、素子の上面には何等の機能膜
もなく、捺印にさいしても極めて自由度が高いという効
果を奏する。Further, in the conventional thin film capacitor, the functional portion is positioned on the upper surface of the element and the electrode terminals are positioned on both sides, whereas in the present application, the functional portion is also used as a single-sided electrode terminal. Therefore, there is no functional film on the upper surface of the element, and there is an effect that the degree of freedom is extremely high even when stamping is performed.
【００２５】また、個片化してからのプロセスがほとん
どないため、極めて生産性が高く安定した供給が可能な
のである。[0025] Further, since there is almost no process after singulation, extremely high productivity and stable supply are possible.
【００２６】なお、実施の形態例では片面機能膜の例の
みを述べたが、当然基板の両面に機能膜を位置付けるキ
ャパシタンスの直列接続構造も可能である。しかも機能
膜と電極とを兼ねるて素子の側面に形成する構成は、な
んら薄い膜コンデンサのみに適用することに限られるも
のではなくたの薄い膜部品への展開は可能である。Although only one-sided functional film has been described in the embodiment, a series connection structure of capacitance in which the functional films are positioned on both surfaces of the substrate is of course also possible. In addition, the configuration in which the functional film and the electrode are formed on the side surface of the element as well as the electrode is not limited to being applied to only a thin film capacitor, but can be applied to a thin film component.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明の薄膜コンデンサの製造方法の第１の実
施例を示し、（ａ）〜（ｆ）は製造工程を示した断面
図、（ｇ）は（ｆ）の斜視図である。FIG. 1 shows a first embodiment of a method of manufacturing a thin film capacitor according to the present invention, in which (a) to (f) are cross-sectional views showing manufacturing steps, and (g) is a perspective view of (f).
【図２】本発明の薄膜コンデンサの製造方法の第２の実
施例を示し、（ａ）〜（ｄ）は製造工程を示した断面
図、（ｅ）は（ｄ）の斜視図、（ｆ）は（ｄ）の変形例
を示す斜視図である。FIG. 2 shows a second embodiment of a method for manufacturing a thin film capacitor according to the present invention, wherein (a) to (d) are cross-sectional views showing manufacturing steps, (e) is a perspective view of (d), and (f). () Is a perspective view showing a modification of (d).
【図３】従来の薄膜コンデンサの製造方法の第１の実施
例を示し、（ａ）及び（ｂ）は製造工程を示した断面
図、（ｃ）は（ｂ）を切断した状態の斜視図である。FIGS. 3A and 3B show a first embodiment of a conventional method of manufacturing a thin film capacitor, wherein FIGS. 3A and 3B are cross-sectional views showing manufacturing steps, and FIG. It is.
１、２１ 低抵抗半導体基板 ２，２２ 第１の溝 ３ 絶縁性樹脂 ４ 誘電体膜 ６，２３ 第２の溝 ７ 第３の溝 ８、２５ Ａｌ（アルミニウム膜） ９、２６ Ｎｉ（ニッケル膜） ２４、５５ 誘電体膜 ５１ 半導体基板 ５２、５３ 金属層 ５６，５７ 電極 1, 21 Low resistance semiconductor substrate 2, 22 First groove 3 Insulating resin 4 Dielectric film 6, 23 Second groove 7 Third groove 8, 25 Al (aluminum film) 9, 26 Ni (nickel film) 24, 55 Dielectric film 51 Semiconductor substrate 52, 53 Metal layer 56, 57 Electrode
Claims (5)
工程と、該第１の溝に絶縁性樹脂を埋込んで平坦化する
工程と、前記表面に誘電体膜を形成する工程と、前記第
１の溝の内側に前記第１の溝よりも幅寸法及び深さ寸法
が小さい第２の溝を形成する工程と、該第２の溝と前記
基板の表裏面で位置が整合するよう前記基板の裏面に前
記第２の溝と略同形状の第３の溝を形成する工程と、前
記基板の両面に金属膜を形成する工程と、さらに前記第
２及び第３の溝で切断する工程とを含むことを特徴とす
る薄膜コンデンサの製造方法。1. A step of forming a first groove on a surface of a low-resistance substrate, a step of embedding an insulating resin in the first groove to flatten the same, and a step of forming a dielectric film on the surface. Forming a second groove having a smaller width and a smaller depth than the first groove inside the first groove; and aligning the position of the second groove with the front and back surfaces of the substrate. Forming a third groove having substantially the same shape as the second groove on the back surface of the substrate, forming a metal film on both surfaces of the substrate, and further forming the second and third grooves. Cutting the thin film capacitor.
う溝を形成する工程と、前記表裏面に誘電体膜を形成す
る工程と、該誘電体膜上に金属膜を形成する工程と、前
記溝の中央部で切断する工程とを含むことを特徴とする
薄膜コンデンサの製造方法。2. A step of forming a groove so that positions are aligned on the front and back surfaces of a low-resistance substrate, a step of forming a dielectric film on the front and back surfaces, and a step of forming a metal film on the dielectric film. Cutting at the center of the groove.
製造方法によって製造された薄膜コンデンサにおいて、
前記表裏面ともに誘電体膜を保持するコンデンサ構造で
あって、前記低抵抗基板の両面に前記コンデンサを保持
した直列接続型であることを特徴とする薄膜コンデン
サ。3. A thin film capacitor manufactured by the method for manufacturing a thin film capacitor according to claim 1 or 2,
A thin film capacitor having a capacitor structure that holds a dielectric film on both the front and back surfaces, and is a series connection type in which the capacitor is held on both surfaces of the low-resistance substrate.
製造方法によって製造された薄膜コンデンサにおいて、
前記低抵抗基板が導体であることを特徴とする薄膜コン
デンサ。4. A thin film capacitor manufactured by the method for manufacturing a thin film capacitor according to claim 1 or 2,
The thin-film capacitor, wherein the low-resistance substrate is a conductor.
製造方法によって製造された薄膜コンデンサにおいて、
導体又は低抵抗半導体によって誘電体膜が挟まれてなる
コンデンサ層が部品の側面に形成されていることを特徴
とする薄膜コンデンサ。5. A thin film capacitor manufactured by the method for manufacturing a thin film capacitor according to claim 1 or 2,
A thin-film capacitor comprising a capacitor layer formed by sandwiching a dielectric film between a conductor or a low-resistance semiconductor on a side surface of a component.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15552696A JPH104029A (en) | 1996-06-17 | 1996-06-17 | Thin film capacitor and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15552696A JPH104029A (en) | 1996-06-17 | 1996-06-17 | Thin film capacitor and method for manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH104029A true JPH104029A (en) | 1998-01-06 |
Family
ID=15608003
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15552696A Withdrawn JPH104029A (en) | 1996-06-17 | 1996-06-17 | Thin film capacitor and method for manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH104029A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003077757A (en) * | 2001-09-05 | 2003-03-14 | Soshin Electric Co Ltd | Chip capacitor and method of manufacturing the same |
| KR100568306B1 (en) | 2004-07-23 | 2006-04-05 | 삼성전기주식회사 | Thin film type multi-layered ceramic capacitor and method of producing the same |
-
1996
- 1996-06-17 JP JP15552696A patent/JPH104029A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003077757A (en) * | 2001-09-05 | 2003-03-14 | Soshin Electric Co Ltd | Chip capacitor and method of manufacturing the same |
| KR100568306B1 (en) | 2004-07-23 | 2006-04-05 | 삼성전기주식회사 | Thin film type multi-layered ceramic capacitor and method of producing the same |
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|---|---|---|---|
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