JP2002516027A - 電圧吸収端部を有するpn接合を含むSiC半導体デバイス - Google Patents
電圧吸収端部を有するpn接合を含むSiC半導体デバイスInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 72
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 68
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 64
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 230000009467 reduction Effects 0.000 claims description 7
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 4
- -1 aluminum ions Chemical class 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 4
- 239000010410 layer Substances 0.000 description 219
- 230000005684 electric field Effects 0.000 description 26
- 230000015556 catabolic process Effects 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
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- 230000002441 reversible effect Effects 0.000 description 4
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- 239000000654 additive Substances 0.000 description 2
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- 238000009792 diffusion process Methods 0.000 description 2
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- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 1
- 241001676573 Minium Species 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
Description
Claims (1)
- 【特許請求の範囲】 1. pn接合を含み、前記pn接合の第1導電型(n)層と第2導電型(p )層は共に炭化珪素(SiC)のドープされた層で構成し、前記層の少なくとも 一方の端部に終端(T)を設ける半導体素子であって、前記終端(T)は前記終 端の外側の境界に向かって段階的にまたは連続的に減少する全電荷を持つことを 特徴とする、半導体素子。 2. 前記pn接合は、第2導電型の第1の低ドープ層(3)と、前記第1層 の上にあり前記第1層(3)より小さな領域延長を有する第2導電型の第2の高 ドープ層(4、8)を備えることを特徴とする、請求項1に記載の半導体素子。 3. 前記pn接合は、その周辺でその厚さが段階(d0−d4)でゼロまで減 少する第2導電型の第1の低ドープ層(10)と、前記第1層の上にある第2導 電型の第2高ドープ層(11)を備えることを特徴とする、請求項1に記載の半 導体素子。 4. 前記pn接合は、第2導電型の第1の低ドープ層(12)と前記第1層 の上にある第2導電型の第2高ドープ層(13)を備え、前記第2層(13)の 境界の外側の第1層(12)はその周辺でその厚さが段階(Q0、Q1、Q2、 Q5)でゼロまで減少し、前記第1層(12)の外側および付近で第2導電型で 少なくとも1つの注入されて第1層を取り囲むゾーン(Q3、Q4、Q6、Q7 )を有し、これにより第1層(12)と注入ゾーン(Q3、Q4、Q6、Q7) は終端(T)を構成することを特徴とする、請求項1に記載の半導体素子。 5. 前記pn接合の前記第2導電型層は、外向きに段階的にまたは連続的に ドーピング濃度が減少して終端(T)を形成する第2導電型端部の横方向に形成 された層(17)で囲まれた、第1の高ドープ層(16)を含むことを特徴とす る、請求項1に記載の半導体素子。 6. 前記横方向に成長した端部層(17)とSiC素子の残部の間にAlN 層を設けることを特徴とする、請求項5に記載の半導体素子。 7. 前記接合部の第1導電型の低ドープ層(2)と第2導電型の層の間に追 加のドープ層(21)を設け、追加の層(21)は第1導電型(n--)であって 第1導電型の低ドープ(n-)層(2)より低いトーピング濃度を有することを 特徴とする、前記請求項のいずれかに記載の半導体素子。 8. pn接合を含み、前記pn接合のp導電層とn導電層は共に炭化珪素( SiC)のドープ層で構成し、前記層の少なくとも一方の端部に終端(T)を設 ける半導体素子の製造方法であって、第1の導電型のドープ層(2)を含む炭化 珪素ウェーハ(S)の上に第2導電型の少なくとも2つのドープ層(3、4)、 (3、8)を互いの上に配置し、各新しい第2導電型の層のドープ濃度は順に高 く形成し、第2導電型の層の領域は順に小さくなるように形成し、端部(5)に 向かって減少する全電荷または単位面積当たりの電荷密度が減少する第2導電型 の各層の終端(T)を形成することを特徴とする、半導体素子の製造方法。 9. 第2導電型の層(3、4)を互いの上にエピタキシャル成長させること を特徴とする、請求項8に記載の半導体素子の製造方法。 10. 第2導電型の層(3、4)をマスキングにより段階的にエッチし、順 次の層の領域を順に小さくすることを特徴とする、請求項9に記載の半導体素子 の製造方法。 11. 第2導電型の層(3、8)を少なくとも1つの第1エピタキシャル成 長層(3)の上にイオンを注入することにより形成し、これにより下の層(3) より高ドーピング濃度を有する第2層(8)を形成することを特徴とする、請求 項8に記載の半導体素子の製造方法。 12. 注入層(8)の下にある第2導電型のエピタキシャル成長層(3)を マスキングにより段階的にエッチし、第2導電型の順次の層(3、8)の面積を 順に小さくすることを特徴とする、請求項9に記載の半導体素子の製造方法。 13. pn接合を含み、前記pn接合のp導電層とn導電層は共に炭化珪素 (SiC)のドープ層で構成し、前記層の少なくとも一方の端部に終端(T)を 設ける半導体素子の製造方法であって、第1の導電型のドープ層(2)を含む炭 化珪素ウェーハ(S)の上に第2導電型の少なくとも第1の低ドープ層(10) をエピタキシャル成長させ、この第1層(10)の上に前記第2導電型の第2の 高ドープ層(10)をエピタキシャル成長させ、次にマスキングと段階的なエッ チングにより第2層(11)の外の境界の外側に前記第1層(10)を前記第1 層(10)の周辺に向かって段階的に減らした厚さ(d0−d4)で形成し、端部 (5)に向かって減少する全電荷を有する第2導電型の層の終端(T)を形成す ることを特徴とする、半導体素子の製造方法。 14. 前記第2導電型の4段階の第1層(10)の段階の相対的厚さはd0 :d1:d2:d3:d4=100:60:45−50:30−35:20であり、 前記第2導電型の2段階の第1層(10)の段階の相対的厚さはd0:d1:d2 =100:60:30−35であり、前記第2導電型の1段階の第1層(10) の段階の相対的厚さはd0:d1=100:50−60であることを特徴とする、 請求項13に記載の半導体素子の製造方法。 15. pn接合を含み、前記pn接合のp導電層とn導電層は共に炭化珪素 (SiC)のドープ層を構成し、前記層の少なくとも一方の端部に終端(T)を 設ける半導体素子の製造方法であって、第1の導電型のドープ層(2)を含む炭 化珪素ウェーハ(S)の上に第2導電型の少なくとも第1の低ドープ層(12) をエピタキシャル成長させ、この第1層(12)の上に前記第2導電型の第2の 高ドープ層(13)をエピタキシャル成長させ、次にマスキングと段階的なエッ チングにより第2層(13)の外の境界の外側に前記第1層(12)を前記第1 層(12)の周辺に向かって段階的に減らした厚さ(Q0、Q1、Q2、Q5)で形 成し、また前記第2導電型の前記第1層(12)の境界の外側で隣接して端部( 5)に向かって減少する全電荷を有する第1層を囲む少なくとも1つのゾーン( Q3、Q4、Q6、Q7)をウェーハ(S)上で前記第2導電型のイオンを注入し、 端部(5)に向かって減少する全電荷を有する第2導電型の層の終端(T)を形 成することを特徴とする、半導体素子の製造方法。 16. 第2導電型の層(10、Q3、Q4)を含む終端(T)において4段 階で減少する電荷の間の関係はQ0:Q1:Q2:Q3:Q4=100:60:45 −50:30−35:20であることを特徴とする、請求項15に記載の半導体 素子の製造方法。 17. 前記注入はホウ素またはアルミニウムのイオンを用いて行うことを特 徴とする、請求項15に記載の半導体素子の製造方法。 18. pn接合を含み、前記pn接合のp導電層とn導電層は共に炭化珪素 (SiC)のドープ層を構成し、前記層の少なくとも一方の端部に終端(T)を 設ける半導体素子の製造方法であって、第1の導電型のドープ層(2)を含む炭 化珪素ウェーハ(S)の上に第2の導電型の一方の高ドープ層(16)をエピタ キシャル成長させ、次に前記第1層(16)と前記第1導電型の前記ドープ層( 2)をエッチすることにより接合部端部をメサ構造に形成し、次にドーピング濃 度を外側に向かって段階的にまたは連続的に減少させて端部層(17)を前記接 合部の端部に横方向に成長させ、これにより端部(5)に向かって減少する全電 荷を有する第2導電型の層の終端(T)を形成することを特徴とする、半導体素 子の製造方法。 19. 前記端部層(17)は中間エッチバック操作により成長させることを 特徴とする、請求項18に記載の半導体素子の製造方法。 20. 前記終端(T)のドーピング濃度の減少は、前記端部層(17)のエ ピタキシャル成長中にドーピングガスのドーズ量を連続的にまたは段階的に減少 させることにより行うことを特徴とする、請求項18に記載の半導体素子の製造 方法。 21. AlNの層(18)を前記メサ構造の上に(エピタキシャル的に)形 成した後、前記AlN層(18)の上に端部層(17)を成長させることを特徴 とする、請求項18、19、20のいずれかに記載の半導体素子の製造方法。 22. pn接合を含み、前記pn接合のp導電層とn導電層は共に炭化珪素 (SiC)のドープ層を構成し、前記層の少なくとも一方の端部に終端(T)を 設ける半導体素子の製造方法であって、第1の導電型のドープ層(2)を含む炭 化珪素ウェーハ(S)の上に第2の導電型の少なくとも1つの低ドープ層(12 )をエピタキシャル成長させ、この第1層(12)の上に前記第2導電型の第2 の高ドープ層(13)をエピタキシャル成長させ、次にマスキングと段階的なエ ッチングにより、第2層(13)の外の境界の外側に前記第1層(12)の周辺 に向かって段階的に厚さを減少させて前記第1層(12)を形成し、前記段階の 外側に最低の全電荷を持つ材料の少なくとも1つのゾーンを縦方向のエピタキシ ャル成長により作り、端部(5)に向かって減少する全電荷を有する第2導電型 の層の終端(T)を形成することを特徴とする、半導体素子の製造方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US520,689 | 1995-08-30 | ||
US08/520,689 US5967795A (en) | 1995-08-30 | 1995-08-30 | SiC semiconductor device comprising a pn junction with a voltage absorbing edge |
PCT/SE1996/001073 WO1997008754A2 (en) | 1995-08-30 | 1996-08-30 | SiC SEMICONDUCTOR DEVICE COMPRISING A PN JUNCTION WITH A VOLTAGE ABSORBING EDGE |
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JP2002516027A true JP2002516027A (ja) | 2002-05-28 |
JP4350798B2 JP4350798B2 (ja) | 2009-10-21 |
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JP51019497A Expired - Lifetime JP4350798B2 (ja) | 1995-08-30 | 1996-08-30 | 電圧吸収端部を有するpn接合を含むSiC半導体デバイス |
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US (2) | US5967795A (ja) |
EP (1) | EP0847598B1 (ja) |
JP (1) | JP4350798B2 (ja) |
DE (1) | DE69631664T2 (ja) |
WO (1) | WO1997008754A2 (ja) |
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JP2017183428A (ja) * | 2016-03-29 | 2017-10-05 | 豊田合成株式会社 | 半導体装置およびその製造方法 |
Also Published As
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WO1997008754A3 (en) | 1997-10-30 |
US5967795A (en) | 1999-10-19 |
WO1997008754A2 (en) | 1997-03-06 |
US5977605A (en) | 1999-11-02 |
DE69631664T2 (de) | 2004-12-23 |
EP0847598B1 (en) | 2004-02-25 |
JP4350798B2 (ja) | 2009-10-21 |
EP0847598A2 (en) | 1998-06-17 |
DE69631664D1 (de) | 2004-04-01 |
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