JP2002353362A - Land formation method in substrate for use in mounting flip-chip and the substrate for the same - Google Patents
Land formation method in substrate for use in mounting flip-chip and the substrate for the sameInfo
- Publication number
- JP2002353362A JP2002353362A JP2001158147A JP2001158147A JP2002353362A JP 2002353362 A JP2002353362 A JP 2002353362A JP 2001158147 A JP2001158147 A JP 2001158147A JP 2001158147 A JP2001158147 A JP 2001158147A JP 2002353362 A JP2002353362 A JP 2002353362A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- land
- semiconductor element
- flip
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、フリップチップ実
装用基板のランド形成方法及びフリップチップ実装用基
板に関する。The present invention relates to a method for forming a land on a flip-chip mounting substrate and a flip-chip mounting substrate.
【０００２】[0002]
【従来の技術】一般に、フリップチップ実装において
は、半導体素子上に電極端子を形成し、これをフェイス
ダウンで配線基板導体と接続する。配線基板上、つまり
フリップチップ実装用の基板には半導体素子の電極端子
に対応してランドが設けられており、これらを突き合わ
せた状態で熱圧着あるいは加熱溶着により基板上に半導
体素子を実装していた。2. Description of the Related Art Generally, in flip-chip mounting, an electrode terminal is formed on a semiconductor element, and this is connected face-down to a wiring board conductor. Lands are provided on the wiring substrate, that is, on the flip-chip mounting substrate, in correspondence with the electrode terminals of the semiconductor element, and the semiconductor element is mounted on the substrate by thermocompression bonding or heat welding in a state where these are abutted. Was.
【０００３】図５は、従来例を説明するための図であ
る。この図において、１はフリップチップ実装用基板
（以下、単に基板と称す）、２は基板１上に設けられた
ランド、３は半導体素子、４は半導体素子３上に形成さ
れた電極端子、５は熱硬化性樹脂である。FIG. 5 is a diagram for explaining a conventional example. In this drawing, 1 is a flip-chip mounting substrate (hereinafter simply referred to as a substrate), 2 is a land provided on the substrate 1, 3 is a semiconductor element, 4 is an electrode terminal formed on the semiconductor element 3, 5 Is a thermosetting resin.
【０００４】基板１への半導体素子３の実装は次のよう
に行われる。 １）半導体素子３上に金属突起物の電極端子４を形成す
る。 ２）基板１の半導体素子実装面に熱硬化性樹脂５を供給
する。 ３）基板１の平坦なランド２に対して、半導体素子３の
電極端子４を位置合わせする。 ４）半導体素子３を基板１に対して、熱硬化性樹脂５に
より圧接実装（加熱、加圧）して固定する。The mounting of the semiconductor element 3 on the substrate 1 is performed as follows. 1) An electrode terminal 4 of a metal protrusion is formed on a semiconductor element 3. 2) Supply the thermosetting resin 5 to the semiconductor element mounting surface of the substrate 1. 3) Align the electrode terminals 4 of the semiconductor element 3 with the flat lands 2 of the substrate 1. 4) The semiconductor element 3 is fixed to the substrate 1 by press-fitting (heating and pressing) with a thermosetting resin 5.
【０００５】[0005]
【発明が解決しようとする課題】ところで、上述した従
来のフリップチップ実装用基板にあっては、次のような
問題がある。すなわち、基板１の平坦なランド２上に半
導体素子３を圧接実装する際、ランド２に半導体素子３
の電極端子４を正確に搭載し、加熱、加圧しながら接合
させるようにしているが、ランド２が平坦な形状である
ことから、圧接実装装置（図示略）の精度が十分でない
場合には、図６に示すように、半導体素子３の電極端子
４がランド２から滑り落ちて位置ずれを起こすことがあ
る。そして、このようなことが起こると歩留まりが低下
し、製品コストの削減が困難になる。なお、この問題
は、精度が十分にとれる圧接実装装置を使用することで
回避できるが、精度の高い装置はそれだけ高価になる。However, the above-mentioned conventional flip-chip mounting substrate has the following problems. That is, when the semiconductor element 3 is pressure-welded on the flat land 2 of the substrate 1, the semiconductor element 3
Although the electrode terminals 4 are accurately mounted and joined while heating and pressurizing, since the land 2 has a flat shape, if the accuracy of the pressure welding mounting device (not shown) is not sufficient, As shown in FIG. 6, the electrode terminals 4 of the semiconductor element 3 may slide off the lands 2 and cause a positional shift. When such a situation occurs, the yield decreases, and it becomes difficult to reduce the product cost. Although this problem can be avoided by using a pressure contact mounting device having sufficient accuracy, a device with high accuracy becomes more expensive.
【０００６】本発明は係る点に鑑みてなされたもので、
精度が十分でない安価な圧接実装装置でも、確実に基板
のランド上に半導体素子を圧接実装できるフリップチッ
プ実装用基板におけるランド形成方法及びフリップチッ
プ実装用基板を提供することを目的とする。[0006] The present invention has been made in view of the above points,
An object of the present invention is to provide a method for forming a land on a flip-chip mounting substrate and a flip-chip mounting substrate that can reliably press-mount a semiconductor element on a land of a substrate even with an inexpensive pressure-contact mounting device that does not have sufficient accuracy.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
の本発明に係る請求項１記載のフリップチップ実装用基
板のランド形成方法は、基板に、開口端の径を圧接実装
しようとする半導体素子の電極端子のトップ径より大き
く且つ前記半導体素子の底面と前記基板上の配線パター
ンとが接触しない深さの凹部を形成する凹部形成工程
と、前記凹部を形成した側の基板上に金属箔をプレス
し、前記凹部に金属箔を追従させてランドを形成するラ
ンド形成工程と、を具備することを特徴とする。According to a first aspect of the present invention, there is provided a method for forming a land on a flip-chip mounting substrate according to the present invention. Forming a recess having a depth larger than the top diameter of the electrode terminal of the element and a depth not allowing the bottom surface of the semiconductor element to contact the wiring pattern on the substrate; and forming a metal foil on the substrate on the side where the recess is formed. And a land forming step of forming a land by pressing a metal foil to the concave portion.
【０００８】また、本発明に係る請求項２記載のフリッ
プチップ実装用基板のランド形成方法は、請求項１記載
のフリップチップ実装用基板のランド形成方法におい
て、前記凹部の形状を円錐状としたことを特徴とする。According to a second aspect of the present invention, there is provided a method for forming a land on a flip-chip mounting substrate according to the first aspect, wherein the concave portion has a conical shape. It is characterized by the following.
【０００９】また、本発明に係る請求項３記載のフリッ
プチップ実装用基板のランド形成方法は、請求項１又は
請求項２のいずれかに記載のフリップチップ実装用基板
のランド形成方法において、前記凹部の深さを１０μｍ
以上１５μｍ以下としたことを特徴とする。According to a third aspect of the present invention, there is provided a method for forming a land on a flip-chip mounting substrate according to the first or second aspect. 10 μm depth of recess
It is characterized by being not less than 15 μm.
【００１０】本発明に係る請求項４記載のフリップチッ
プ実装用基板は、基板上の回路パターンに半導体素子を
取り付けるためのランドに、開口端の径を圧接実装しよ
うとする半導体素子の電極端子のトップ径より大きく且
つ深さを１０μｍ以上１５μｍ以下とした円錐状凹部を
設けたことを特徴とする。According to a fourth aspect of the present invention, there is provided a flip-chip mounting substrate, wherein a diameter of an opening end of an electrode terminal of a semiconductor element to be pressure-welded is mounted on a land for mounting the semiconductor element on a circuit pattern on the substrate. A conical concave portion having a depth larger than the top diameter and having a depth of 10 μm or more and 15 μm or less is provided.
【００１１】本発明においては、基板上の回路パターン
に半導体素子を取り付けるためのランドに、開口端の径
を圧接実装しようとする半導体素子の電極端子のトップ
径より大きく且つ半導体素子の底面と基板上の配線パタ
ーンとが接触しない深さの凹部を設けるようにしたの
で、半導体チップを実装する際の電極端子とランドの位
置ずれを抑制さでき、両者間の位置決めを正確且つ容易
に行えるようになる。この場合、凹部の形状深さとして
は１０μｍ以上１５μｍ以下が好適であり、また形状と
しては円錐状が好適である。In the present invention, the diameter of the opening end is larger than the top diameter of the electrode terminal of the semiconductor element to be pressed and mounted on the land for attaching the semiconductor element to the circuit pattern on the substrate, and the bottom of the semiconductor element is connected to the substrate. Since a concave portion having a depth that does not make contact with the upper wiring pattern is provided, displacement of the electrode terminal and the land when mounting the semiconductor chip can be suppressed, and positioning between the two can be performed accurately and easily. Become. In this case, the shape depth of the concave portion is preferably 10 μm or more and 15 μm or less, and the conical shape is preferable.
【００１２】したがって、精度が十分でない安価な圧接
実装装置でも、確実に基板のランド上に半導体素子を圧
接実装することができる。Therefore, even with an inexpensive pressure-contact mounting apparatus with insufficient accuracy, it is possible to reliably press-mount a semiconductor element on a land of a substrate.
【００１３】[0013]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を用いて説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１４】図１は、本発明の実施の形態に係るフリッ
プチップ実装用基板を示す図である。なお、この図にお
いて前述した図５と共通する部分には同一の符号を付け
ている。図１において、１は基板（フリップチップ実装
用基板）、３は半導体素子、４は半導体素子３上に形成
された電極端子、５は熱硬化性樹脂、６は基板１上に設
けられたランドである。FIG. 1 is a view showing a flip-chip mounting substrate according to an embodiment of the present invention. In this figure, the same parts as those in FIG. 5 described above are denoted by the same reference numerals. In FIG. 1, 1 is a substrate (flip chip mounting substrate), 3 is a semiconductor element, 4 is an electrode terminal formed on the semiconductor element 3, 5 is a thermosetting resin, and 6 is a land provided on the substrate 1. It is.
【００１５】ランド６の上面には、開口端の径を圧接実
装しようとする半導体素子３の電極端子４のトップ径よ
りも大きく且つ深さを１０μｍから１５μｍ以下とした
円錐状の凹部６Ａが形成されている。なお、この円錐状
凹部６Ａの形成には、例えばレーザ等を利用した穴開け
装置が用いられる。この穴開け装置を用いて穴を形成す
ることで、基板工程での余計な工程を増やさなくて済
む。On the upper surface of the land 6, a conical concave portion 6A having an opening end diameter larger than the top diameter of the electrode terminal 4 of the semiconductor element 3 to be mounted by pressure and having a depth of 10 μm to 15 μm or less is formed. Have been. In order to form the conical recess 6A, for example, a punching device using a laser or the like is used. By forming a hole using this punching device, it is not necessary to increase an extra step in the substrate process.
【００１６】ここで、円錐状凹部６Ａの深さを１０μｍ
から１５μｍ以下にした理由は、深さを１５μｍ以上に
すると、半導体素子３の本体の底面と基板１の表面との
間の距離が短くなって、基板１上の配線パターンが半導
体素子３の底面に接触してしまう虞があるからである。
このようなことが起こらないように、深さを１０μｍか
ら１５μｍ以下に限定している。Here, the depth of the conical recess 6A is 10 μm.
The reason is that when the depth is set to 15 μm or more, the distance between the bottom surface of the main body of the semiconductor element 3 and the surface of the substrate 1 becomes short, and the wiring pattern on the substrate 1 becomes This is because there is a risk of contact with the device.
To prevent this from happening, the depth is limited to 10 μm to 15 μm or less.
【００１７】また、円錐状凹部６Ａの開口端の径を半導
体素子３の電極端子４のトップ径よりも大きくしたの
は、次のような理由からである。 半導体素子３上に金属突起物の電極端子４を形成する
際の装置の位置精度、半導体素子３の電極端子４を基
板１のランド２に搭載するときの位置精度、基板１に
レーザ等の穴開け装置で凹みを形成する際の位置精度が
あることから、これらの点における位置精度を考慮する
と、円錐状凹部６Ａの開口端の径を半導体素子３の電極
端子４のトップ径より大きくすることで、正確な位置決
めが可能になる。The reason why the diameter of the opening end of the conical concave portion 6A is larger than the top diameter of the electrode terminal 4 of the semiconductor element 3 is as follows. Position accuracy of the device when forming the electrode terminals 4 of the metal protrusions on the semiconductor element 3, position accuracy when mounting the electrode terminals 4 of the semiconductor element 3 on the lands 2 of the substrate 1, holes in the substrate 1 such as lasers Since there is a positional accuracy when forming the dent with the opening device, considering the positional accuracy at these points, the diameter of the opening end of the conical concave portion 6A should be larger than the top diameter of the electrode terminal 4 of the semiconductor element 3. Thus, accurate positioning becomes possible.
【００１８】次に、ランド６の形成工程について図３を
参照して説明する。 １）まず、基板１に（又は基材とその上に形成した絶縁
層とからなる基板）にレーザを利用した穴開け装置（図
示略）を用いて、図２の斜視図に示すような、円錐状で
且つ１０μｍ〜１５μｍの深さの凹部１Ａを形成する。
このとき、凹部１Ａの開口端の径を、圧接実装しようと
する半導体素子３の電極端子４のトップ径より大きくす
る。Next, a process of forming the land 6 will be described with reference to FIG. 1) First, as shown in a perspective view of FIG. 2, using a punching device (not shown) using a laser on the substrate 1 (or a substrate comprising a base material and an insulating layer formed thereon), A concave portion 1A having a conical shape and a depth of 10 μm to 15 μm is formed.
At this time, the diameter of the opening end of the concave portion 1A is made larger than the top diameter of the electrode terminal 4 of the semiconductor element 3 to be pressed and mounted.
【００１９】２）基板１に凹部１Ａを形成した後、それ
を形成した側の基板１の上面に金属箔７をプレスする。 ３）基板１に金属箔７をプレスした後、配線を形成す
る。これにより、基板１の凹部１Ａに金属箔が追従して
円錐状のランド６が形成される。以上により、ランド６
が完成する。2) After forming the concave portion 1A in the substrate 1, a metal foil 7 is pressed on the upper surface of the substrate 1 on which the concave portion 1A is formed. 3) After the metal foil 7 is pressed on the substrate 1, wiring is formed. Thus, the conical land 6 is formed by the metal foil following the concave portion 1A of the substrate 1. Thus, land 6
Is completed.
【００２０】次に、半導体素子３の基板１への実装工程
について図４を参照して説明する。 １）半導体素子３上に先端に丸みを付けた金属突起物の
電極端子４を形成する。 ２）次いで、基板１上の半導体素子３を実装する部分に
熱硬化性樹脂５を供給する。Next, a process of mounting the semiconductor element 3 on the substrate 1 will be described with reference to FIG. 1) An electrode terminal 4 of a metal protrusion having a rounded tip is formed on a semiconductor element 3. 2) Next, the thermosetting resin 5 is supplied to a portion on the substrate 1 where the semiconductor element 3 is to be mounted.
【００２１】３）次いで、熱硬化性樹脂５を供給した基
板１のランド６に半導体素子３の電極端子４が接続する
ように位置合わせして搭載する。そして、ランド６に半
導体素子３の電極端子４を搭載した後、圧接実装（加
熱、加圧）する。この際、基板１のランド６が円錐状に
凹んでいることで、半導体素子３の電極端子４が滑り落
ちることがなくそのランド６の凹みに嵌まり込むので、
安定した接合ができる。この状態から熱圧着等の手段に
より両者を接合して基板１と半導体素子３を電気的に接
続する。 ４）以上により、基板１のランド６への半導体素子実装
が完成する。3) Next, the semiconductor device 3 is mounted on the land 6 of the substrate 1 to which the thermosetting resin 5 has been supplied so that the electrode terminal 4 is connected to the land 6. Then, after mounting the electrode terminals 4 of the semiconductor element 3 on the lands 6, they are pressure-welded (heated and pressed). At this time, since the land 6 of the substrate 1 is concavely conical, the electrode terminal 4 of the semiconductor element 3 does not slide down and fits into the concave of the land 6.
Stable joining is possible. From this state, the substrate 1 and the semiconductor element 3 are electrically connected by joining them by means such as thermocompression bonding. 4) As described above, the mounting of the semiconductor element on the land 6 of the substrate 1 is completed.
【００２２】このように、本実施の形態によれば、基板
１上の回路パターンに半導体素子３を取り付けるための
ランド６に、開口端の径を半導体素子３の電極端子４の
トップ径よりも大きく且つ深さを１０μｍから１５μｍ
以下とした円錐状凹部６Ａを形成して、半導体素子３の
電極端子４の接合時のずれを防止するようにしたので、
正確で安定した位置決めが可能となり、精度が十分でな
い安価な圧接実装装置でも確実にランド６上に半導体素
子３を圧接実装することができる。これにより、歩留ま
りが向上し、信頼性の向上が図れ、さらには製品のコス
トダウンも図れる。As described above, according to the present embodiment, the diameter of the opening end of the land 6 for attaching the semiconductor element 3 to the circuit pattern on the substrate 1 is larger than the top diameter of the electrode terminal 4 of the semiconductor element 3. Large and 10 to 15 μm deep
The following conical recess 6A is formed to prevent the electrode terminal 4 of the semiconductor element 3 from shifting at the time of joining.
Accurate and stable positioning is possible, and even an inexpensive pressure-contact mounting apparatus with insufficient accuracy can reliably press-mount the semiconductor element 3 on the land 6. As a result, the yield can be improved, the reliability can be improved, and the cost of the product can be reduced.
【００２３】なお、上記実施の形態では、ランド６上の
円錐状凹部６Ａの形成を、基板１に穴を開けることで行
ったが、基板１上に設けられたランド上にフォトレジス
トをパターニングし、これにエッチング処理を施して形
成する方法もある。In the above embodiment, the conical concave portion 6A on the land 6 is formed by making a hole in the substrate 1. However, a photoresist is patterned on the land provided on the substrate 1. There is also a method of forming the film by performing an etching process.
【００２４】[0024]
【発明の効果】以上説明したように、本発明によれば、
基板上に形成するランドに円錐状凹部を形成して半導体
素子の電極端子の接合時のずれを防止するようにしたの
で、正確で安定した位置決めが可能となり、精度が十分
でない安価な圧接実装装置でも確実にランド上に半導体
素子を圧接実装することができる。これにより、歩留ま
りが向上し、信頼性の向上が図れ、さらには製品のコス
トダウンも図れる。As described above, according to the present invention,
A conical recess is formed in the land formed on the substrate to prevent misalignment of the electrode terminals of the semiconductor element at the time of joining, so that accurate and stable positioning is possible, and an inexpensive pressure contact mounting apparatus with insufficient accuracy. However, the semiconductor element can be securely mounted on the land by pressure welding. As a result, the yield can be improved, the reliability can be improved, and the cost of the product can be reduced.
【図１】本発明の実施の形態に係るフリップチップ実装
用基板を示す図である。FIG. 1 is a view showing a flip-chip mounting substrate according to an embodiment of the present invention.
【図２】図１のフリップチップ実装用基板上に形成され
る凹部を示す斜視図である。FIG. 2 is a perspective view showing a concave portion formed on the flip-chip mounting substrate of FIG. 1;
【図３】図１のフリップチップ実装用基板のランド形成
工程を説明するための図である。FIG. 3 is a view for explaining a land forming step of the flip-chip mounting substrate of FIG. 1;
【図４】図１のフリップチップ実装用基板における半導
体素子の基板への実装工程を説明するための図である。FIG. 4 is a view for explaining a step of mounting a semiconductor element on the substrate in the flip-chip mounting substrate of FIG. 1;
【図５】従来のフリップチップ実装用基板を示す図であ
る。FIG. 5 is a diagram showing a conventional flip-chip mounting substrate.
【図６】従来のフリップチップ実装用基板の問題点を説
明するための図である。FIG. 6 is a view for explaining a problem of a conventional flip-chip mounting substrate.
１…フリップチップ実装用基板、１Ａ…凹部、３…半導
体素子、４…電極端子、５…熱硬化性樹脂、６…ラン
ド、６Ａ…円錐状凹部、７…金属箔DESCRIPTION OF SYMBOLS 1 ... Flip chip mounting board, 1A ... concave part, 3 ... semiconductor element, 4 ... electrode terminal, 5 ... thermosetting resin, 6 ... land, 6A ... conical concave part, 7 ... metal foil
フロントページの続き Ｆターム(参考） 5E317 AA30 CD32 GG16 5E319 AA03 AB06 AC02 AC11 CC12 CD04 GG09 GG15 5F044 KK02 KK17 KK18 KK19 LL00 LL15 RR18 Continued on the front page F term (reference) 5E317 AA30 CD32 GG16 5E319 AA03 AB06 AC02 AC11 CC12 CD04 GG09 GG15 5F044 KK02 KK17 KK18 KK19 LL00 LL15 RR18
Claims (4)
する半導体素子の電極端子のトップ径より大きく且つ前
記半導体素子の底面と前記基板上の配線パターンとが接
触しない深さの凹部を形成する凹部形成工程と、 前記凹部を形成した側の基板上に金属箔をプレスし、前
記凹部に金属箔を追従させてランドを形成するランド形
成工程と、 を具備することを特徴とするフリップチップ実装用基板
のランド形成方法。1. A recess having a diameter of an opening end larger than a top diameter of an electrode terminal of a semiconductor element to be pressure-welded on a substrate and having such a depth that a bottom surface of the semiconductor element does not contact a wiring pattern on the substrate. Forming a recess by pressing a metal foil on the substrate on the side where the recess is formed, and forming a land by causing the metal foil to follow the recess. A land forming method for a chip mounting substrate.
徴とする請求項１記載のフリップチップ実装用基板のラ
ンド形成方法。2. The method according to claim 1, wherein said recess has a conical shape.
以下としたことを特徴とする請求項１又は請求項２記載
のフリップチップ実装用基板のランド形成方法。3. The depth of the recess is not less than 10 μm and not more than 15 μm.
3. The method for forming a land on a flip-chip mounting substrate according to claim 1, wherein:
り付けるためのランドに、開口端の径を圧接実装しよう
とする半導体素子の電極端子のトップ径より大きく且つ
深さを１０μｍ以上１５μｍ以下とした円錐状凹部を設
けたことを特徴とするフリップチップ実装用基板。4. A land for mounting a semiconductor element on a circuit pattern on a substrate, wherein the diameter of the opening end is larger than the top diameter of the electrode terminal of the semiconductor element to be pressed and mounted, and the depth is 10 μm or more and 15 μm or less. A flip-chip mounting substrate having a conical recess.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001158147A JP2002353362A (en) | 2001-05-28 | 2001-05-28 | Land formation method in substrate for use in mounting flip-chip and the substrate for the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001158147A JP2002353362A (en) | 2001-05-28 | 2001-05-28 | Land formation method in substrate for use in mounting flip-chip and the substrate for the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002353362A true JP2002353362A (en) | 2002-12-06 |
Family
ID=19001912
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001158147A Pending JP2002353362A (en) | 2001-05-28 | 2001-05-28 | Land formation method in substrate for use in mounting flip-chip and the substrate for the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002353362A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008021751A (en) * | 2006-07-11 | 2008-01-31 | National Institute Of Advanced Industrial & Technology | Electrode, semiconductor chip, substrate, connecting structure of electrode for semiconductor chip, and semiconductor module and its manufacturing method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10199933A (en) * | 1997-01-09 | 1998-07-31 | Sony Corp | Method of mounting semiconductor device |
| WO2000059033A1 (en) * | 1999-03-25 | 2000-10-05 | Seiko Epson Corporation | Wiring board, connection board, semiconductor device, method of manufacture thereof, circuit board, and electronic device |
-
2001
- 2001-05-28 JP JP2001158147A patent/JP2002353362A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10199933A (en) * | 1997-01-09 | 1998-07-31 | Sony Corp | Method of mounting semiconductor device |
| WO2000059033A1 (en) * | 1999-03-25 | 2000-10-05 | Seiko Epson Corporation | Wiring board, connection board, semiconductor device, method of manufacture thereof, circuit board, and electronic device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008021751A (en) * | 2006-07-11 | 2008-01-31 | National Institute Of Advanced Industrial & Technology | Electrode, semiconductor chip, substrate, connecting structure of electrode for semiconductor chip, and semiconductor module and its manufacturing method |
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