JP2008021751A - Electrode, semiconductor chip, substrate, connecting structure of electrode for semiconductor chip, and semiconductor module and its manufacturing method - Google Patents

Electrode, semiconductor chip, substrate, connecting structure of electrode for semiconductor chip, and semiconductor module and its manufacturing method Download PDF

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JP2008021751A
JP2008021751A JP2006190868A JP2006190868A JP2008021751A JP 2008021751 A JP2008021751 A JP 2008021751A JP 2006190868 A JP2006190868 A JP 2006190868A JP 2006190868 A JP2006190868 A JP 2006190868A JP 2008021751 A JP2008021751 A JP 2008021751A
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electrode
semiconductor chip
substrate
insertion opening
electrode according
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JP5187714B2 (en
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Yasuhiro Yamaji
泰弘 山地
Hirotaka Osato
啓孝 大里
Tokihiko Yokoshima
時彦 横島
Masahiro Aoyanagi
昌宏 青柳
Hiroshi Nakagawa
博 仲川
Katsuya Kikuchi
克弥 菊地
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National Institute of Advanced Industrial Science and Technology AIST
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
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    • H—ELECTRICITY
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Electric Connection Of Electric Components To Printed Circuits (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrode connecting structure for an electrode and a semiconductor chip, which is capable of eliminating positional deviation of electrodes mutually upon connection, to provide a semiconductor chip, to provide a substrate, to provide a semiconductor device, and to provide its manufacturing method, which are all improved in connecting reliability by equipping these electrode and electrode connecting structure. <P>SOLUTION: A projective electrode 11A is formed at the side of the semiconductor chip 1. The electrode 21 having an inserting opening 22 is formed at the side of the substrate 2. The electrode 11A is connected to the electrode 21A by being inserted into the inserting opening 22 while being slid into a direction toward the center of the electrode 21A along the opening rim of the inserting opening 22 of the electrode 21A. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体チップおよび基板に形成される電極、当該電極を備えた半導体チップおよび基板、当該半導体チップの電極接続構造、半導体モジュールおよびその製造方法に関する。   The present invention relates to an electrode formed on a semiconductor chip and a substrate, a semiconductor chip and a substrate provided with the electrode, an electrode connection structure of the semiconductor chip, a semiconductor module, and a manufacturing method thereof.

従来、半導体チップと基板の接続構造として、半導体チップをフェースダウンで配線基板上に搭載し、バンプ電極を介して両者の電極を接続する構造が知られている（特許文献１、非特許文献１参照）。   Conventionally, as a connection structure between a semiconductor chip and a substrate, a structure in which a semiconductor chip is mounted face-down on a wiring substrate and both electrodes are connected via bump electrodes is known (Patent Document 1, Non-Patent Document 1). reference).

特許文献１および非特許文献１それぞれに記載されている構造では、半導体チップと基板の電極を、その間に設けられた一つの金属製のバンプ電極で接続している。   In the structure described in each of Patent Document 1 and Non-Patent Document 1, the semiconductor chip and the electrode of the substrate are connected by one metal bump electrode provided therebetween.

一方、図２１（ａ）〜（ｃ）は、従来の別の接続構造を説明するための図であり、この構造では、半導体チップ１００の電極パッド１０１および基板２００の電極パッド２０１上にバンプ電極１０２，２０２を設けて、それらを加圧接合している。   On the other hand, FIGS. 21A to 21C are diagrams for explaining another conventional connection structure. In this structure, bump electrodes are formed on the electrode pads 101 of the semiconductor chip 100 and the electrode pads 201 of the substrate 200. 102 and 202 are provided, and they are pressure bonded.

バンプ電極１０２およびバンプ電極２０２は、互いにほぼ同じ幅寸法であり（図２１（ａ）参照）、ほぼ同じ面積の先端表面を有する円柱または角柱状の凸型の金属導体である。バンプ電極１０２，２０２の幅ａ，ｂは、例えば１０μｍ以下である。
特開２００６−１３５７７１号公報 N. Tanaka, Y. Yoshimura, T. Naito, C. Miyazaki, Y. Nemoto, M.Nakanishi and T, Akazawa, “Ultra-Thin 3D-Stacked SIP Formed UsingRoom-Temperature Bonding between Stacked Chips”, 2005 Electronic Components andTechnologyConference, pp.788-794. The bump electrode 102 and the bump electrode 202 are substantially the same width dimension as each other (see FIG. 21A), and are cylindrical or prismatic convex metal conductors having tip surfaces with substantially the same area. The widths a and b of the bump electrodes 102 and 202 are, for example, 10 μm or less.
Japanese Patent Laid-Open No. 2006-135771 N. Tanaka, Y. Yoshimura, T. Naito, C. Miyazaki, Y. Nemoto, M. Nakanishi and T, Akazawa, “Ultra-Thin 3D-Stacked SIP Formed UsingRoom-Temperature Bonding between Stacked Chips”, 2005 Electronic Components and TechnologyConference , pp.788-794.

しかしながら、図２１に例示したような接続構造では、近年のバンプ電極１０２，２０２の微細化に伴う、幅１０μｍ以下の微小バンプ電極の出現により、図２１（ｂ）に示すように、装置の位置合わせ精度の限界（例えば±２〜１０μｍ）に起因する接合初期のずれ、つまり半導体チップ１００の中心Ｍ１と基板２００の中心Ｍ２の位置ずれが発生する。   However, in the connection structure as illustrated in FIG. 21, due to the appearance of a minute bump electrode having a width of 10 μm or less accompanying the recent miniaturization of the bump electrodes 102 and 202, the position of the device is as shown in FIG. A deviation in the initial stage of bonding due to a limit of alignment accuracy (for example, ± 2 to 10 μm), that is, a positional deviation between the center M1 of the semiconductor chip 100 and the center M2 of the substrate 200 occurs.

図２１（ｃ）に示すように、この接合初期のずれは、その後の加圧時のバンプ電極１０２，２０２同士の逃げによる横ずれに繋がる。中心からずれた状態での接合は、著しい接合強度の低下や、断線等の接合不良を引き起こす。   As shown in FIG. 21 (c), the deviation at the initial stage of joining leads to a lateral deviation due to the relief of the bump electrodes 102 and 202 during subsequent pressurization. Bonding in a state deviated from the center causes a significant decrease in bonding strength and bonding failure such as disconnection.

本発明は上記の事情に鑑みてなされたものであり、その目的は、電極同士の位置ずれを接合時に解消することができる電極および半導体チップの電極接続構造を提供することにある。   The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an electrode connection structure for an electrode and a semiconductor chip that can eliminate misalignment between electrodes during bonding.

本発明の他の目的は、上記の電極および半導体チップの電極接続構造を備えることにより、接続信頼性を向上させた半導体チップ、基板、半導体装置およびその製造方法を提供することにある。   Another object of the present invention is to provide a semiconductor chip, a substrate, a semiconductor device, and a method for manufacturing the same, which have improved connection reliability by providing the electrode connection structure of the electrode and the semiconductor chip.

上記の目的を達成するため、本発明の電極は、第１には、突起状の金属導体からなり、接続相手である他の電極に設けられた挿入開口部に挿入される際に、挿入開口部の開口縁または内壁面に沿って他の電極の中心に向かう方向に摺動しながら挿入されて、他の電極と接続されることを特徴とする。   In order to achieve the above object, the electrode of the present invention is first formed of a protruding metal conductor, and is inserted into an insertion opening provided in another electrode which is a connection partner. It is inserted while sliding in the direction toward the center of the other electrode along the opening edge or inner wall surface of the portion, and is connected to the other electrode.

この第１の電極は、第２には、錐体形であること、第３には、先端部が平坦化された錐体形であること、第４には、柱体形であること、をもその特徴とする。   The first electrode has a cone shape in the second, a cone shape with a flattened tip, and a column shape in the fourth. Features.

また、第５には、金属バルク体と、金属バルク体の表面に設けられた金属バルク体とは異なる金属層とを有していること、第６には、前記金属層が、前記金属バルク体よりも低融点の金属でなること、をも特徴とする。   In addition, fifth, the metal bulk body has a metal layer different from the metal bulk body provided on the surface of the metal bulk body, and sixth, the metal layer has the metal bulk body. It is also characterized by being made of a metal having a melting point lower than that of the body.

さらに、本発明の電極は、第７には、接続相手である他の電極を挿入する挿入開口部を備え、他の電極を、挿入開口部の開口縁または内壁面に沿って挿入開口部の中心に向かう方向に摺動させながら挿入させて、他の電極と接続することを特徴とする。   Furthermore, the electrode of the present invention seventhly includes an insertion opening for inserting another electrode as a connection partner, and the other electrode is provided along the opening edge or inner wall surface of the insertion opening. It is inserted while being slid in the direction toward the center, and is connected to another electrode.

この第７の電極は、第８には、ドーナッツ形であること、第９には、前記挿入開口部が円柱空洞状であること、第１０には、前記挿入開口部がすり鉢形の窪みであること、第１１には、前記挿入開口部が錐体形の窪みであること、第１２には、凸状に形成されていること、第１３には、凹状に形成されていること、をもその特徴とする。   The seventh electrode is, in the eighth, a donut shape, in the ninth, the insertion opening is a cylindrical cavity, and in the tenth, the insertion opening is a mortar-shaped depression. Eleventh, the insertion opening is a cone-shaped depression, twelfth is formed in a convex shape, and thirteenth is formed in a concave shape. Its features.

また、第１４には、金属バルク体と、金属バルク体の表面に設けられた金属バルク体とは異なる金属層とを有していること、第１５には、前記金属層が、前記金属バルク体よりも低融点の金属でなること、をもその特徴とする。   The fourteenth aspect includes a metal bulk body and a metal layer different from the metal bulk body provided on the surface of the metal bulk body. Fifteenth, the metal layer includes the metal bulk body. It is also characterized by being made of a metal having a melting point lower than that of the body.

本発明の半導体チップは、前記第１ないし第１５のいずれかの電極を備えたことを特徴とする。   A semiconductor chip according to the present invention includes any one of the first to fifteenth electrodes.

本発明の基板は、前記第１ないし第１５のいずれかの電極を備えたことを特徴とする。   The substrate of the present invention is characterized by comprising any one of the first to fifteenth electrodes.

本発明の半導体チップの電極接続構造は、半導体チップに設けられた前記第１ないし第６のいずれかの電極が、基板もしくは他の半導体チップに設けられた前記第７ないし第１５のいずれかの電極の挿入開口部に挿入されて、前記電極同士が接続されていることを特徴とする。   In the electrode connection structure of a semiconductor chip according to the present invention, any one of the first to sixth electrodes provided on the semiconductor chip may be any one of the seventh to fifteenth provided on a substrate or another semiconductor chip. The electrodes are connected to each other by being inserted into an insertion opening of the electrodes.

本発明の半導体チップの電極接続構造は、基板もしくは半導体チップに設けられた前記第１ないし第６のいずれかの電極が、他の半導体チップに設けられた前記第７ないし第１５のいずれかの電極の挿入開口部に挿入されて、前記電極同士が接続されていることを特徴とする。   The electrode connection structure of a semiconductor chip according to the present invention is such that any one of the first to sixth electrodes provided on the substrate or the semiconductor chip is provided on any other semiconductor chip. The electrodes are connected to each other by being inserted into an insertion opening of the electrodes.

本発明の半導体装置は、基板もしくは半導体チップと他の半導体チップの電極同士が接続された半導体装置であって、前記基板もしくは半導体チップと前記他の半導体チップの電極間において、前記電極接続構造を有することを特徴とする。   The semiconductor device of the present invention is a semiconductor device in which electrodes of a substrate or a semiconductor chip and another semiconductor chip are connected to each other, and the electrode connection structure is provided between the electrodes of the substrate or the semiconductor chip and the other semiconductor chip. It is characterized by having.

本発明の半導体装置の製造方法は、半導体チップに設けた前記第１ないし第６のいずれかの電極を、基板もしくは他の半導体チップに設けた前記第７ないし第１５のいずれかの電極の挿入開口部に挿入して、前記電極同士を接合させることにより、前記半導体チップを前記基板もしくは他の半導体チップ上に搭載することを特徴とする。   According to the method of manufacturing a semiconductor device of the present invention, any one of the first to sixth electrodes provided on a semiconductor chip is inserted into any one of the seventh to fifteenth electrodes provided on a substrate or another semiconductor chip. The semiconductor chip is mounted on the substrate or another semiconductor chip by inserting into the opening and bonding the electrodes together.

本発明の別の半導体装置の製造方法は、基板もしくは半導体チップに設けた前記第１ないし第６のいずれかの電極を、他の半導体チップに設けた前記第７ないし第１５のいずれかの電極の挿入開口部に挿入して、前記電極同士を接合させることにより、前記他の半導体チップを前記基板もしくは他の半導体チップ上に搭載することを特徴とする。   According to another method of manufacturing a semiconductor device of the present invention, any one of the first to sixth electrodes provided on a substrate or a semiconductor chip is used, and any one of the seventh to fifteenth electrodes provided on another semiconductor chip. The other semiconductor chip is mounted on the substrate or another semiconductor chip by inserting the electrode into the insertion opening and bonding the electrodes together.

本発明によれば、電極同士の位置合わせずれを接合時に解消することができる電極および半導体チップの電極接続構造を実現することができる。また、本発明によれば、上記の電極および電極接続構造を備えることにより、接続信頼性を向上させた半導体チップ、基板、半導体装置およびその製造方法を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the electrode connection structure of the electrode and semiconductor chip which can eliminate the misalignment of electrodes at the time of joining is realizable. In addition, according to the present invention, it is possible to provide a semiconductor chip, a substrate, a semiconductor device, and a method for manufacturing the same with improved connection reliability by including the above-described electrode and electrode connection structure.

以下に、本発明の実施の形態について、図面を参照して説明する。   Embodiments of the present invention will be described below with reference to the drawings.

（第１実施形態）
図１〜図３は、各々、本発明の一実施形態を示す図である。 (First embodiment)
1 to 3 are diagrams each showing an embodiment of the present invention.

本実施形態における半導体チップ１は、基板２側を向いた第一面である回路形成面の適宜位置に形成された電極パッド１０と、その上に突起状に形成された電極１１Ａを有している。   The semiconductor chip 1 in this embodiment has an electrode pad 10 formed at an appropriate position on a circuit formation surface, which is a first surface facing the substrate 2, and an electrode 11A formed in a protruding shape on the electrode pad 10. Yes.

この半導体チップ１が搭載される基板２は、半導体チップ１側を向く第一面の適宜位置に形成された電極パッド２０と、その上に突出して形成された電極２１Ａを有している。   The substrate 2 on which the semiconductor chip 1 is mounted has an electrode pad 20 formed at an appropriate position on the first surface facing the semiconductor chip 1 side, and an electrode 21A formed so as to protrude thereon.

半導体チップ１の電極１１Ａは、図２（ａ）に示したように、高さ方向に従ってつまり基板２方向に向かって幅が狭まっていく円錐形の金属導体であり、バンプ電極とも呼べる。円錐形導体は、電極中心に対称な形状であり、その側面１２は滑らかな面となっている。電極１１Ａの円推形への加工は、たとえばレジストを用いたエッチングにより行われる。   As shown in FIG. 2A, the electrode 11A of the semiconductor chip 1 is a conical metal conductor whose width decreases in the height direction, that is, toward the substrate 2, and can also be called a bump electrode. The conical conductor has a symmetrical shape with respect to the center of the electrode, and its side surface 12 is a smooth surface. The electrode 11A is processed into a circular shape by, for example, etching using a resist.

基板２の電極２１Ａは、図２（ｂ）に示したように、深さ方向に幅（径とも呼べる）が均一な円柱空洞状の挿入開口部２２を略中央に有する、肉厚のドーナツ形（円筒形とも呼べる）の金属導体となっている。ドーナッツ形導体は、電極中心に対称な形状である。電極２１Ａのドーナッツ形への加工や挿入開口部２２の形成は、たとえばレジストパターンを用いたエッチングにより行われる。   As shown in FIG. 2B, the electrode 21A of the substrate 2 has a thick donut shape having a cylindrical hollow insertion opening 22 having a uniform width (also referred to as a diameter) in the depth direction. It is a metal conductor (also called a cylindrical shape). The donut-shaped conductor has a symmetrical shape with respect to the center of the electrode. The processing of the electrode 21A into a donut shape and the formation of the insertion opening 22 are performed, for example, by etching using a resist pattern.

電極１１Ａと電極２１Ａの関係については、互いに対応する位置に配置されているとともに、電極２１Ａの挿入開口部２２の内径ｂが電極１１Ａの底面の径ａよりも小さくされている（ｂ＜ａ）。   Regarding the relationship between the electrode 11A and the electrode 21A, they are arranged at positions corresponding to each other, and the inner diameter b of the insertion opening 22 of the electrode 21A is smaller than the diameter a of the bottom surface of the electrode 11A (b <a). .

このような電極１１Ａを備えた半導体チップ１と電極２１Ａを備えた基板２とからなる半導体装置の製造においては、互いに対応する位置に配置された各電極１１Ａと各電極２１Ａの中心位置が揃うように位置合わせを行う必要があるが、上記の通りの円錐状およびドーナッツ状を有していることで、自動的に中心アライメント（位置補正）が実現されることとなる。   In manufacturing a semiconductor device including the semiconductor chip 1 having the electrode 11A and the substrate 2 having the electrode 21A, the center positions of the electrodes 11A and the electrodes 21A arranged at positions corresponding to each other are aligned. However, by having the cone shape and the donut shape as described above, center alignment (position correction) is automatically realized.

すなわち、図３に示すように、接合前において半導体チップ１の中心Ｍ１が基板２の中心Ｍ２からずれていても、まず電極１１Ａの先端が電極２１Ａの挿入開口部２２内に入り、続いて電極１１Ａの側面１２が挿入開口部２２の開口縁に接触し、そのまま開口縁に沿って滑り落ちながら、電極１１Ａ全体が電極２１Ａの中心に向かう方向に摺動する。この結果、挿入開口部２２の底部まで電極１１Ａの先端が到達した時点で、電極１１Ａ，２１Ａ同士の中心位置が揃うことになる。図中、僅かに横方向にずれていたそれぞれの垂直中心線が、挿入開口部２２の開口縁に接触した状態の電極１１Ａが電極２１Ａの中心に向かう斜め左下方向に摺動した後、互いに一致していることが分かる。   That is, as shown in FIG. 3, even if the center M1 of the semiconductor chip 1 is shifted from the center M2 of the substrate 2 before bonding, the tip of the electrode 11A first enters the insertion opening 22 of the electrode 21A, and then the electrode The entire surface of the electrode 11A slides in the direction toward the center of the electrode 21A while the side surface 12 of the 11A contacts the opening edge of the insertion opening 22 and slides down along the opening edge. As a result, when the tip of the electrode 11A reaches the bottom of the insertion opening 22, the center positions of the electrodes 11A and 21A are aligned. In the drawing, the vertical center lines slightly shifted in the lateral direction are aligned with each other after the electrode 11A in contact with the opening edge of the insertion opening 22 slides obliquely downward to the left toward the center of the electrode 21A. You can see that you are doing it.

そして、必要に応じて加圧および加熱処理などを施し、電極１１Ａ，２１Ａ同士を接合させる。図３では、接合後の電極１１Ａの先端部を、加圧および加熱によって挿入開口部２２内にて潰れて広がった状態になっているものとして図示している。後述する各実施形態でも同様な処理が施される。   Then, pressure and heat treatment are performed as necessary to join the electrodes 11A and 21A. In FIG. 3, the distal end portion of the electrode 11 </ b> A after bonding is illustrated as being in a state of being crushed and expanded in the insertion opening 22 by pressurization and heating. Similar processing is performed in each embodiment described later.

以上により、半導体チップ１を基板２上に搭載させる際に、自動的に半導体チップ１と基板２の中心位置ずれを補正しつつ、電極１１Ａ，２１Ａ同士を接続することが可能となる。   As described above, when the semiconductor chip 1 is mounted on the substrate 2, the electrodes 11 </ b> A and 21 </ b> A can be connected to each other while automatically correcting the center position shift between the semiconductor chip 1 and the substrate 2.

本実施形態によれば、半導体チップ１側に高さ方向に幅が減少する突起状の電極１１Ａを設け、基板２側に挿入開口部２２を有する電極２１Ａを設けることにより、半導体チップ１と基板２との接合過程において、電極２１Ａの挿入開口部２２に電極１１Ａを挿入させるだけで、中心ずれを解消する自動アライメントが行われることとなる。したがって、基板２上への半導体チップ１の実装精度を向上させることができ、接続信頼性を向上させた電極接続構造および半導体モジュールを実現することができる。   According to the present embodiment, the semiconductor chip 1 and the substrate are provided by providing the protruding electrode 11A whose width decreases in the height direction on the semiconductor chip 1 side and the electrode 21A having the insertion opening 22 on the substrate 2 side. In the process of joining with No. 2, automatic alignment for eliminating the center deviation is performed only by inserting the electrode 11A into the insertion opening 22 of the electrode 21A. Therefore, the mounting accuracy of the semiconductor chip 1 on the substrate 2 can be improved, and an electrode connection structure and a semiconductor module with improved connection reliability can be realized.

なお、半導体チップ１の電極１１Ａについては、円錐形のみならず、角錐形の錐体とすることもできる。角錐形の電極１１Ａであっても、基板２の電極２１Ａに設けられた挿入開口部２２の開口縁に接触して電極２１Ａの中心に向かう方向に摺動しながら、挿入開口部２２内に落とし込まれて、互いの中心位置が揃うことになり、半導体チップ１の基板２への実装と位置合わせと電極接続を同時に高精度で実現できる。   Note that the electrode 11A of the semiconductor chip 1 may be not only a conical shape but also a pyramid. Even the pyramidal electrode 11A is dropped into the insertion opening 22 while sliding in the direction toward the center of the electrode 21A in contact with the opening edge of the insertion opening 22 provided on the electrode 21A of the substrate 2. As a result, the center positions of the semiconductor chips 1 are aligned, and mounting, positioning, and electrode connection of the semiconductor chip 1 to the substrate 2 can be simultaneously realized with high accuracy.

また、上述した電極２１Ａに対する電極１１Ａの摺動をスムーズなものにして、より高精度な位置合わせを実現するには、電極１１Ａ，２１Ａはともに、接触時に変形しない剛体であることが望ましい。   Moreover, in order to make the sliding of the electrode 11A with respect to the electrode 21A described above smooth and realize a more accurate alignment, it is desirable that both the electrodes 11A and 21A are rigid bodies that do not deform when contacted.

（第２実施形態）
図４〜図６は、各々、本発明の別の実施形態示す図である。 (Second Embodiment)
4-6 is a figure which shows another embodiment of this invention, respectively.

本実施形態では、半導体チップ１の電極１１Ｂが、円錐体の先端部を平坦化した断面台形の金属導体となっている。他の構成は第１実施形態と同じである。平坦先端を持つ錐体形の加工は、たとえばレジストを用いたエッチングにより行われる。   In the present embodiment, the electrode 11B of the semiconductor chip 1 is a metal conductor having a trapezoidal cross section in which the tip of the cone is flattened. Other configurations are the same as those of the first embodiment. The processing of the cone shape having a flat tip is performed by etching using a resist, for example.

電極１１Ｂの先端が若干平坦になっていることにより、電極１１Ｂの作製がより容易となり、各電極１１Ｂの高さをより高精度で揃えやすいという利点がある。   Since the tip of the electrode 11B is slightly flat, it is easier to manufacture the electrode 11B, and there is an advantage that the height of each electrode 11B can be easily aligned with high accuracy.

この場合、電極２１Ａの挿入開口部２２の内径ｂは電極１１Ｂの底面の径ａよりも小さく、先端幅ｃよりも大きい（ｃ＜ｂ＜ａ）という条件が必要である。   In this case, it is necessary that the inner diameter b of the insertion opening 22 of the electrode 21A is smaller than the diameter a of the bottom surface of the electrode 11B and larger than the tip width c (c <b <a).

このような電極１１Ｂと電極２１Ａによっても、第１実施形態と同様にして、図６に示すように、接合前において半導体チップ１の中心Ｍ１が基板２の中心Ｍ２からずれていても、まず電極１１Ｂの平坦状先端が電極２１Ａの挿入開口部２２内に入り、続いて電極１１Ｂの側面１２が挿入開口部２２の開口縁に接触し、そのまま開口縁に沿って滑り落ちながら、電極１１Ｂ全体が電極２１Ａの中心に向かう方向に摺動する。この結果、挿入開口部２２の底部まで電極１１Ｂの平坦状先端が到達した時点で、電極１１Ｂ，２１Ａ同士の中心位置が一致することになる。   Even with such an electrode 11B and electrode 21A, as in the first embodiment, even if the center M1 of the semiconductor chip 1 is shifted from the center M2 of the substrate 2 before bonding, as shown in FIG. The flat tip of 11B enters the insertion opening 22 of the electrode 21A, and then the side surface 12 of the electrode 11B comes into contact with the opening edge of the insertion opening 22 and slides down along the opening edge. Slide in a direction toward the center of the electrode 21A. As a result, when the flat tip of the electrode 11B reaches the bottom of the insertion opening 22, the center positions of the electrodes 11B and 21A coincide.

よって、半導体チップ１と基板２の位置ずれを補正しつつ、互いの電極１１Ｂ，２１Ａ同士を接続することが可能となり、半導体チップ１の実装と位置合わせと電極接続を同時に高精度で実現することができる。   Therefore, it is possible to connect the electrodes 11B and 21A to each other while correcting the positional deviation between the semiconductor chip 1 and the substrate 2, and to simultaneously mount and align the semiconductor chip 1 and connect the electrodes with high accuracy. Can do.

（第３実施形態）
図７〜図９は、本発明の第３実施形態を示す図である。
本実施形態では、基板２が、その電極パッド２０上に、深さ方向にしたがって次第に内径（開口幅とも呼べる）が減少するすり鉢形（円錐形または半円形とも呼べる）の窪みである挿入開口部２２を有する電極２１Ｂを備えている。他の構成は第２実施形態と同じである。 (Third embodiment)
7-9 is a figure which shows 3rd Embodiment of this invention.
In this embodiment, the substrate 2 is an insertion opening that is a mortar-shaped (also called conical or semicircular) depression whose inner diameter (also called opening width) gradually decreases in the depth direction on the electrode pad 20. An electrode 21B having 22 is provided. Other configurations are the same as those of the second embodiment.

電極２１へのすり鉢状の挿入開口部２２の形成は、たとえばレジストパターンを用いたエッチングにより行われる。エッチングの条件を調節することにより、窪みの形状を制御することができる。   The mortar-shaped insertion opening 22 is formed in the electrode 21 by, for example, etching using a resist pattern. The shape of the depression can be controlled by adjusting the etching conditions.

なお、本実施形態の半導体チップ１は、第２実施形態と同じ平坦化先端を持つ円錐形の電極１１Ｂを備えているが、第１実施形態と同じ円錐形の電極１１Ａとしても良いことは言うまでもない。もちろん角錐形も採用できる。   The semiconductor chip 1 of this embodiment includes the conical electrode 11B having the same flattening tip as that of the second embodiment, but needless to say, the same conical electrode 11A as that of the first embodiment may be used. Yes. Of course, a pyramid shape can also be adopted.

このような電極２１Ｂと電極１１Ｂ（又は電極１１Ａ）を備えた構造によっても、第１，第２実施形態と同様にして、図９に示すように、接合前において半導体チップ１の中心Ｍ１が基板２の中心Ｍ２からずれていても、まず電極１１Ｂの平坦状先端が電極２１Ａの挿入開口部２２内に入り、続いて電極１１Ｂの側面１２ないしは平坦状先端の周縁が挿入開口部２２の開口縁ないしは内壁面に接触し、そのまま挿入開口部２２に沿って滑り落ちながら、電極１１Ｂ全体が電極２１Ｂの中心に向かう方向に摺動する。この結果、挿入開口部２２の底部まで電極１１Ｂの平坦状先端が到達した時点で、電極１１Ｂ，２１Ｂ同士の中心位置が一致することになる。   Even with such a structure including the electrode 21B and the electrode 11B (or the electrode 11A), as in the first and second embodiments, the center M1 of the semiconductor chip 1 is the substrate before bonding as shown in FIG. 2, the flat tip of the electrode 11 </ b> B first enters the insertion opening 22 of the electrode 21 </ b> A, and then the side surface 12 of the electrode 11 </ b> B or the periphery of the flat tip is the opening edge of the insertion opening 22. Or the entire electrode 11B slides in the direction toward the center of the electrode 21B while contacting the inner wall surface and sliding down along the insertion opening 22 as it is. As a result, when the flat tip of the electrode 11B reaches the bottom of the insertion opening 22, the center positions of the electrodes 11B and 21B coincide with each other.

よって、半導体チップ１と基板２の位置ずれを補正しつつ、互いの電極１１Ｂ，２１Ｂ同士を接続することが可能となり、半導体チップ１の実装と位置合わせと電極接続を同時に高精度で実現することができる。   Therefore, it is possible to connect the electrodes 11B and 21B to each other while correcting the misalignment between the semiconductor chip 1 and the substrate 2, and to simultaneously mount and align the semiconductor chip 1 and connect the electrodes with high accuracy. Can do.

本実施形態によれば、電極２１Ｂにおけるすり鉢形の挿入開口部２２の内壁面が曲面となっており、この曲面に沿って電極１１Ｂの先端部が位置合わせされるため、ずれに対する補正効果および安定した接合効果を更に向上させることができる。   According to the present embodiment, the inner wall surface of the mortar-shaped insertion opening 22 in the electrode 21B is a curved surface, and the tip of the electrode 11B is aligned along this curved surface. The improved bonding effect can be further improved.

なお、本実施形態では、第１、第２実施形態と異なり、挿入開口部２２の開口幅ｄが先端幅ｃよりも大（ｄ＞ｃ）であれば、挿入開口部２２の開口幅ｄについて必ずしもｄ＜ａの関係が成り立たなくとも、位置合わせは十分可能となる。したがって、半導体チップ１と基板２の間の初期の位置ずれに対する許容度が更に増し、より安定した加圧による金属接合が可能となる。   In the present embodiment, unlike the first and second embodiments, if the opening width d of the insertion opening 22 is larger than the tip width c (d> c), the opening width d of the insertion opening 22 will be described. Even if the relationship of d <a does not necessarily hold, the alignment is sufficiently possible. Therefore, the tolerance for the initial positional deviation between the semiconductor chip 1 and the substrate 2 is further increased, and metal bonding by more stable pressurization is possible.

（第４実施形態）
上記第３実施形態では、基板２の電極２１Ｂにおける挿入開口部２２の形状をすり鉢形としているが、これ以外にも、たとえば図１０（ａ）に示すような角錐形の窪みとすることもできる（電極２１Ｃ）。 (Fourth embodiment)
In the said 3rd Embodiment, although the shape of the insertion opening part 22 in the electrode 21B of the board | substrate 2 is a mortar shape, it can also be set as a pyramid-shaped hollow as shown, for example to Fig.10 (a). (Electrode 21C).

この場合も同様に、図１０（ｂ）に示すように、半導体チップ２の搭載時に中心位置を自動アライメントし、安定した電極接合を実現できる。   Similarly in this case, as shown in FIG. 10B, the center position is automatically aligned when the semiconductor chip 2 is mounted, and stable electrode bonding can be realized.

（第５実施形態）
図１１〜図１３は、本発明の第５実施形態を示す図である。 (Fifth embodiment)
11-13 is a figure which shows 5th Embodiment of this invention.

上述した第１〜第４実施形態では、基板２に設けられている電極パッド２０上に電極２１（電極２１Ａ等を総称して電極２１と呼ぶ）を、上方に突出させて凸状に形成している。   In the first to fourth embodiments described above, the electrode 21 (the electrode 21A and the like are collectively referred to as the electrode 21) is formed on the electrode pad 20 provided on the substrate 2 so as to protrude upward. ing.

これに対し、本実施形態では、基板２の電極形成領域に、深さ方向に従って次第に内径が減少する角錐形の凹部を設け、この凹部を被覆するように薄膜状の金属導体を形成することにより、この金属導体を、凹部形状に沿った角錐形の挿入開口部２２を備えた電極２１Ｄとしている。   On the other hand, in this embodiment, a pyramid-shaped recess whose inner diameter gradually decreases in the depth direction in the electrode formation region of the substrate 2 and a thin-film metal conductor is formed so as to cover the recess. The metal conductor is an electrode 21D having a pyramidal insertion opening 22 along the shape of the recess.

基板２への凹部の形成は、たとえばレジストパターンを用いたエッチングにより行われる。エッチングの条件を調節することにより、凹部の形状を制御することができる。   The formation of the recesses in the substrate 2 is performed by etching using, for example, a resist pattern. The shape of the recess can be controlled by adjusting the etching conditions.

このような電極２１Ｄによっても、図１３に示すように、接合前において半導体チップ１の中心Ｍ１が基板２の中心Ｍ２からずれていても、まず電極１１Ｂの先端が電極２１Ｄの挿入開口部２２内に入り、続いて電極１１Ｂの側面１２ないしは平坦状先端の周縁が挿入開口部２２の内壁面に接触し、そのまま挿入開口部２２に沿って滑り落ちながら、電極１１Ｂ全体が電極２１の中心に向かう方向に摺動する。この結果、挿入開口部２２の底部まで電極１１Ｂの先端が到達した時点で、電極１１Ｂ，２１Ｄ同士の中心位置が揃うことになる。   Even with such an electrode 21D, as shown in FIG. 13, even if the center M1 of the semiconductor chip 1 is deviated from the center M2 of the substrate 2 before bonding, the tip of the electrode 11B is first in the insertion opening 22 of the electrode 21D. Subsequently, the side surface 12 of the electrode 11B or the peripheral edge of the flat tip contacts the inner wall surface of the insertion opening 22 and slides down along the insertion opening 22 as it is, so that the entire electrode 11B moves toward the center of the electrode 21. Slide in the direction. As a result, when the tip of the electrode 11B reaches the bottom of the insertion opening 22, the center positions of the electrodes 11B and 21D are aligned.

以上により、半導体チップ１と基板２の位置ずれを補正しつつ、互いの電極１１Ｂ，２１Ｄ同士を接続することが可能となり、半導体チップ１の実装と位置合わせと電極接続を同時に高精度で実現することができる。   As described above, the electrodes 11B and 21D can be connected to each other while correcting the positional deviation between the semiconductor chip 1 and the substrate 2, and the mounting, alignment, and electrode connection of the semiconductor chip 1 are simultaneously realized with high accuracy. be able to.

本実施形態によれば、第３，４実施形態と同様に、ずれに対する補正効果および安定した接合効果を更に向上させることができる。   According to the present embodiment, as in the third and fourth embodiments, it is possible to further improve the correction effect on displacement and the stable joining effect.

なお、本実施形態では、第１、第２実施形態と異なり、挿入開口部２２の開口幅ｄが先端幅ｃよりも大（ｂ＞ｃ）であれば、挿入開口部２２の幅ｄについて必ずしもｄ＜ａの関係が成り立たなくとも、位置合わせは十分可能となる。したがって、半導体チップ１と基板２の間の初期の位置ずれに対する許容度が更に増し、より安定した加圧による金属接合が可能となる。   In this embodiment, unlike the first and second embodiments, if the opening width d of the insertion opening 22 is larger than the tip width c (b> c), the width d of the insertion opening 22 is not necessarily limited. Even if the relationship of d <a does not hold, alignment is sufficiently possible. Therefore, the tolerance for the initial positional deviation between the semiconductor chip 1 and the substrate 2 is further increased, and metal bonding by more stable pressurization is possible.

（第６実施形態）
上記第５実施形態では、基板２の電極２１Ｄにおける挿入開口部２２の形状を角錐形としているが、これ以外にも、たとえば図１４（ｂ）に示すような円錐形の窪みとする電極２１Ｅも採用でき、同様にして位置ずれを補正した電極接合を実現できる。 (Sixth embodiment)
In the fifth embodiment, the shape of the insertion opening 22 in the electrode 21D of the substrate 2 is a pyramid, but in addition to this, for example, an electrode 21E having a conical depression as shown in FIG. It can be employed, and similarly, electrode joining with corrected misalignment can be realized.

また、半導体チップ１は、たとえば図１４（ａ）に示すような円柱形の電極１１Ｃを有するものとしてもよい。   Further, the semiconductor chip 1 may have a columnar electrode 11C as shown in FIG.

たとえばこの電極１１Ｃと電極２１Ｅを組み合わせた場合にも、図１４（ｃ）に示すように、他の実施形態と同様にして中心位置ずれを自動補正した電極接合を実現できる。   For example, even when the electrode 11C and the electrode 21E are combined, as shown in FIG. 14C, electrode joining in which the center position deviation is automatically corrected can be realized in the same manner as in the other embodiments.

（第７実施形態）
図１５〜図１７は、本発明の第７実施形態を示す図である。 (Seventh embodiment)
15-17 is a figure which shows 7th Embodiment of this invention.

本実施形態は、半導体チップ１における円柱形の電極１１Ｃと基板２における突出すり鉢形の電極２１Ｂを組み合わせた場合のものであり、他の実施形態と同様にして、半導体チップ１の実装と位置合わせと電極接続を同時に高精度で実現することができる。   In the present embodiment, the cylindrical electrode 11C in the semiconductor chip 1 and the projecting mortar-shaped electrode 21B in the substrate 2 are combined, and the mounting and alignment of the semiconductor chip 1 are performed in the same manner as in the other embodiments. And electrode connection can be realized simultaneously with high accuracy.

このような電極１１Ｃと電極２１Ｂによっても、図１７に示すように、接合前において、半導体チップ１の中心Ｍ１が基板２の中心Ｍ２からずれていても、まず電極１１Ｃの先端が電極２１Ｂの挿入開口部２２内に入り、続いて電極１１Ｃの先端周縁が挿入開口部２２の内壁面に接触し、そのまま挿入開口部２２に沿って滑り落ちながら、電極１１Ｃ全体が電極２１の中心に向かう方向に摺動する。この結果、挿入開口部２２の底部まで電極１１Ｃの先端が到達した時点で、電極１１Ｃ，２１Ｂ同士の中心位置が揃うことになる。   Even with such an electrode 11C and electrode 21B, as shown in FIG. 17, even if the center M1 of the semiconductor chip 1 is shifted from the center M2 of the substrate 2 before bonding, the tip of the electrode 11C is first inserted into the electrode 21B. The entire periphery of the electrode 11 </ b> C is directed toward the center of the electrode 21 while entering the opening 22, and subsequently the tip periphery of the electrode 11 </ b> C contacts the inner wall surface of the insertion opening 22 and slides down along the insertion opening 22. Slide. As a result, when the tip of the electrode 11C reaches the bottom of the insertion opening 22, the center positions of the electrodes 11C and 21B are aligned.

以上により、半導体チップ１と基板２の位置ずれを補正しつつ、互いの電極１１Ｃ，２１Ｂ同士を接続することが可能となり、半導体チップ１の実装と位置合わせと電極接続を同時に高精度で実現することができる。   As described above, the electrodes 11C and 21B can be connected to each other while correcting the positional deviation between the semiconductor chip 1 and the substrate 2, and the mounting, alignment, and electrode connection of the semiconductor chip 1 are simultaneously realized with high accuracy. be able to.

本実施形態では、凸状の電極１１（電極１１Ａ等を総称して電極１１と呼ぶ）に対する形状の制限が無くなるため、半導体チップ１側の電極１１形成の設計上およびプロセス上の自由度を向上させることができる。   In the present embodiment, since there is no limitation on the shape of the convex electrode 11 (the electrode 11A and the like are collectively referred to as the electrode 11), the degree of freedom in design and process of forming the electrode 11 on the semiconductor chip 1 side is improved. Can be made.

また、半導体チップ１の電極１１Ｃについては、円柱形以外にも、角柱形の柱体とすることもできる。角柱形の電極１１Ｃであっても、同様にして、半導体チップ１の基板２への実装と位置合わせと電極接続を同時に高精度で実現できる。   In addition, the electrode 11C of the semiconductor chip 1 may be a prismatic column other than the cylinder. Even in the case of the prismatic electrode 11C, the mounting, alignment and electrode connection of the semiconductor chip 1 to the substrate 2 can be simultaneously realized with high accuracy.

（第８実施形態）
本実施形態は、図１８（ａ）（ｂ）（ｃ）に示すように、上記円柱形の電極１１Ｃと角錐形の挿入開口部２２を持つ電極２１Ｃを組み合わせた場合のものであり、他の実施形態と同様にして、半導体チップ１の基板２への搭載時に電極１１Ｃを電極２１Ｃの挿入開口部２２に挿入させるだけで、自動位置アライメントを伴う良好な電極接合を容易に実現できる。 (Eighth embodiment)
As shown in FIGS. 18A, 18B, and 18C, the present embodiment is a combination of the cylindrical electrode 11C and the electrode 21C having the pyramidal insertion opening 22, and the other Similar to the embodiment, it is possible to easily realize good electrode joining with automatic position alignment by simply inserting the electrode 11C into the insertion opening 22 of the electrode 21C when the semiconductor chip 1 is mounted on the substrate 2.

（第９実施形態）
図１９は、本発明の第９実施形態を示す断面図である。 (Ninth embodiment)
FIG. 19 is a cross-sectional view showing a ninth embodiment of the present invention.

本実施形態は、第１〜第８実施形態と比べて、半導体チップ１側と基板２側の電極１１，２１の凹凸構造が逆転した例である。   This embodiment is an example in which the concavo-convex structure of the electrodes 11 and 21 on the semiconductor chip 1 side and the substrate 2 side is reversed as compared with the first to eighth embodiments.

本実施形態における半導体チップ１は、基板２側を向いた第一面である回路形成面の適宜位置に形成された電極パッド１０と、その上に突出して形成された電極１１Ｄを有している。   The semiconductor chip 1 in the present embodiment includes an electrode pad 10 formed at an appropriate position on a circuit formation surface that is a first surface facing the substrate 2 side, and an electrode 11D formed so as to protrude thereon. .

この半導体チップ１が搭載される基板２は、半導体チップ１側を向く第一面の適宜位置に形成された電極パッド２０と、その上に形成された突起状の電極２１Ｆを有している。   The substrate 2 on which the semiconductor chip 1 is mounted has an electrode pad 20 formed at an appropriate position on the first surface facing the semiconductor chip 1 side, and a protruding electrode 21F formed thereon.

半導体チップ１の電極１１Ｄは、深さ方向に幅（径とも呼べる）が均一な円柱空洞状の挿入開口部１３を略中央に有する、肉厚のドーナツ形（円筒形とも呼べる）の金属導体となっている。ドーナッツ形導体は、電極中心に対称な形状である。電極１１Ｄのドーナッツ形への加工や挿入開口部１３の形成は、たとえばレジストパターンを用いたエッチングにより行われる。   The electrode 11D of the semiconductor chip 1 has a thick donut-shaped (also called cylindrical) metal conductor having a cylindrical hollow insertion opening 13 having a uniform width (also called diameter) in the depth direction at the center. It has become. The donut-shaped conductor has a symmetrical shape with respect to the center of the electrode. The processing of the electrode 11D into a donut shape and the formation of the insertion opening 13 are performed, for example, by etching using a resist pattern.

基板２の電極２１Ｆは、高さ方向に従ってつまり半導体チップ１方向に向かって幅が狭まっていく円錐形であって、且つその先端部を平坦化した断面台形の金属導体であり、バンプ電極とも呼べる。円錐形導体は、電極中心に対称な形状であり、その側面１２は滑らかな面となっている。この電極２１Ｆの加工は、たとえばレジストを用いたエッチングにより行われる。   The electrode 21F of the substrate 2 is a cone-shaped metal conductor whose width decreases in the direction of the height, that is, toward the semiconductor chip 1, and is a trapezoidal metal conductor with a flattened tip, and can also be called a bump electrode. . The conical conductor has a symmetrical shape with respect to the center of the electrode, and its side surface 12 is a smooth surface. The processing of the electrode 21F is performed by etching using a resist, for example.

電極１１Ｄと電極２１Ｆの関係については、互いに対応する位置に配置されているとともに、電極１１Ｄの挿入開口部１３の内径ｂが電極２１Ｆの底面の径ａよりも小さくされている（ｂ＜ａ）。   Regarding the relationship between the electrode 11D and the electrode 21F, they are arranged at positions corresponding to each other, and the inner diameter b of the insertion opening 13 of the electrode 11D is smaller than the diameter a of the bottom surface of the electrode 21F (b <a). .

このような構造によっても、接合前において半導体チップ１の中心Ｍ１が基板２の中心Ｍ２からずれていても、電極１１Ｄの挿入開口部１３へ電極１２１Ｆが挿入されていくに従って、電極１１Ｄは電極２１Ｆの中心に向かって摺動する。この結果、挿入開口部１３の底部まで電極２１Ｆの平坦状先端が到達した時点で、電極１１Ｄ，２１Ｆ同士の中心位置が一致することになる。   Even with such a structure, even if the center M1 of the semiconductor chip 1 is deviated from the center M2 of the substrate 2 before bonding, the electrode 11D becomes the electrode 21F as the electrode 121F is inserted into the insertion opening 13 of the electrode 11D. Slide toward the center of the. As a result, when the flat tip of the electrode 21F reaches the bottom of the insertion opening 13, the center positions of the electrodes 11D and 21F coincide with each other.

よって、半導体チップ１と基板２の位置ずれを補正しつつ、互いの電極１１Ｄ，２１Ｆ同士を安定して接合させることが可能となり、半導体チップ１の実装と位置合わせと電極接続を同時に高精度で実現することができる。   Therefore, it is possible to stably bond the electrodes 11D and 21F to each other while correcting the positional deviation between the semiconductor chip 1 and the substrate 2, and simultaneously mounting, aligning and connecting the electrodes of the semiconductor chip 1 with high accuracy. Can be realized.

もちろん、半導体チップ１と基板２の電極１１，２１を逆転させただけであるので、図示した電極１１Ｄ（電極２１Ｂに対応），２１Ｆ（電極１１Ｂに対応）の組み合わせだけでなく、他の実施形態における電極１１，２１のあらゆる組み合わせを逆にした組み合わせも採用できる。   Of course, since the electrodes 11 and 21 of the semiconductor chip 1 and the substrate 2 are merely reversed, not only the combination of the illustrated electrodes 11D (corresponding to the electrode 21B) and 21F (corresponding to the electrode 11B) but also other embodiments. Combinations in which all combinations of the electrodes 11 and 21 are reversed can also be employed.

（第１０実施形態）
ところで、半導体チップ１の電極１１および基板２の電極２１は、第１の実施形態でも述べたように、電極２１に対する電極１１の摺動スムーズ化を図るべく、接触時に変形しない剛体であることが望ましいとした。 (10th Embodiment)
By the way, as described in the first embodiment, the electrode 11 of the semiconductor chip 1 and the electrode 21 of the substrate 2 are rigid bodies that are not deformed at the time of contact in order to achieve smooth sliding of the electrode 11 with respect to the electrode 21. Desirable.

しかしながら、一般には、金属同士の接合の際には、少なくとも接合に寄与する金属部は変形しやすいように硬度を下げて柔らかくすることも重要である。   However, in general, at the time of joining metals, it is also important to lower the hardness and soften at least the metal part that contributes to the joining so as to be easily deformed.

そこで、本発明は、たとえば図２０Ａ，２０Ｂに示したように、電極１１および電極２１を、金属バルク体（母材とも呼べる）１１ａ，２１ａと、金属バルク体１１ａ，２１ａの表面に設けられた金属バルク体１１ａ，２１ａとは異なる金属層（異種金属層とも呼べる）１１ｂ，２１ｂとを有するものとした実施形態も採用することができる。   Therefore, in the present invention, for example, as shown in FIGS. 20A and 20B, the electrode 11 and the electrode 21 are provided on the surfaces of the metal bulk bodies (also called base materials) 11a and 21a and the metal bulk bodies 11a and 21a. An embodiment having metal layers (also called different metal layers) 11b and 21b different from the metal bulk bodies 11a and 21a can also be adopted.

金属バルク体１１ａ，２１ａは、適度な硬さの金属、たとえば銅Ｃｕ等、でなる剛体とし、金属層１１ｂ，２１ｂは、金属バルク体よりも低融点の金属、たとえばすずＳｎやＳｎ系合金もしくは変形しやすい柔らかい金属、でなる層状体とする。   The metal bulk bodies 11a and 21a are rigid bodies made of a moderately hard metal such as copper Cu, and the metal layers 11b and 21b are metals having a melting point lower than that of the metal bulk body, such as tin Sn or Sn-based alloys or A layered body made of a soft metal that easily deforms.

この構造によれば、挿入の際、電極１１，２１が変形することなくスムーズな摺動による位置合わせが行われる一方で、その後の接合に際しては、低融点金属の金属層１１ｂ，２１ｂを介することにより、上下の電極１１，２１間の低温での確実な溶融接合もしくは拡散接合による金属接合が行われることとなる。   According to this structure, during insertion, the electrodes 11 and 21 are aligned by smooth sliding without deformation, while the subsequent joining is performed through the metal layers 11b and 21b of the low melting point metal. As a result, reliable metal bonding or diffusion bonding between the upper and lower electrodes 11 and 21 at a low temperature is performed.

なお、金属バルク体１１ａ，２１ａと金属層１１ｂ，２１ｂでなる構造は、上下の電極１１および電極２１の両方でも、どちらか一方でもよい。少なくとも一方がこの構造を有していれば上記効果を実現できる。   In addition, the structure which consists of the metal bulk bodies 11a and 21a and the metal layers 11b and 21b may be either one of the upper and lower electrodes 11 and 21, or one of them. If at least one of them has this structure, the above effect can be realized.

また、金属層１１ｂ，２１ｂは、金属バルク体１１ａ，２１ａの表面の全部でなくても、接合相手の電極１１，２１と接触する一部分に設けられていればよい。   Further, the metal layers 11b and 21b may be provided on a part of the metal bulk bodies 11a and 21a that are in contact with the electrodes 11 and 21 to be joined, even if not all of the surfaces of the metal bulk bodies 11a and 21a.

たとえば、図２０Ａ（ａ）（ｂ）は、各々、金属層１１ｂを、図１〜図３の実施形態で用いられている電極１１Ａの表面全領域に設けた例、先端頂点から側面の一部まで覆う領域にのみ選択的に形成した例を示している。   For example, FIGS. 20A (a) and 20 (b) show examples in which the metal layer 11b is provided in the entire surface area of the electrode 11A used in the embodiment of FIGS. An example is shown in which it is selectively formed only in the region covering up to.

図２０Ａ（ｃ）（ｄ）は、各々、金属層１１ｂを、図４〜図１３の実施形態で用いられている電極１１Ｂの表面全領域に設けた例、先端表面領域にのみ選択的に形成した例を示している。   20A (c) and 20 (d) are examples in which the metal layer 11b is provided in the entire surface area of the electrode 11B used in the embodiment of FIGS. 4 to 13, and selectively formed only in the tip surface area. An example is shown.

図２０Ａ（ｅ）（ｆ）（ｇ）は、金属層１１ｂを、図１４〜図１８の実施形態で用いられている電極１１Ｃの表面全領域に設けた例、先端表面から側面の一部まで覆う領域または先端表面領域にのみ選択的に形成した例を示している。   20A (e) (f) (g) shows an example in which the metal layer 11b is provided in the entire surface area of the electrode 11C used in the embodiment of FIGS. 14 to 18, from the tip surface to a part of the side surface. An example is shown in which it is selectively formed only in the covered region or the tip surface region.

一方、たとえば、図２０Ｂ（ａ）（ｂ）（ｃ）は、各々、金属層２１ｂを、図１〜図６の実施形態で用いられている電極２１Ａの挿入開口部２２を含む表面全領域に設けた例、挿入開口部２２の底面から内壁面を覆う領域または底面領域にのみ選択的に形成した例を示している。   On the other hand, for example, FIGS. 20B (a), 20 (b), and 20 (c) each have the metal layer 21b over the entire surface area including the insertion opening 22 of the electrode 21A used in the embodiment of FIGS. The example which provided, the example selectively formed only in the area | region which covers an inner wall surface from the bottom face of the insertion opening part 22, or a bottom face area | region is shown.

図２０Ｂ（ｄ）（ｅ）（ｆ）は、各々、金属層２１ｂを、図７〜図９の実施形態で用いられている電極２１Ｂの挿入開口部２２を含む表面全領域に設けた例、挿入開口部２２の内面全領域または内面の底部領域にのみ選択的に形成した例を示している。   20B (d), (e), and (f) are examples in which the metal layer 21b is provided over the entire surface area including the insertion opening 22 of the electrode 21B used in the embodiment of FIGS. The example which selectively formed only in the inner surface whole area | region of the insertion opening part 22 or the bottom part area | region of the inner surface is shown.

図２０Ｂ（ｇ）（ｈ）は、金属層２１ｂを、図１１〜図１３の実施形態で用いられている電極２１Ｄの挿入開口部２２を含む表面全領域に設けた例、挿入開口部２２の内面全領域にのみ選択的に形成した例を示している。   20B (g) (h) shows an example in which the metal layer 21b is provided in the entire surface area including the insertion opening 22 of the electrode 21D used in the embodiment of FIGS. An example of selective formation only in the entire inner surface area is shown.

もちろん図示していない他の電極１１，２１にも適用できることは言うまでもない。   Of course, it is needless to say that the present invention can be applied to other electrodes 11 and 21 (not shown).

（その他の実施形態）
本発明は、上記の実施形態の説明に限定されない。 (Other embodiments)
The present invention is not limited to the description of the above embodiment.

例えば、電極１１，２１の材料や製法に限定はなく、種々の公知の材料や製法を採用することが可能である。   For example, the materials and manufacturing methods of the electrodes 11 and 21 are not limited, and various known materials and manufacturing methods can be employed.

また、電極１１，２１の組み合わせについても、上述した各実施形態だけでなく、同様な効果を実現できる限り様々な組み合わせを採用することが可能である。   Further, regarding the combinations of the electrodes 11 and 21, not only the above-described embodiments, but also various combinations can be adopted as long as the same effect can be realized.

なお、上記各実施形態は、半導体チップ１を基板２に搭載させる際の実施形態として半導体チップ１の電極１１と基板２の電極２１について説明しているが、半導体チップ１同士の積層時における電極接続にも応用できることは言うまでもない。この場合、電極１１を上層の半導体チップ１の電極、電極２１を下層の半導体チップ１の電極として採用すればよい。   In addition, although each said embodiment demonstrated the electrode 11 of the semiconductor chip 1 and the electrode 21 of the board | substrate 2 as embodiment at the time of mounting the semiconductor chip 1 in the board | substrate 2, the electrode at the time of lamination | stacking of the semiconductor chips 1 mutually is demonstrated. Needless to say, it can also be applied to connections. In this case, the electrode 11 may be used as the electrode of the upper semiconductor chip 1 and the electrode 21 may be used as the electrode of the lower semiconductor chip 1.

その他、本発明の要旨を逸脱しない範囲で、種々の変更が可能である。   In addition, various modifications can be made without departing from the scope of the present invention.

本発明の第１実施形態を示す断面図である。It is sectional drawing which shows 1st Embodiment of this invention. （ａ）（ｂ）は第１実施形態における電極１１Ａ，２１Ａを示す斜視図である。(A) and (b) are perspective views showing electrodes 11A and 21A in the first embodiment. 第１実施形態を説明するための図である。It is a figure for demonstrating 1st Embodiment. 本発明の第２実施形態を示す断面図である。It is sectional drawing which shows 2nd Embodiment of this invention. （ａ）（ｂ）は第２実施形態における電極１１Ｂ，２１Ａを示す斜視図である。(A) and (b) are perspective views showing electrodes 11B and 21A in the second embodiment. 第２実施形態を説明するための図である。It is a figure for demonstrating 2nd Embodiment. 本発明の第３実施形態を示す断面図である。It is sectional drawing which shows 3rd Embodiment of this invention. （ａ）（ｂ）は第３実施形態における電極１１Ｂ，２１Ｂを示す斜視図である。(A) and (b) are perspective views showing electrodes 11B and 21B in the third embodiment. 第３実施形態を説明するための図である。It is a figure for demonstrating 3rd Embodiment. （ａ）（ｂ）は本発明の第４実施形態における電極２１Ｃの斜視図および電極１１Ｂ，２１Ｃの接合状態を示す断面図である。(A) and (b) are sectional views showing a perspective view of an electrode 21C and a joined state of the electrodes 11B and 21C in the fourth embodiment of the present invention. 本発明の第５実施形態を示す断面図である。It is sectional drawing which shows 5th Embodiment of this invention. （ａ）（ｂ）は第５実施形態における電極１１Ｂ，２１Ｄを示す斜視図である。(A) and (b) are perspective views showing electrodes 11B and 21D in the fifth embodiment. 第５実施形態を説明するための図である。It is a figure for demonstrating 5th Embodiment. （ａ）（ｂ）（ｃ）は本発明の第６実施形態における電極１１Ｃを示す斜視図、電極２１Ｅを示す、および電極１１Ｃ，２１Ｅの接合状態を示す断面図である。(A) (b) (c) is a perspective view showing an electrode 11C in a sixth embodiment of the present invention, showing an electrode 21E, and a cross-sectional view showing a joined state of the electrodes 11C and 21E. 本発明の第７実施形態を示す断面図である。It is sectional drawing which shows 7th Embodiment of this invention. 第７実施形態における電極１１Ｃ，２１Ｂを示す斜視図である。It is a perspective view which shows electrodes 11C and 21B in 7th Embodiment. 第７実施形態を説明するための図である。It is a figure for demonstrating 7th Embodiment. （ａ）（ｂ）（ｃ）は本発明の第８実施形態における電極１１Ｃの斜視図、電極２１Ｂの斜視図、および電極１１Ｃ，２１Ｃの接合状態を示す断面図である。(A), (b), and (c) are a perspective view of an electrode 11C, a perspective view of an electrode 21B, and a sectional view showing a joined state of the electrodes 11C and 21C in an eighth embodiment of the present invention. 本発明の第９実施形態を示す断面図である。It is sectional drawing which shows 9th Embodiment of this invention. （ａ）〜（ｇ）は本発明の第１０実施形態における電極１１のバリエーション例を示す断面図である。(A)-(g) is sectional drawing which shows the example of a variation of the electrode 11 in 10th Embodiment of this invention. （ａ）〜（ｈ）は本発明の第１０実施形態における電極２１のバリエーション例を示す断面図である。(A)-(h) is sectional drawing which shows the example of a variation of the electrode 21 in 10th Embodiment of this invention. 従来の半導体装置の製造方法を説明するための図である。It is a figure for demonstrating the manufacturing method of the conventional semiconductor device.

符号の説明Explanation of symbols

１ 半導体チップ
１０ 電極パッド
１１，１１Ａ−１１Ｄ 電極
１１ａ 金属バルク体
１１ｂ 金属層
１２ 側面
１３ 挿入開口部
２ 基板
２０ 電極パッド
２１，２１Ａ−２１Ｆ 電極
２１ａ 金属バルク体
２１ｂ 金属層
２２ 挿入開口部
１００ 半導体チップ
１０１ 電極パッド
１０２ バンプ
２００ 基板
２０１ 電極パッド
２０２ バンプ
Ｍ１ 半導体チップの中心
Ｍ２ 基板の中心 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 10 Electrode pad 11,11A-11D Electrode 11a Metal bulk body 11b Metal layer 12 Side surface 13 Insertion opening part 2 Substrate 20 Electrode pad 21,21A-21F Electrode 21a Metal bulk body 21b Metal layer 22 Insertion opening part 100 Semiconductor chip 101 Electrode pad 102 Bump 200 Substrate 201 Electrode pad 202 Bump M1 Center of semiconductor chip M2 Center of substrate

Claims (22)

突起状の金属導体からなり、
接続相手である他の電極に設けられた挿入開口部に挿入される際に、挿入開口部の開口縁または内壁面に沿って他の電極の中心に向かう方向に摺動しながら挿入されて、互いの中心位置が揃った状態で他の電極と接続されることを特徴とする電極。 It consists of a protruding metal conductor,
When inserted into the insertion opening provided in the other electrode that is the connection partner, it is inserted while sliding in the direction toward the center of the other electrode along the opening edge or inner wall surface of the insertion opening, An electrode characterized by being connected to another electrode in a state in which the center positions thereof are aligned. 錐体形であることを特徴とする請求項１記載の電極。   2. The electrode according to claim 1, wherein the electrode has a cone shape. 先端部が平坦化された錐体形であることを特徴とする請求項１記載の電極。   2. The electrode according to claim 1, wherein the tip has a flattened cone shape. 柱体形であることを特徴とする請求項１記載の電極。   2. The electrode according to claim 1, wherein the electrode has a columnar shape. 金属バルク体と、金属バルク体の表面に設けられた金属バルク体とは異なる金属層とを有していることを特徴とする請求項１ないし４のいずれかに記載の電極。   The electrode according to any one of claims 1 to 4, comprising a metal bulk body and a metal layer different from the metal bulk body provided on the surface of the metal bulk body. 前記金属層が、前記金属バルク体よりも低融点の金属でなることを特徴とする請求項５記載の電極。   The electrode according to claim 5, wherein the metal layer is made of a metal having a melting point lower than that of the bulk metal. 接続相手である他の電極を挿入する挿入開口部を備え、他の電極を、挿入開口部の開口縁または内壁面に沿って挿入開口部の中心に向かう方向に摺動させながら挿入させて、他の電極と接続することを特徴とする電極。   It is provided with an insertion opening for inserting another electrode as a connection partner, and the other electrode is inserted while sliding in the direction toward the center of the insertion opening along the opening edge or inner wall surface of the insertion opening, An electrode connected to another electrode. ドーナッツ形であることを特徴とする請求項７記載の電極。   The electrode according to claim 7, wherein the electrode has a donut shape. 前記挿入開口部が円柱空洞状であることを特徴とする請求項７または８記載の電極。   The electrode according to claim 7 or 8, wherein the insertion opening has a cylindrical cavity shape. 前記挿入開口部がすり鉢形の窪みであることを特徴とする請求項７記載の電極。   The electrode according to claim 7, wherein the insertion opening is a mortar-shaped depression. 前記挿入開口部が錐体形の窪みであることを特徴とする請求項７記載の電極。   The electrode according to claim 7, wherein the insertion opening is a conical depression. 凸状に形成されていることを特徴とする請求項７ないし１１のいずれかに記載の電極。   12. The electrode according to claim 7, wherein the electrode is formed in a convex shape. 凹状に形成されていることを特徴とする請求項７ないし１１のいずれかに記載の電極。   The electrode according to claim 7, wherein the electrode is formed in a concave shape. 金属バルク体と、金属バルク体の表面に設けられた金属バルク体とは異なる金属層とを有していることを特徴とする請求項７ないし１３のいずれかに記載の電極。   The electrode according to claim 7, comprising a metal bulk body and a metal layer different from the metal bulk body provided on the surface of the metal bulk body. 前記金属層が、前記金属バルク体よりも低融点の金属でなることを特徴とする請求項１４記載の電極。   The electrode according to claim 14, wherein the metal layer is made of a metal having a melting point lower than that of the bulk metal. 請求項１ないし１５のいずれかに記載の電極を備えたことを特徴とする半導体チップ。   A semiconductor chip comprising the electrode according to claim 1. 請求項１ないし１５のいずれかに記載の電極を備えたことを特徴とする基板。   A substrate comprising the electrode according to claim 1. 半導体チップに設けられた請求項１ないし６のいずれかに記載の電極が、基板もしくは他の半導体チップに設けられた請求項７ないし１５のいずれかに記載の電極の挿入開口部に挿入されて、前記電極同士が接続されていることを特徴とする半導体チップの電極接続構造。   The electrode according to any one of claims 1 to 6 provided on a semiconductor chip is inserted into an insertion opening of the electrode according to any one of claims 7 to 15 provided on a substrate or another semiconductor chip. The electrode connection structure of a semiconductor chip, wherein the electrodes are connected to each other. 基板もしくは半導体チップに設けられた請求項１ないし６のいずれかに記載の電極が、他の半導体チップに設けられた請求項７ないし１５のいずれかに記載の電極の挿入開口部に挿入されて、前記電極同士が接続されていることを特徴とする半導体チップの電極接続構造。   The electrode according to any one of claims 1 to 6 provided on a substrate or a semiconductor chip is inserted into an insertion opening of the electrode according to any one of claims 7 to 15 provided on another semiconductor chip. The electrode connection structure of a semiconductor chip, wherein the electrodes are connected to each other. 基板もしくは半導体チップと他の半導体チップの電極同士が接続された半導体装置であって、
前記基板もしくは半導体チップと前記他の半導体チップの電極間において、請求項１８または１９に記載の電極接続構造を有する
ことを特徴とする半導体装置。 A semiconductor device in which electrodes of a substrate or a semiconductor chip and another semiconductor chip are connected to each other,
20. A semiconductor device comprising the electrode connection structure according to claim 18 or 19 between electrodes of the substrate or semiconductor chip and the other semiconductor chip. 半導体チップに設けた請求項１ないし６のいずれかに記載の電極を、基板もしくは他の半導体チップに設けた請求項７ないし１５のいずれかに記載の電極の挿入開口部に挿入して、前記電極同士を接合させることにより、前記半導体チップを前記基板もしくは他の半導体チップ上に搭載することを特徴とする半導体装置の製造方法。   The electrode according to any one of claims 1 to 6 provided on a semiconductor chip is inserted into an insertion opening of the electrode according to any one of claims 7 to 15 provided on a substrate or another semiconductor chip, A method of manufacturing a semiconductor device, wherein the semiconductor chip is mounted on the substrate or another semiconductor chip by bonding electrodes together. 基板もしくは半導体チップに設けた請求項１ないし６のいずれかに記載の電極を、他の半導体チップに設けた請求項７ないし１５のいずれかに記載の電極の挿入開口部に挿入して、前記電極同士を接合させることにより、前記他の半導体チップを前記基板もしくは他の半導体チップ上に搭載することを特徴とする半導体装置の製造方法。
The electrode according to any one of claims 1 to 6 provided on a substrate or a semiconductor chip is inserted into an insertion opening of the electrode according to any one of claims 7 to 15 provided on another semiconductor chip, A method of manufacturing a semiconductor device, wherein the other semiconductor chip is mounted on the substrate or another semiconductor chip by bonding electrodes together.
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