JP2002289653A - Semiconductor device tape carrier and its manufacturing method - Google Patents
Semiconductor device tape carrier and its manufacturing methodInfo
- Publication number
- JP2002289653A JP2002289653A JP2001086913A JP2001086913A JP2002289653A JP 2002289653 A JP2002289653 A JP 2002289653A JP 2001086913 A JP2001086913 A JP 2001086913A JP 2001086913 A JP2001086913 A JP 2001086913A JP 2002289653 A JP2002289653 A JP 2002289653A
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- Prior art keywords
- tin
- copper
- plating
- thickness
- layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、精密電子部品であ
るＴＡＢテープキャリアのような半導体装置用テープキ
ャリア、特にその銅箔の配線パターンにスズめっきを行
うに際し、ソルダーレジスト際の銅の喰われを防止した
構造のテープキャリア及びスズめっき手法に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tape carrier for semiconductor devices such as a TAB tape carrier, which is a precision electronic component, and more particularly, to tin plating on a wiring pattern of a copper foil when copper is solder resisted. And a tin plating method.
【０００２】[0002]
【従来の技術】従来のＴＡＢテープキャリアの構造は、
図２に示すように、ポリイミド樹脂製絶縁フィルム１に
接着剤層２を介して貼り合わせた銅箔に所定の配線パタ
ーン３を形成し（図２（ａ））、その配線パターン３上
には、その銅リード３ａ等の端子部分を除く所定の位置
に、絶縁層としてソルダーレジスト６を印刷塗布し（図
２（ｂ））、その後、当該配線パターン３の端子部分で
ある銅リード３ａに安定した接合性を与えるために、無
電解スズめっきにより純スズめっき層４を形成し（図２
（ｃ））、加熱処理によりスズ−銅合金層５を形成した
構造（図２（ｄ））である。2. Description of the Related Art The structure of a conventional TAB tape carrier is as follows.
As shown in FIG. 2, a predetermined wiring pattern 3 is formed on a copper foil bonded to an insulating film 1 made of a polyimide resin via an adhesive layer 2 (FIG. 2A). Then, a solder resist 6 is printed and applied as an insulating layer at a predetermined position except for the terminal portions such as the copper leads 3a (FIG. 2B). The pure tin plating layer 4 is formed by electroless tin plating in order to provide the improved bonding property.
FIG. 2C shows a structure in which a tin-copper alloy layer 5 is formed by a heat treatment (FIG. 2D).
【０００３】このＴＡＢテープキャリアの半導体素子へ
の実装作業は、例えば図３に示すように半導体素子（Ｉ
Ｃチップ）７をデバイスホールに位置するように配置
し、デバイスホールに突出したインナーリードと半導体
素子７の電極を位置合わせした後、ボンディングツール
により圧着する。半導体素子７の電極には金バンプ８が
形成されており、加熱された状態で銅リード３ａに圧着
されると、スズめっきが溶融し金−スズ合金が形成し、
電極とインナーリードが接合される。[0003] The work of mounting the TAB tape carrier on a semiconductor device is performed, for example, as shown in FIG.
The C chip 7 is arranged so as to be located in the device hole, and the inner lead projecting into the device hole and the electrode of the semiconductor element 7 are aligned, and then pressure-bonded by a bonding tool. Gold bumps 8 are formed on the electrodes of the semiconductor element 7, and when pressed against the copper leads 3a in a heated state, the tin plating melts to form a gold-tin alloy,
The electrode and the inner lead are joined.
【０００４】[0004]
【発明が解決しようとする課題】一般にスズめっきは、
耐食性、はんだ付け性に優れていることから電子部品に
広く使用されている。In general, tin plating is
It is widely used in electronic components because of its excellent corrosion resistance and solderability.
【０００５】しかしながら、上記した従来のＴＡＢテー
プキャリアにおいては、無電解スズめっきする際に、図
４に示すように、ソルダーレジスト６の下方の際部（端
部）にて銅が過剰溶解し、銅リード３ａに溝状に浸食さ
れた部分（過剰溶解部９）を形成し、リード強度を低下
させるという問題がある。However, in the above-described conventional TAB tape carrier, when electroless tin plating is performed, as shown in FIG. 4, copper excessively dissolves at the edge (end) below the solder resist 6, There is a problem in that a groove-eroded portion (excess melting portion 9) is formed in the copper lead 3a and lead strength is reduced.
【０００６】一般に無電解スズめっきは銅との置換で析
出するが、この場合、無電解スズめっきの前処理液がソ
ルダーレジスト下方は浸透しにくく、銅表面に有機物の
残さ、汚染物等が残り、無電解スズめっき時に反応速度
が著しく早くなり、銅が過剰に溶解する。In general, electroless tin plating is precipitated by substitution with copper. In this case, the pretreatment liquid for electroless tin plating hardly penetrates below the solder resist, and organic substances and contaminants remain on the copper surface. At the time of electroless tin plating, the reaction speed is remarkably increased, and copper is excessively dissolved.
【０００７】さらに最近では微細配線パターン化の要求
が強くなっており、めっき面積がより小さくなっている
ことから、めっき面積の大きいところと微細な部分で、
無電解スズめっき時に反応速度に差が生じる。特に、微
細部では無電解スズめっきの反応速度が早くなり、銅が
過剰溶解しリード強度が低下する。[0007] More recently, the demand for fine wiring patterning has become stronger, and the plating area has become smaller.
A difference occurs in the reaction rate during electroless tin plating. In particular, the reaction rate of the electroless tin plating is increased in the fine part, and the copper is excessively dissolved to lower the lead strength.
【０００８】他の問題点として、スズめっき皮膜はスズ
めっき直後、放置するとホイスカ（ひげ状の結晶）が発
生することが良く知られており、特に微細ピッチのパタ
ーンではホイスカの発生がショートの原因となるため、
種々の検討が行われてきた。このスズホイスカの抑制手
段としては、(1) 下地めっきとして、ニッケル、銅、
鉛、はんだ、スズ−ニッケル合金、スズ−銅合金層を形
成する。(2) めっき後にリフロー処理を施す。(3) めっ
き後に加熱してアニール処理を施す。等が知られてい
る。As another problem, it is well known that whiskers (whisker-like crystals) are generated when the tin plating film is left immediately after tin plating, and the generation of whiskers is a cause of short-circuit especially in a fine pitch pattern. Because
Various studies have been made. As means for suppressing tin whiskers, (1) nickel, copper,
Form a lead, solder, tin-nickel alloy, tin-copper alloy layer. (2) Perform reflow treatment after plating. (3) Anneal by heating after plating. Etc. are known.
【０００９】しかしながら、上記(1) の下地めっきを施
す手法は、下地めっき工程が付与されるのでコストが高
くなる。上記(2) のめっき後にリフロー処理を施す方法
は、最初に厚く均一なめっきを施したとしても、リフロ
ー後はめっき厚にバラツキが生じてしまい、さらにスズ
めっき表面が酸化するという問題が生じる。上記(3)の
めっき後にアニール処理を施す方法は、短期間ではホイ
スカ抑制効果があるが、６ケ月程度の長期間になると完
全にホイスカの成長を防止することができないため、完
全なホイスカ対策とはならないという問題がある。However, the method of (1) for applying the base plating increases the cost because the base plating step is provided. In the method (2) of performing reflow treatment after plating, even if thick and uniform plating is performed first, the plating thickness varies after reflow, and furthermore, there arises a problem that the tin plating surface is oxidized. The method of performing the annealing treatment after the plating of the above (3) has an effect of suppressing whiskers in a short period of time, but cannot completely prevent whisker growth in a long period of about 6 months. There is a problem that should not be.
【００１０】そこで、本発明の目的は、上記課題を解決
し、ソルダーレジスト下方のリード配線の銅の過剰溶
解、つまりソルダーレジスト際の銅の喰われを防止する
と共に、安価に、且つスズめっきの特性を損なわずに、
スズめっきのホイスカを抑制することのできる、高い信
頼性を有するスズめっき構造の半導体装置用テープキャ
リアおよびその製造方法を提供することにある。Therefore, an object of the present invention is to solve the above-mentioned problems, to prevent excessive dissolution of copper in the lead wiring below the solder resist, that is, to prevent copper from being eroded at the time of the solder resist, and to reduce the cost of tin plating. Without impairing the characteristics,
An object of the present invention is to provide a highly reliable tin-plated semiconductor device tape carrier capable of suppressing tin-plated whiskers and a method of manufacturing the same.
【００１１】[0011]
【課題を解決するための手段】上記目的を達成するた
め、本発明は、次のように構成したものである。Means for Solving the Problems In order to achieve the above object, the present invention is configured as follows.
【００１２】（１）請求項１の発明に係る半導体装置用
テープキャリアは、絶縁フィルム上に接着剤層を介して
施された銅箔の配線パターン上に、銀、金、パラジウム
等の貴金属めっきを施し、前記配線パターンの端子部分
を除く所定の位置にソルダーレジストを塗布し、前記端
子部分にスズめっき層を形成し加熱処理することによ
り、厚さ０．２０μｍ以上のスズ−銅合金層と厚さ０．
１５〜０．８０μｍの純スズ層を形成したことを特徴と
する。(1) The tape carrier for a semiconductor device according to the first aspect of the present invention is a precious metal plating of silver, gold, palladium or the like on a copper foil wiring pattern provided on an insulating film via an adhesive layer. By applying a solder resist at predetermined positions except for the terminal portion of the wiring pattern, forming a tin plating layer on the terminal portion and performing a heat treatment, thereby forming a tin-copper alloy layer having a thickness of 0.20 μm or more. Thickness 0.
A pure tin layer having a thickness of 15 to 0.80 μm is formed.
【００１３】（２）請求項２の発明は、請求項１記載の
半導体装置用テープキャリアにおいて、前記貴金属めっ
きの厚さを０．１μｍ以下としたことを特徴とする。(2) According to a second aspect of the present invention, in the tape carrier for a semiconductor device according to the first aspect, the thickness of the noble metal plating is 0.1 μm or less.
【００１４】（３）請求項３の発明に係る半導体装置用
テープキャリアの製造方法は、絶縁フィルム上に接着剤
層を介して施された銅箔の配線パターン上に、銀、金、
パラジウム等の貴金属めっきを施した後、前記配線パタ
ーンの端子部分を除く所定の位置にソルダーレジストを
塗布し、その後、前記端子部分にスズめっき層を形成
し、その後、加熱処理することにより、厚さ０．２０μ
ｍ以上のスズ−銅合金層と厚さ０．１５〜０．８０μｍ
の純スズ層を形成することを特徴とする。(3) The method of manufacturing a tape carrier for a semiconductor device according to the third aspect of the present invention is a method for manufacturing a tape carrier for a semiconductor device, wherein silver, gold, silver, gold, or the like is formed on a copper foil wiring pattern provided on an insulating film via an adhesive layer.
After applying a noble metal plating such as palladium, a solder resist is applied to a predetermined position except for the terminal portion of the wiring pattern, and thereafter, a tin plating layer is formed on the terminal portion, and then, a heat treatment is performed. 0.20μ
m or more tin-copper alloy layer and thickness 0.15-0.80 μm
Characterized by forming a pure tin layer of
【００１５】（４）請求項４の発明は、請求項３記載の
製造方法において、前記貴金属めっきの厚さを０．１μ
ｍ以下とすることを特徴とする。(4) The invention according to claim 4 is the manufacturing method according to claim 3, wherein the thickness of the noble metal plating is 0.1 μm.
m or less.
【００１６】（５）請求項３又は４記載の製造方法にお
いて、前記スズめっきを無電解めっきにより行うことを
特徴とする。(5) The manufacturing method according to the third or fourth aspect, wherein the tin plating is performed by electroless plating.
【００１７】[0017]
【発明の実施の形態】以下、本発明を図示の実施形態に
基づいて説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on the illustrated embodiment.
【００１８】図１に本発明による半導体装置用テープキ
ャリアの例としてのＴＡＢテープキャリアの製造方法を
示す。まず、ポリイミド樹脂製絶縁フィルム１上に接着
剤層２を介して銅箔を形成したテープキャリアに、所定
のフォトレジストを塗布して乾燥させた後に、所定の配
線リードパターンを有するフォトマスクを通して露光、
現像させた後、エッチングを行うことにより、図１
（ａ）に示すように所定の微細配線パターン３を作製す
る。FIG. 1 shows a method of manufacturing a TAB tape carrier as an example of a tape carrier for a semiconductor device according to the present invention. First, a predetermined photoresist is applied to a tape carrier on which a copper foil is formed on a polyimide resin insulating film 1 via an adhesive layer 2 and dried, and then exposed through a photomask having a predetermined wiring lead pattern. ,
After the development, etching is performed to obtain FIG.
A predetermined fine wiring pattern 3 is formed as shown in FIG.
【００１９】次に、図１（ｂ）に示すように、この銅箔
の配線パターン３上に、厚さ０．０１〜０．１μｍの
銀、金、パラジウム等の貴金属めっき層１０を形成す
る。Next, as shown in FIG. 1B, a noble metal plating layer 10 of silver, gold, palladium or the like having a thickness of 0.01 to 0.1 μm is formed on the wiring pattern 3 of the copper foil. .
【００２０】次いで、図１（ｃ）に示すように、この貴
金属めっき層１０が形成された配線パターン３上の一部
分に、つまり銅リード３ａ等の端子部分を除いた所定の
位置に、ソルダーレジスト６を印刷法により塗布する。Next, as shown in FIG. 1C, a solder resist is provided on a part of the wiring pattern 3 where the noble metal plating layer 10 is formed, that is, at a predetermined position excluding the terminal parts such as the copper leads 3a. 6 is applied by a printing method.
【００２１】次に、図１（ｄ）に示すように、このテー
プキャリアの上記端子部分（銅リード３ａ等）に、つま
り貴金属めっき層１０上に、スズめっき層４を形成し、
その後、１００〜１５０℃、５分〜９０分の加熱処理を
することにより、当該スズめっき層に銅を拡散して、図
１（ｅ）に示すように、厚さ０．１５〜０．８０μｍの
実質的に銅を含有しないスズめっき層すなわち純スズ層
４と、厚さ０．２０μｍ以上の銅拡散スズめっき層すな
わちスズ−銅合金層５を形成する。Next, as shown in FIG. 1D, a tin plating layer 4 is formed on the terminal portion (copper lead 3a or the like) of the tape carrier, that is, on the noble metal plating layer 10.
Thereafter, by performing a heat treatment at 100 to 150 ° C. for 5 to 90 minutes, copper is diffused in the tin plating layer, and as shown in FIG. 1 (e), a thickness of 0.15 to 0.80 μm Of a tin-plated layer substantially free of copper, that is, a pure tin layer 4 and a copper-diffused tin-plated layer having a thickness of 0.20 μm or more, that is, a tin-copper alloy layer 5.
【００２２】このようにして形成されるＴＡＢテープキ
ャリアは、先に銀、金、パラジウム等の貴金属めっき層
１０が形成され、この貴金属めっき層１０により銅リー
ド３ａ等の端子部分が覆われ、その上にソルダーレジス
ト６が形成される。このため、スズめっき処理の際に、
ソルダーレジスト６の下面にめっき液が侵入したとして
も、銅の表面は貴金属めっき層１０に覆われていて、銅
箔がめっき液と接触することはないので、局部的な電食
が起こらない。従って、図４に示した銅の過剰溶解部９
が銅リード３ａに形成されることがない。よって、銅リ
ード３ａに銅の過剰溶解部９が存在して銅リード３ａの
強度が弱まるという不都合を無くすことができる。In the TAB tape carrier thus formed, a noble metal plating layer 10 of silver, gold, palladium or the like is formed first, and the noble metal plating layer 10 covers terminal portions such as the copper leads 3a. A solder resist 6 is formed thereon. For this reason, during tin plating,
Even if the plating solution enters the lower surface of the solder resist 6, the copper surface is covered with the noble metal plating layer 10, and the copper foil does not come into contact with the plating solution, so that local electrolytic corrosion does not occur. Therefore, the copper excessive melting portion 9 shown in FIG.
Is not formed on the copper lead 3a. Therefore, it is possible to eliminate the inconvenience that the copper lead 3a has the excessively melted copper 9 and the strength of the copper lead 3a is reduced.
【００２３】上記したＴＡＢテープキャリアの製造方法
において、貴金属めっき層１０の厚さは０．１μｍ以下
であることが好ましい。この貴金属めっき層１０の厚さ
が０．１μｍを越えると、無電解スズめっき時に貴金属
めっき皮膜のピンホールを通じて析出する際に、ほぼ全
面が貴金属めっきで覆われてしまし、無電解スズめっき
液がピンホールを通じて下地の銅まで達するまでに時間
がかかり、析出速度が低下するからである。In the above-described method for producing a TAB tape carrier, the thickness of the noble metal plating layer 10 is preferably 0.1 μm or less. If the thickness of the noble metal plating layer 10 exceeds 0.1 μm, almost all of the surface of the noble metal plating film is covered with the noble metal plating when depositing through the pinholes of the noble metal plating film during electroless tin plating. This is because it takes time to reach the underlying copper through the pinhole, and the deposition rate decreases.
【００２４】一方、純スズ層４の厚さを０．１５〜０．
８０μｍとした理由は、０．１５μｍ未満の場合はイン
ナリードのボンディング性が困難となり、０．８μｍを
越えるとめっきだれを生じ、短絡の原因となるからであ
る。また、２回目のスズめっき処理によるスズ−銅合金
層５の厚さを０．２０μｍ以上とした理由は、０．２０
μｍ未満の場合はホイスカ抑制効果が不十分となるから
である。On the other hand, the thickness of the pure tin layer 4 is set to 0.15 to 0.5.
The reason why the thickness is set to 80 μm is that if the thickness is less than 0.15 μm, the bonding property of the inner lead becomes difficult, and if it exceeds 0.8 μm, the plating may be dripped and cause a short circuit. The reason for setting the thickness of the tin-copper alloy layer 5 to 0.20 μm or more by the second tin plating treatment is as follows:
If it is less than μm, the effect of suppressing whiskers will be insufficient.
【００２５】上記ＴＡＢテープキャリアの半導体素子へ
の実装作業は、例えば図３に示すように半導体素子（Ｉ
Ｃチップ）７をデバイスホールに位置するように配置
し、デバイスホールに突出したインナーリードと半導体
素子７の電極を位置合わせした後、ボンディングツール
により圧着する。半導体素子７の電極には金バンプ８が
形成されており、加熱された状態で銅リード３ａに圧着
されると、スズめっきが溶融し金−スズ合金が形成し、
電極とインナーリードが強固に接合される。The work of mounting the TAB tape carrier on a semiconductor device is performed, for example, as shown in FIG.
The C chip 7 is arranged so as to be located in the device hole, and the inner lead projecting into the device hole and the electrode of the semiconductor element 7 are aligned, and then pressure-bonded by a bonding tool. Gold bumps 8 are formed on the electrodes of the semiconductor element 7, and when pressed against the copper leads 3a in a heated state, the tin plating melts to form a gold-tin alloy,
The electrode and the inner lead are firmly joined.
【００２６】[0026]
【実施例】ポリイミド樹脂製絶縁フィルム１上に接着剤
層２を介して形成された銅箔２５μｍのテープキャリア
に、所定のレジストを塗布して乾燥させた後に、所定の
配線リードパターンを有するフォトマスクを通して露
光、現像させた後、エッチングを行うことによりリード
パターンを作製した。DESCRIPTION OF THE PREFERRED EMBODIMENTS A predetermined resist is applied to a tape carrier of 25 μm copper foil formed on a polyimide resin insulating film 1 via an adhesive layer 2 and dried, and then a photo having a predetermined wiring lead pattern is formed. After exposure and development through a mask, etching was performed to produce a lead pattern.
【００２７】そして、まず、ポリイミド樹脂製絶縁フィ
ルム１上に銅の微細パターンが形成された半導体装置用
テープキャリアの銅配線パターン上に、厚さ０．０１〜
０．２５μｍの銀めっきを施し、その配線パターン上の
一部分にソルダーレジスト６を印刷した後、約０．５μ
ｍのスズめっき層を形成し、１００℃〜１５０℃で５分
〜９０分加熱処理により、純スズ層４とスズ−銅合金層
５を形成した。ここでは、加熱処理により純スズ層４を
０．２〜０．３μｍ、スズ−銅合金層５を０．１５〜
０．２０μｍ形成させたものを作製した。First, a copper wiring pattern of a semiconductor device tape carrier in which a fine copper pattern is formed on an insulating film 1 made of a polyimide resin has a thickness of 0.01 to 0.01 mm.
After applying a silver plating of 0.25 μm and printing a solder resist 6 on a part of the wiring pattern, about 0.5 μm
m, a pure tin layer 4 and a tin-copper alloy layer 5 were formed by heat treatment at 100 ° C. to 150 ° C. for 5 minutes to 90 minutes. Here, the pure tin layer 4 is heated to 0.2 to 0.3 μm and the tin-copper alloy layer 5 is heated to
One having a thickness of 0.20 μm was produced.
【００２８】ここでスズめっきは電解及び無電解めっき
のいずれかの方法で形成しても良いが、めっき厚のバラ
ツキの少ない点で無電解めっきとした。Here, the tin plating may be formed by any of electrolytic and electroless plating methods, but the electroless plating is used because the plating thickness does not vary greatly.
【００２９】無電解スズめっき液は石原薬品製５８０Ｍ
を用い、７０℃、５〜５００ｓで処理した。このように
作製したサンプルについて、銅の過剰溶解性の評価を断
面観察にて行った。この結果を、表１にスズめっき条件
と銅過剰溶解性評価結果として示す。The electroless tin plating solution is 580M manufactured by Ishihara Chemical Co., Ltd.
And treated at 70 ° C. for 5 to 500 s. With respect to the sample thus produced, the excess solubility of copper was evaluated by cross-sectional observation. The results are shown in Table 1 as tin plating conditions and copper excess solubility evaluation results.
【００３０】[0030]
【表１】 [Table 1]
【００３１】表１から判るように、下地にＡｇめっきを
行ったいずれのサンプルも、銅の過剰溶解は観察されな
かった。すなわち、銀めっき層（貴金属めっき層１０）
の厚さは、少なくとも０．０１μｍ以上であれば、銅の
過剰溶解が防止できるものと考えられる。また銀めっき
厚さが０．１μｍを越えるとスズめっきの析出速度が低
下するので、銀めっき厚さは０．１μｍ以下が好まし
い。As can be seen from Table 1, no excessive dissolution of copper was observed in any of the samples in which the underlayer was plated with Ag. That is, the silver plating layer (noble metal plating layer 10)
It is considered that if the thickness is at least 0.01 μm, excessive dissolution of copper can be prevented. If the silver plating thickness exceeds 0.1 μm, the deposition rate of tin plating decreases, so the silver plating thickness is preferably 0.1 μm or less.
【００３２】一方、サンプル１のようにソルダーレジス
ト印刷後に無電解スズめっきをしただけの場合には、銅
の過剰溶解が観察された。On the other hand, when only the electroless tin plating was performed after the solder resist printing as in Sample 1, excessive dissolution of copper was observed.
【００３３】次に、コクール計により純スズめっき厚、
蛍光Ｘ線膜厚計により全スズ厚を測定し、（全スズ厚）
から（純スズ厚）を差し引きしてスズ−銅合金層の層厚
を求め、１〜６月（３０日、６０日、９０日、１８０
日）放置した後のインナリード１５０本について、それ
ぞれ２００倍の光学顕微鏡によりホイスカの観察を行
い、そのホイスカの発生数を数えた。このスズめっき条
件とスズめっき厚、ホイスカ性評価結果を表２に示す。
表２から判るように、スズ−銅合金層が０．２０μｍ未
満（サンプル２、５、８、１１、１４）の場合、経過日
数が増加するにつれてホイスカ発生数が増加することが
観察された。これによりスズ−銅の拡散層が厚いほどス
ズのホイスカを抑制する効果があることが判る。Next, the thickness of the pure tin plating was
Measure the total tin thickness with a fluorescent X-ray film thickness meter, (total tin thickness)
(Pure tin thickness) is subtracted from the above to determine the thickness of the tin-copper alloy layer, and from January to June (30 days, 60 days, 90 days, 180 days)
Day) The whiskers were observed for each of the 150 inner leads after standing by using an optical microscope of 200 times, and the number of whiskers generated was counted. Table 2 shows the tin plating conditions, tin plating thickness and whisker evaluation results.
As can be seen from Table 2, when the tin-copper alloy layer was less than 0.20 μm (samples 2, 5, 8, 11, and 14), it was observed that the number of whiskers generated increased as the number of elapsed days increased. This shows that the thicker the tin-copper diffusion layer is, the more effective it is to suppress tin whiskers.
【００３４】[0034]
【表２】 [Table 2]
【００３５】上記実施例では銅箔２５μｍのテープキャ
リアを用いたが、これに代えて銅箔１０μｍのテープキ
ャリアで上記と同様な評価を行ったところ、１回目の銀
めき厚さが０．１０μｍ以下では銅の過剰溶解現象は発
生しなかった。In the above embodiment, a tape carrier having a copper foil of 25 μm was used. However, a tape carrier having a copper foil of 10 μm was used in the same evaluation as described above, and the first silvering thickness was 0.10 μm. In the following, the excessive dissolution phenomenon of copper did not occur.
【００３６】また、上記実施例と同様に下地めっきに金
又はパラジウムめっきを同様に施してから評価を行った
ところ、上記実施例の表１、表２と同様な結果を得た。In addition, as in the case of the above example, the undercoat was plated with gold or palladium in the same manner, and the evaluation was performed. As a result, the same results as those in Tables 1 and 2 of the above example were obtained.
【００３７】[0037]
【発明の効果】以上説明したように本発明によれば、次
のような優れた効果が得られる。As described above, according to the present invention, the following excellent effects can be obtained.
【００３８】本発明の半導体装置用テープキャリア及び
その製造方法によれば、絶縁フィルム上に接着剤層を介
して施された銅箔の配線パターン上に、銀、金、パラジ
ウム等の貴金属めっきを施した後、前記配線パターンの
端子部分を除く所定の位置にソルダーレジストを塗布
し、その後、前記端子部分にスズめっき層を形成し、そ
の後、加熱処理することにより、厚さ０．２０μｍ以上
のスズ−銅合金層と厚さ０．１５〜０．８０μｍの純ス
ズ層を形成する。According to the tape carrier for a semiconductor device and the method of manufacturing the same of the present invention, a noble metal plating such as silver, gold, palladium or the like is formed on a copper foil wiring pattern provided on an insulating film via an adhesive layer. After the application, a solder resist is applied to a predetermined position excluding the terminal portion of the wiring pattern, and thereafter, a tin plating layer is formed on the terminal portion, and thereafter, a heat treatment is performed to obtain a thickness of 0.20 μm or more. A tin-copper alloy layer and a pure tin layer having a thickness of 0.15 to 0.80 μm are formed.
【００３９】先に銀、金、パラジウム等の貴金属めっき
層が形成され、この貴金属めっき層により銅リード等の
端子部分が覆われ、その貴金属めっき層上の一部にソル
ダーレジストが形成される。このため、スズめっき処理
の際に、ソルダーレジストの下面にめっき液が侵入した
としても、銅の表面は貴金属めっき層に覆われていて、
銅箔がめっき液と接触することはないので、局部的な電
食が起こらない。従って、銅の過剰溶解部が銅リードに
形成されることがない。よって、銅リードに銅の過剰溶
解部が存在して銅リードの強度が弱まるという不都合を
無くすことができる。First, a noble metal plating layer of silver, gold, palladium or the like is formed, the terminal portion such as a copper lead is covered with the noble metal plating layer, and a solder resist is formed on a part of the noble metal plating layer. For this reason, even if the plating solution enters the lower surface of the solder resist during the tin plating process, the copper surface is covered with the noble metal plating layer,
Since the copper foil does not come into contact with the plating solution, local electrolytic corrosion does not occur. Therefore, an excessive melting portion of copper is not formed on the copper lead. Therefore, it is possible to eliminate the disadvantage that the copper lead has an excessively dissolved portion of copper and the strength of the copper lead is weakened.
【００４０】更に、２回目のスズめっき処理において
は、純スズ層を０．１５〜０．８０μｍとしているの
で、インナリードのボンディング性が良好であり、且つ
めっきだれを生じない。また２回目のスズ−銅合金層を
０．２０μｍ以上としているので、十分なホイスカ抑制
効果を得ることができる。Further, in the second tin plating treatment, since the pure tin layer has a thickness of 0.15 to 0.80 μm, the bonding property of the inner lead is good and no plating dripping occurs. Further, since the second tin-copper alloy layer has a thickness of 0.20 μm or more, a sufficient whisker suppression effect can be obtained.
【図１】本発明のテープキャリアの構造を工程毎に示し
た断面図である。FIG. 1 is a sectional view showing the structure of a tape carrier of the present invention for each process.
【図２】従来のテープキャリアの構造を工程毎に示した
断面図である。FIG. 2 is a sectional view showing the structure of a conventional tape carrier for each process.
【図３】本発明のテープキャリアにＩＣチップを搭載し
て半導体装置を構成した組立図である。FIG. 3 is an assembly diagram in which a semiconductor device is configured by mounting an IC chip on the tape carrier of the present invention.
【図４】銅の過剰溶解現象を示した断面図である。FIG. 4 is a cross-sectional view showing the phenomenon of excessive dissolution of copper.
１ ポリイミド樹脂製絶縁フィルム ２ 接着剤層 ３ 配線パターン ３ａ 銅リード ４ 純スズめっき層 ５ スズ−銅合金層 ６ ソルダーレジスト ９ 銅の過剰溶解部 １０ 貴金属めっき層 DESCRIPTION OF SYMBOLS 1 Insulating film made of polyimide resin 2 Adhesive layer 3 Wiring pattern 3a Copper lead 4 Pure tin plating layer 5 Tin-copper alloy layer 6 Solder resist 9 Excessive dissolution part of copper 10 Precious metal plating layer
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｃ２３Ｃ 30/00 Ｃ２３Ｃ 30/00 Ｅ (72)発明者 菅野 優 茨城県日立市助川町３丁目１番１号 日立 電線株式会社電線工場内 Ｆターム(参考） 4K022 AA15 AA31 AA41 BA01 BA03 BA21 BA35 BA36 DA04 EA01 4K044 AA16 AB02 BA08 BA10 BB03 BB10 BC02 CA15 CA62 5F044 MM03 MM23 MM25 MM48 ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) C23C 30/00 C23C 30/00 E (72) Inventor Yu Sugano 3-1-1 Sukekawacho, Hitachi City, Ibaraki Prefecture No. Hitachi Cable Co., Ltd. F term in the wire plant (reference) 4K022 AA15 AA31 AA41 BA01 BA03 BA21 BA35 BA36 DA04 EA01 4K044 AA16 AB02 BA08 BA10 BB03 BB10 BC02 CA15 CA62 5F044 MM03 MM23 MM25 MM48
Claims (5)
た銅箔の配線パターン上に、銀、金、パラジウム等の貴
金属めっきを施し、 前記配線パターンの端子部分を除く所定の位置にソルダ
ーレジストを塗布し、 前記端子部分にスズめっき層を形成し加熱処理すること
により、厚さ０．２０μｍ以上のスズ−銅合金層と厚さ
０．１５〜０．８０μｍの純スズ層を形成したことを特
徴とする半導体装置用テープキャリア。1. A noble metal plating such as silver, gold, or palladium is applied to a wiring pattern of a copper foil provided on an insulating film via an adhesive layer, and the wiring pattern is provided at a predetermined position excluding a terminal portion. By applying a solder resist, forming a tin plating layer on the terminal portion and performing a heat treatment, a tin-copper alloy layer having a thickness of 0.20 μm or more and a pure tin layer having a thickness of 0.15 to 0.80 μm are formed. A tape carrier for a semiconductor device, comprising:
アにおいて、前記貴金属めっきの厚さを０．１μｍ以下
としたことを特徴とする請求項１記載の半導体装置用テ
ープキャリア。2. The tape carrier for a semiconductor device according to claim 1, wherein said noble metal plating has a thickness of 0.1 μm or less.
た銅箔の配線パターン上に、銀、金、パラジウム等の貴
金属めっきを施した後、 前記配線パターンの端子部分を除く所定の位置にソルダ
ーレジストを塗布し、 その後、前記端子部分にスズめっき層を形成し、その
後、加熱処理することにより、厚さ０．２０μｍ以上の
スズ−銅合金層と厚さ０．１５〜０．８０μｍの純スズ
層を形成することを特徴とする半導体装置用テープキャ
リアの製造方法。3. After a noble metal plating of silver, gold, palladium or the like is applied on a wiring pattern of a copper foil applied on an insulating film via an adhesive layer, a predetermined portion excluding a terminal portion of the wiring pattern is formed. A solder resist is applied to the position, and then a tin plating layer is formed on the terminal portion, and then a heat treatment is performed to form a tin-copper alloy layer having a thickness of 0.20 μm or more and a thickness of 0.15 to 0.1. A method for manufacturing a tape carrier for a semiconductor device, comprising forming a pure tin layer of 80 μm.
金属めっきの厚さを０．１μｍ以下とすることを特徴と
する半導体装置用テープキャリアの製造方法。4. The method according to claim 3, wherein the thickness of the noble metal plating is 0.1 μm or less.
前記スズめっきを無電解めっきにより行うことを特徴と
する半導体装置用テープキャリアの製造方法。5. The method according to claim 3, wherein
A method for producing a tape carrier for a semiconductor device, wherein the tin plating is performed by electroless plating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001086913A JP2002289653A (en) | 2001-03-26 | 2001-03-26 | Semiconductor device tape carrier and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001086913A JP2002289653A (en) | 2001-03-26 | 2001-03-26 | Semiconductor device tape carrier and its manufacturing method |
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| Publication Number | Publication Date |
|---|---|
| JP2002289653A true JP2002289653A (en) | 2002-10-04 |
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ID=18942224
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7180006B2 (en) | 2002-12-02 | 2007-02-20 | Lg Electronics Inc. | Tape substrate and method for fabricating the same |
| KR100712669B1 (en) * | 2005-06-11 | 2007-05-02 | 에스피텍 주식회사 | SURFACE PROCESS METHOD FOR PREVENTION WHISKER USING Ag UNDER PLATING |
| KR100769966B1 (en) | 2006-09-28 | 2007-10-25 | 에스피텍 주식회사 | Surface treatmemt method for preventing whisker of semiconductor lead frame |
| US7396596B2 (en) | 2004-06-23 | 2008-07-08 | Ormecon Gmbh | Article with a coating of electrically conductive polymer |
| US7547479B2 (en) * | 2004-06-25 | 2009-06-16 | Ormecon Gmbh | Tin-coated printed circuit boards with low tendency to whisker formation |
| US7947199B2 (en) | 2005-03-02 | 2011-05-24 | Ormecon Gmbh | Conductive polymers consisting of anisotropic morphology particles |
| US7989533B2 (en) | 2005-08-19 | 2011-08-02 | Ormecon Gmbh | Chemical compound comprising an indium-containing intrinsically conductive polymer |
| US8153271B2 (en) | 2006-09-13 | 2012-04-10 | Ormecon Gmbh | Article with a coating of electrically conductive polymer and precious/semiprecious metal and process for production thereof |
| US8344062B2 (en) | 2004-01-23 | 2013-01-01 | Ormecon Gmbh | Dispersions of intrinsically conductive polymers |
| JP2020172683A (en) * | 2019-04-10 | 2020-10-22 | 上村工業株式会社 | Gold plating method and plated film |
-
2001
- 2001-03-26 JP JP2001086913A patent/JP2002289653A/en not_active Withdrawn
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7180006B2 (en) | 2002-12-02 | 2007-02-20 | Lg Electronics Inc. | Tape substrate and method for fabricating the same |
| US7255802B2 (en) * | 2002-12-02 | 2007-08-14 | Lg Electronics Inc. | Tape substrate and method for fabricating the same |
| US8344062B2 (en) | 2004-01-23 | 2013-01-01 | Ormecon Gmbh | Dispersions of intrinsically conductive polymers |
| US7396596B2 (en) | 2004-06-23 | 2008-07-08 | Ormecon Gmbh | Article with a coating of electrically conductive polymer |
| US7547479B2 (en) * | 2004-06-25 | 2009-06-16 | Ormecon Gmbh | Tin-coated printed circuit boards with low tendency to whisker formation |
| US7947199B2 (en) | 2005-03-02 | 2011-05-24 | Ormecon Gmbh | Conductive polymers consisting of anisotropic morphology particles |
| KR100712669B1 (en) * | 2005-06-11 | 2007-05-02 | 에스피텍 주식회사 | SURFACE PROCESS METHOD FOR PREVENTION WHISKER USING Ag UNDER PLATING |
| US7989533B2 (en) | 2005-08-19 | 2011-08-02 | Ormecon Gmbh | Chemical compound comprising an indium-containing intrinsically conductive polymer |
| US8153271B2 (en) | 2006-09-13 | 2012-04-10 | Ormecon Gmbh | Article with a coating of electrically conductive polymer and precious/semiprecious metal and process for production thereof |
| KR100769966B1 (en) | 2006-09-28 | 2007-10-25 | 에스피텍 주식회사 | Surface treatmemt method for preventing whisker of semiconductor lead frame |
| JP2020172683A (en) * | 2019-04-10 | 2020-10-22 | 上村工業株式会社 | Gold plating method and plated film |
| JP7285123B2 (en) | 2019-04-10 | 2023-06-01 | 上村工業株式会社 | Gold plating method and plating film |
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