JP2002246744A - Conductor-forming method, and multilayer wiring board manufacturing method using the same - Google Patents
Conductor-forming method, and multilayer wiring board manufacturing method using the sameInfo
- Publication number
- JP2002246744A JP2002246744A JP2001043792A JP2001043792A JP2002246744A JP 2002246744 A JP2002246744 A JP 2002246744A JP 2001043792 A JP2001043792 A JP 2001043792A JP 2001043792 A JP2001043792 A JP 2001043792A JP 2002246744 A JP2002246744 A JP 2002246744A
- Authority
- JP
- Japan
- Prior art keywords
- forming
- layer
- insulating layer
- substrate
- conductive pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は配線パターン等の導
体を形成する方法に関し、特に半導体素子の高密度実装
に適した高信頼性を有する多層配線基板を製造するのに
好適な方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a conductor such as a wiring pattern, and more particularly to a method suitable for manufacturing a highly reliable multilayer wiring board suitable for high-density mounting of semiconductor elements.
【０００２】[0002]
【従来の技術】従来の導体配線および多層配線基板形成
法としては、例として特開平１０−５１１０５号公報に
示されているような、基板もしくは樹脂上に形成されて
いる銅箔をエッチングすることで導体を形成し、積層す
るサブトラクティブ法と、無電解めっきや電解めっきを
用いてレジストパターン内に導体形成するアディティブ
法が知られ、行われている。また、アディティブ法にお
いては、特開平９−０６４４９３号公報に示されている
ような、給電層を形成した後にレジスト内に電解めっき
で導体形成し、レジストを除去後に給電層をエッチング
して配線パターンとして積層するセミアディティブ法
と、特開平６−３３４３３４号公報に示されているよう
な、基板もしくは樹脂表面を活性化した後にレジストで
パターンを形成し、このレジストを絶縁層として無電解
めっきにより導体形成し積層するフルアディティブ法が
ある。また、特開２０００−１６５０４９号公報には、
レーザ法を用いてビアホールおよび配線を形成した後、
全面めっきを行い研磨で仕上げる製造方法が提示されて
いる。2. Description of the Related Art A conventional method for forming a conductor wiring and a multilayer wiring board is to etch a copper foil formed on a board or a resin as disclosed in Japanese Patent Application Laid-Open No. 10-51105. A subtractive method of forming and laminating a conductor by using a subtractive method and an additive method of forming a conductor in a resist pattern using electroless plating or electrolytic plating are known and practiced. In the additive method, as described in JP-A-9-064493, a conductor is formed in a resist by electrolytic plating after forming a power supply layer, and after removing the resist, the power supply layer is etched to form a wiring pattern. And a pattern formed with a resist after activating a substrate or a resin surface as disclosed in JP-A-6-334334, and using the resist as an insulating layer by electroless plating. There is a full additive method of forming and laminating. Also, JP-A-2000-165049 discloses that
After forming via holes and wiring using the laser method,
There has been proposed a manufacturing method in which the entire surface is plated and finished by polishing.
【０００３】[0003]
【発明が解決しようとする課題】上述した配線形成法の
うち、銅箔をエッチングすることにより導体を形成する
サブトラクティブ法と電解めっきにより導体を形成した
後にレジストを除去して形成するセミアディティブ法の
いずれにおいても、層間を接続しているビアがすり鉢型
になっているために接続信頼性や、ビアの直上にさらに
ビアを形成することができない欠点が存在している。ま
た、導体パターンが基板や絶縁樹脂の上部に突出してい
ることから、その上に絶縁層を形成し、さらに導体パタ
ーンを形成して多層配線とする際、絶縁層を薄くするこ
とや配線段差をなくした平滑な状態を実現することが困
難である。Among the above-mentioned wiring forming methods, a subtractive method in which a conductor is formed by etching a copper foil and a semi-additive method in which a resist is removed after forming a conductor by electrolytic plating and then removed. In any of the above, there are disadvantages in that the vias connecting the layers are in a mortar shape, so that connection reliability and that no vias can be formed directly above the vias are present. In addition, since the conductor pattern protrudes above the substrate or the insulating resin, when an insulating layer is formed thereon and then a conductor pattern is formed to form multilayer wiring, the insulating layer can be made thinner and the wiring steps can be reduced. It is difficult to realize a lost smooth state.
【０００４】また、無電解めっきにより導体部を形成す
るフルアディティブ法においては、レジストパターンの
厚さと導体部の厚さを揃えることが容易であるため、配
線段差のない平滑な状態とすることができる。しかし、
基板や絶縁樹脂上に触媒を吸着させたあとにレジストパ
ターンを形成するために、レジストの現像工程により触
媒が除去されてしまいめっきの不析出による断線、ある
いは下地との密着低下を引き起こす問題点がある。ま
た、導体パターンを形成しないところにも触媒が残るた
めに、金属イオンのマイグレーションが起こりやすく絶
縁信頼性が低下する問題もある。これらの傾向は微細配
線形成において特に顕著になる。In the full additive method of forming a conductor by electroless plating, it is easy to make the thickness of the resist pattern and the thickness of the conductor easy, so that a smooth state without wiring steps is required. it can. But,
In order to form a resist pattern after the catalyst is adsorbed on the substrate or insulating resin, the catalyst is removed by the resist development process, causing problems such as disconnection due to non-precipitation of plating or reduction in adhesion to the base. is there. In addition, since the catalyst remains even where no conductor pattern is formed, migration of metal ions is likely to occur and insulation reliability is reduced. These tendencies become particularly noticeable in the formation of fine wiring.
【０００５】特開２０００−１６５０４９号公報では、
パターンすべてをレーザ法により形成しているが、この
方法では各層ごとのパターンを直接描画することとなる
ため、スループットが悪くかつ微細パターンに対応しき
れない課題がある。つまり、加工に用いるレーザ光の波
長の関係から、２０μm以下の微細なパターンに十分対
応できなくなる。さらに、通常の電解めっきでは溝部の
深さに対応した厚さのめっき金属が不要部分に析出して
しまい、次工程の研磨による切削量が多くなってしまう
欠点を有している。特に、めっき金属として銅や金を用
いる場合は、研磨時の金属の伸びが大きいため、研磨量
が多い場合は加工性が悪くなる。本発明はこれらの問題
点の少なくとも１つを解決することを目的とする。In Japanese Patent Application Laid-Open No. 2000-165049,
All the patterns are formed by the laser method. However, in this method, since the pattern for each layer is directly drawn, there is a problem that the throughput is poor and it is difficult to cope with a fine pattern. That is, due to the relationship of the wavelength of the laser beam used for processing, it is not possible to sufficiently cope with a fine pattern of 20 μm or less. Further, in the usual electrolytic plating, a plating metal having a thickness corresponding to the depth of the groove portion is deposited on an unnecessary portion, so that there is a disadvantage that the amount of cutting by polishing in the next step increases. In particular, when copper or gold is used as the plating metal, the metal elongation during polishing is large, so that when the polishing amount is large, the workability deteriorates. The present invention aims to solve at least one of these problems.
【０００６】[0006]
【課題を解決するための手段】上記課題を解決するため
に本発明の第１の導体形成方法は、絶縁基板上に、導体
パターンに対応する凹部を有する導体パターン形成用絶
縁層を形成する工程と、前記導体パターン形成用絶縁層
が形成された前記基板上に電解めっき用の給電層を形成
する工程と、前記給電層が形成された前記基板上に、前
記凹部が埋まる厚みまで周期的逆電流パルスめっきを行
って電解めっき層を形成する工程と、前記電解めっき層
形成後、前記導体パターン形成用絶縁層が露出するまで
切削する工程とを含むことを特徴とする。本発明の第２
の導体形成方法は、絶縁基板上に、導体パターンに対応
する凹部を有する導体パターン形成用絶縁層を形成する
工程と、前記導体パターン形成用絶縁層が形成された前
記基板上に無電解めっき用の触媒層を形成する工程と、
前記触媒層が形成された前記基板上に、前記凹部が埋ま
る厚みまで無電解めっきを行って無電解めっき層を形成
する工程と、前記無電解めっき層形成後、前記導体パタ
ーン形成用絶縁層が露出するまで切削する工程とを含む
ことを特徴とする。In order to solve the above-mentioned problems, a first conductor forming method of the present invention is a step of forming a conductor pattern forming insulating layer having a concave portion corresponding to a conductor pattern on an insulating substrate. Forming a power supply layer for electrolytic plating on the substrate on which the conductor pattern forming insulating layer is formed, and periodically reversing the thickness on the substrate on which the power supply layer is formed until the recess is filled. The method includes a step of forming an electrolytic plating layer by performing current pulse plating, and a step of cutting until the insulating layer for forming a conductor pattern is exposed after the formation of the electrolytic plating layer. Second embodiment of the present invention
Forming a conductive pattern forming insulating layer having a concave portion corresponding to a conductive pattern on an insulating substrate; and forming an electroless plating layer on the substrate on which the conductive pattern forming insulating layer is formed. Forming a catalyst layer of
On the substrate on which the catalyst layer is formed, a step of forming an electroless plating layer by performing electroless plating until the recesses are filled, and after forming the electroless plating layer, the insulating layer for forming a conductor pattern is Cutting until exposed.
【０００７】本発明の第３の導体形成方法は、絶縁基板
上に配線パターンを形成する工程と、前記配線パターン
が形成された前記基板上にビアホール形成用絶縁層を形
成する工程と、前記ビアホール形成用絶縁層に、前記配
線パターンを露出させるビアホールを形成する工程と、
前記ビアホールが形成された前記基板上に、導体パター
ンに対応する凹部を有する導体パターン形成用絶縁層を
形成する工程と、前記導体パターン形成用絶縁層が形成
された前記基板上に電解めっき用の給電層を形成する工
程と、前記給電層が形成された前記基板上に、前記凹部
および前記ビアホールが埋まる厚みまで周期的逆電流パ
ルスめっきを行って電解めっき層を形成する工程と、前
記電解めっき層形成後、前記導体パターン形成用絶縁層
が露出するまで切削する工程とを含むことを特徴とす
る。In a third conductor forming method according to the present invention, a step of forming a wiring pattern on an insulating substrate; a step of forming an insulating layer for forming a via hole on the substrate on which the wiring pattern is formed; Forming a via hole on the forming insulating layer to expose the wiring pattern;
Forming an insulating layer for forming a conductive pattern having a concave portion corresponding to a conductive pattern on the substrate on which the via hole is formed; and forming an insulating layer for electrolytic plating on the substrate on which the insulating layer for forming the conductive pattern is formed. Forming a power supply layer, forming an electrolytic plating layer on the substrate on which the power supply layer is formed by performing periodic reverse current pulse plating until the recesses and the via holes are filled, and forming the electrolytic plating After forming the layer, cutting until the insulating layer for forming a conductive pattern is exposed.
【０００８】本発明の第４の導体形成方法は、絶縁基板
上に配線パターンを形成する工程と、前記配線パターン
が形成された前記基板上にビアホール形成用絶縁層を形
成する工程と、前記ビアホール形成用絶縁層に、前記配
線パターンを露出させるビアホールを形成する工程と、
前記ビアホールが形成された前記基板上に、導体パター
ンに対応する凹部を有する導体パターン形成用絶縁層を
形成する工程と、前記導体パターン形成用絶縁層が形成
された前記基板上に無電解めっき用の触媒層を形成する
工程と、前記触媒層が形成された前記基板上に、前記凹
部および前記ビアホールが埋まる厚みまで無電解めっき
を行って無電解めっき層を形成する工程と、前記無電解
めっき層形成後、前記導体パターン形成用絶縁層が露出
するまで切削する工程とを含むことを特徴とする。In a fourth conductor forming method of the present invention, a step of forming a wiring pattern on an insulating substrate; a step of forming an insulating layer for forming a via hole on the substrate on which the wiring pattern is formed; Forming a via hole on the forming insulating layer to expose the wiring pattern;
Forming a conductive pattern forming insulating layer having a concave portion corresponding to a conductive pattern on the substrate on which the via hole is formed, and forming an electroless plating layer on the substrate on which the conductive pattern forming insulating layer is formed; Forming the electroless plating layer on the substrate on which the catalyst layer is formed, by performing electroless plating until the recesses and the via holes are filled, and forming the electroless plating layer. After forming the layer, cutting until the insulating layer for forming a conductive pattern is exposed.
【０００９】前記ビアホールのアスペクト比（パターン
深さ／開口幅）は０．５以上２．０以下であることが好
ましい。その理由は、ビアホールのアスペクト比が０．
５より小さいと形成されるビアホール径が大きくなり、
高密度な配線基板形成が難しくなるためであり、２．０
より大きいとめっきの付きまわり性が悪くなり、析出し
ためっき中にボイドが発生するからである。The aspect ratio (pattern depth / opening width) of the via hole is preferably 0.5 or more and 2.0 or less. The reason is that the aspect ratio of the via hole is 0.
If the diameter is smaller than 5, the diameter of the formed via hole becomes large,
This is because it is difficult to form a high-density wiring board.
If it is larger, the throwing power of the plating is deteriorated, and voids are generated in the deposited plating.
【００１０】本発明において、前記導体パターン形成用
絶縁層が、下記一般式（Ｉ）で表されるフルオレン骨格
を有するエポキシアクリレートを主原料とする感光性樹
脂からなることが好ましい。In the present invention, it is preferable that the insulating layer for forming a conductor pattern is made of a photosensitive resin mainly composed of an epoxy acrylate having a fluorene skeleton represented by the following general formula (I).
【００１１】[0011]
【化２】 Embedded image
【００１２】本発明の導体形成方法を用いれば、導体パ
ターンおよびビアホールの表面を平坦化することがで
き、電解めっきによる膜厚のばらつきを解消できる。ま
た、電解めっきの代わりに無電解めっきにより凹部を埋
め込み、切削を行うことによっても、導体パターンおよ
びビアホールの表面を平坦化することができる。本発明
の導体形成方法によれば、導体パターンおよびビアホー
ルがめっきにより埋め込まれるので、ビアホール直上に
ビアホールを配置することができる。また、無電解めっ
きを用いても、絶縁層間に触媒が残留することがなく、
マイグレーションなどの信頼性低下原因を解消すること
ができる。According to the conductor forming method of the present invention, the surface of the conductor pattern and the via hole can be flattened, and the variation in film thickness due to electrolytic plating can be eliminated. Alternatively, the surface of the conductor pattern and the via hole can be flattened by burying the concave portion by electroless plating instead of electrolytic plating and performing cutting. According to the conductor forming method of the present invention, since the conductor pattern and the via hole are buried by plating, the via hole can be arranged immediately above the via hole. Also, even when using electroless plating, no catalyst remains between the insulating layers,
The cause of reliability deterioration such as migration can be eliminated.
【００１３】特に、周期的逆電流パルスめっきは、従来
からあるＰＲ法の析出とエッチングを繰り返すめっき法
とは異なっており、短時間（例えば０．５ｍｓ）の逆電
流負荷（マイナス方向の電流負荷、すなわちアノードと
カソードの逆転）を伴う方法であるので、カソード部の
エッチングおよびアノード部への析出は起こらず、連続
めっきの状態となる。この方法で電解めっきを行えば、
凹部に対し優先的にめっき金属を析出させることがで
き、次工程で切削する部分へのめっき金属の析出が抑え
られる。また、無電解めっきも表面が平坦化しやすい性
質であるため、切削量を少なくなるようにめっき金属厚
みを制御することができる。In particular, the periodic reverse current pulse plating is different from the conventional plating method in which the deposition and etching are repeated in the conventional PR method, and a short-time (eg, 0.5 ms) reverse current load (a negative current load) is used. In other words, the method involves the reversal of the anode and the cathode), so that the etching of the cathode portion and the deposition on the anode portion do not occur, and a continuous plating state is obtained. If electroplating is performed by this method,
The plating metal can be preferentially deposited in the concave portions, and the deposition of the plating metal on the portion to be cut in the next step can be suppressed. In addition, since electroless plating is also a property that the surface is easily flattened, the thickness of the plated metal can be controlled so as to reduce the cutting amount.
【００１４】また、導体パターンに対応する凹部を、フ
ルオレン骨格を有するエポキシアクリレートを主原料と
する高解像度の感光性樹脂を用い、フォトリソプロセス
により一層ごと一括的に形成することで、特開２０００
−１６５０４９号公報で用いられているレーザによる直
描に比べて、スループットや微細化への対応が可能とな
る。フルオレン骨格を有するエポキシアクリレートを主
原料とする感光性樹脂は、特に解像度に優れており、例
えばポリイミドの解像度（アスペクト比）が１．０程度
であるのに対して、アスペクト比２．０のパターン形成
が可能なものである。したがって、今後、益々要求が厳
しくなると予測される微細配線や微細ビアホールの形成
にも十分対応することが可能である。Further, the concave portions corresponding to the conductor patterns are collectively formed by photolithography using a high-resolution photosensitive resin whose main raw material is epoxy acrylate having a fluorene skeleton.
It is possible to deal with throughput and miniaturization as compared with direct drawing by a laser used in -165049. A photosensitive resin containing epoxy acrylate having a fluorene skeleton as a main material is particularly excellent in resolution. For example, a polyimide having a resolution (aspect ratio) of about 1.0 and a pattern having an aspect ratio of 2.0 are used. It can be formed. Therefore, it is possible to sufficiently cope with the formation of fine wirings and fine via holes, which are expected to become more and more demanding in the future.
【００１５】本発明の多層配線基板製造方法は、本発明
の導体形成方法を用いることを特徴とする。A method for manufacturing a multilayer wiring board according to the present invention is characterized by using the conductor forming method according to the present invention.
【００１６】[0016]
【発明の実施の形態】以下、図面を参照し、本発明の好
適な実施例に基づいて本発明をさらに詳細に説明する。 （第１実施の形態）図１の（ａ）乃至（ｄ）は、本実施
形態の基本的な導体形成方法を部分断面図を用いて示し
ている。各図にしたがい工程の説明を行う。なお、各工
程間に適宜に洗浄および熱処理を行う。図中符号１１は
絶縁基板である。本発明における絶縁基板には、有機基
板、セラミック基板、シリコン基板、無機有機混合基板
（例として日本ガイシ社製のＧＶＰ）など絶縁材料から
なる基板だけでなく、絶縁材料以外の材料（例えば金
属）からなる基板上に絶縁体層が形成された積層構造の
ものも含まれる。積層構造のものの場合は、絶縁体層上
に導体が形成される。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in more detail based on preferred embodiments of the present invention with reference to the drawings. (First Embodiment) FIGS. 1A to 1D show a basic method for forming a conductor of the present embodiment using partial cross-sectional views. The process will be described with reference to each figure. Note that cleaning and heat treatment are appropriately performed between each step. Reference numeral 11 in the drawing denotes an insulating substrate. The insulating substrate in the present invention includes not only a substrate made of an insulating material such as an organic substrate, a ceramic substrate, a silicon substrate, and an inorganic-organic mixed substrate (for example, GVP manufactured by NGK Insulators, Ltd.), but also a material other than the insulating material (for example, a metal). And a laminate structure in which an insulator layer is formed on a substrate made of GaAs. In the case of a laminated structure, a conductor is formed on the insulator layer.
【００１７】まず図１（ａ）に示すように、絶縁基板１
１上に、導体パターンに対応する凹部１２ａが形成され
た絶縁材料からなる導体パターン形成用絶縁層１２を形
成する。絶縁基板１１自身に、あらかじめ所定の回路
（パッド・配線・ビアホールなど）が形成されていても
よい。導体パターン形成用絶縁層１２の材料には、上記
一般式（Ｉ）で表されるフルオレン骨格を有するエポキ
シアクリレートを主原料とする感光性樹脂が用いられ
る。このフルオレン骨格を有するエポキシアクリレート
を主原料とした感光性樹脂は、特開平７−４８４２４号
公報において光学用としての用途が開示されている。尚
これ以降、フルオレン骨格を有するエポキシアクリレー
トを主原料とする感光性樹脂をフルオレン樹脂と記載す
る。導体パターン形成用絶縁層１２の形成方法は、フレ
オン樹脂をスピンコート法、ダイコート法、カーテンコ
ート法、印刷法等で塗布し、乾燥等の処理を施してかた
めた後、フォトリソプロセスで所定形状のパターンを形
成し、ドライエッチングなどを用いて凹部１２ａを形成
する。First, as shown in FIG.
A conductive pattern forming insulating layer 12 made of an insulating material having a concave portion 12a corresponding to the conductive pattern formed thereon is formed on the conductive layer. A predetermined circuit (pad, wiring, via hole, etc.) may be formed in advance on the insulating substrate 11 itself. As a material of the insulating layer 12 for forming a conductor pattern, a photosensitive resin mainly composed of an epoxy acrylate having a fluorene skeleton represented by the general formula (I) is used. A photosensitive resin containing epoxy acrylate having a fluorene skeleton as a main raw material is disclosed in Japanese Patent Application Laid-Open No. 7-48424 for use in optical applications. Hereinafter, a photosensitive resin containing epoxy acrylate having a fluorene skeleton as a main raw material is referred to as a fluorene resin. The conductive pattern forming insulating layer 12 is formed by applying a freon resin by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like, performing a treatment such as drying, and then flattening the applied material by a photolithography process. Is formed, and the concave portion 12a is formed by dry etching or the like.
【００１８】次に図１（ｂ）に示すように、電解めっき
時の給電層１３を無電解めっき法、スパッタ法、蒸着
法、ＣＶＤ法などを用いて形成する。無電解めっき法に
より形成される給電層１３は、銅、ニッケルなどが適し
ている。この場合、無電解めっき層を形成する前にはそ
れに適した触媒層を形成する。また密着力等の観点から
絶縁層１２の表面を粗化していてもかまわない。一方、
スパッタ法、蒸着法、ＣＶＤ法などで形成される給電層
１３は、樹脂との密着性が良好な下層と、電解めっきを
行う表層として好適な上層とを積層して形成することが
好ましい。下層としてはクロム、チタン、モリブデン、
ニオブ、タンタルなどのＩＶａ族，Ｖａ族，ＶＩａ族の
遷移金属およびそれらの合金が好ましい。上層として
は、抵抗が小さい銅や銀が最適であるが、アルミニウム
およびＶＩＩＩａ族，Ｉｂ族の遷移金属のパラジウム、
金、白金なども好ましい。Next, as shown in FIG. 1B, a power supply layer 13 for electrolytic plating is formed by an electroless plating method, a sputtering method, a vapor deposition method, a CVD method, or the like. Copper, nickel, or the like is suitable for the power supply layer 13 formed by the electroless plating method. In this case, before forming the electroless plating layer, a catalyst layer suitable for the electroless plating layer is formed. In addition, the surface of the insulating layer 12 may be roughened from the viewpoint of adhesion and the like. on the other hand,
The power supply layer 13 formed by a sputtering method, an evaporation method, a CVD method, or the like is preferably formed by stacking a lower layer having good adhesion to a resin and an upper layer suitable as a surface layer on which electrolytic plating is performed. Chromium, titanium, molybdenum,
Group IVa, Group Va, Group VIa transition metals such as niobium and tantalum and alloys thereof are preferred. As the upper layer, copper or silver having a small resistance is optimal, but aluminum and palladium, a transition metal of VIIIa group or Ib group,
Gold, platinum and the like are also preferable.
【００１９】次いで図１（ｃ）に示すように、給電層１
３を形成した後、絶縁基板１１上の全面に対して凹部１
２ａが埋まる厚みまで周期的逆電流パルスめっきを行
い、電解めっき層１４を形成する。電解めっき層１４の
材料としては、銅および銅合金が最適である。周期的逆
電流パルスめっきには、メルテックス株式会社製のカパ
ーグリームＰＰＲめっき液が適している。この周期的逆
電流パルスめっきは、電流をパルス波形とし、短時間
（０．５ｍｓｅｃ程度）の逆電流を周期的に流す方法で
あり、逆電流時にキャリア成分（めっき抑制剤）の偏り
が発生し、電荷の集中部分への析出阻害が強く働き、全
体として溝部へ優先的にめっきが析出する状況が作り出
される。この方法によれば、直流めっきに比べ、めっき
の析出速度を落とさずに格段に凹部へのめっき析出量が
改善される。特に、例えば凹部に優先的にめっきが析出
する直流めっきがアスペクト比（深さ／幅）で１．０ま
で可能であるのに比べ、周期的逆電流パルスめっきはア
スペクト比で２．０まで対応できることからも、凹部１
２ａへのめっきに対し非常に有効である。Next, as shown in FIG.
3 are formed, and the entire surface of the insulating substrate 11 is
Periodic reverse current pulse plating is performed to a thickness at which 2a is buried, and an electrolytic plating layer 14 is formed. Copper and copper alloy are most suitable as the material of the electrolytic plating layer 14. For periodic reverse current pulse plating, Copper Glyme PPR plating solution manufactured by Meltex Co., Ltd. is suitable. This periodic reverse current pulse plating is a method in which a current has a pulse waveform and a short time (approximately 0.5 msec) reverse current is caused to flow periodically. When the reverse current is applied, bias of a carrier component (plating inhibitor) occurs. In addition, the deposition inhibition at the portion where the electric charge is concentrated acts strongly, and a situation is created in which plating is preferentially deposited as a whole in the groove. According to this method, the amount of plating deposited on the concave portions is remarkably improved without lowering the deposition rate of plating, as compared with DC plating. In particular, for example, DC plating, in which plating is preferentially deposited in recesses, is possible up to an aspect ratio (depth / width) of 1.0, whereas periodic reverse current pulse plating is compatible up to an aspect ratio of 2.0. The recess 1
Very effective for plating on 2a.
【００２０】そして、図１（ｄ）に示すように、電解め
っき層１４を形成したのち、表面の余分な電解めっき層
１４および給電層１３を研磨により切削し、導体パター
ン形成用絶縁層１２を露出させることによって導体パタ
ーンの形成が完了する。この研磨により表面を平坦化す
ることができる。また、研磨後、電解めっき層１４や給
電層１３を構成する金属の伸びを除去するために、エッ
チングを行っても構わない。Then, as shown in FIG. 1D, after the electrolytic plating layer 14 is formed, the excess electrolytic plating layer 14 and the power supply layer 13 on the surface are cut by polishing, and the conductive pattern forming insulating layer 12 is formed. Exposure completes the formation of the conductor pattern. The surface can be flattened by this polishing. After polishing, etching may be performed in order to remove elongation of the metal constituting the electrolytic plating layer 14 and the power supply layer 13.
【００２１】（第１実施例）本発明の第１実施例を図面
を参照して説明する。第１実施例は第１実施の形態に対
応するものである。図１を参照して、第１実施例である
導体形成方法を説明する。絶縁基板１１としてガラス繊
維強化有機基板（ＦＲ−５）を用い、表面を清浄化し
た。導体パターン形成用絶縁層１２としては、ネガ型の
フルオレン樹脂である新日鐵化学株式会社製のＶ−２５
９ＰＡを用いた。このネガ型フルオレン樹脂を、絶縁基
板１１上にスピンコータ法により膜厚１０μmで塗布
し、熱対流式乾燥機で乾燥を施し、フォトリソプロセス
である露光、現像を行って、得ようとする導体パターン
に対応する凹部１２ａを形成し、熱処理を施して硬化さ
せて導体パターン形成用絶縁層１２を形成した。(First Embodiment) A first embodiment of the present invention will be described with reference to the drawings. The first example corresponds to the first embodiment. With reference to FIG. 1, a method for forming a conductor according to a first embodiment will be described. A glass fiber reinforced organic substrate (FR-5) was used as the insulating substrate 11, and the surface was cleaned. The insulating layer 12 for forming a conductive pattern is made of a negative type fluorene resin, V-25 manufactured by Nippon Steel Chemical Co., Ltd.
9PA was used. This negative-type fluorene resin is applied on the insulating substrate 11 to a thickness of 10 μm by a spin coater method, dried by a thermal convection dryer, and subjected to exposure and development as a photolithographic process to obtain a conductor pattern to be obtained. Corresponding concave portions 12a were formed, heat-treated and cured to form conductive pattern forming insulating layer 12.
【００２２】その後、導体パターン形成用絶縁層１２が
形成されている基板１１の表面全面に、給電層１３とし
て、スパッタ法により膜厚８０ｎｍのＴｉＷ膜と膜厚２
００ｎｍのＣｕ膜を順次形成して積層させた。次いで、
給電層１３を用いて、メルテックス株式会社製の周期的
逆電流パルス銅めっき（添加剤：カパーグリームＰＰ
Ｒ、ブライトナー：ＰＰＲ−ＡＭ、キャリアー：ＰＰＲ
−ＣＭ）を行った。操作条件は、電流密度比を正方向：
逆方向＝１：３、通電時間として正方向：逆方向＝１０
／０．５（ｍｓｅｃ）とし、凹部１２ａが埋まり込む厚
さ１０μmの電解めっき層１４を形成した。Thereafter, a TiW film having a thickness of 80 nm and a film thickness of 2 are formed as a power supply layer 13 on the entire surface of the substrate 11 on which the insulating layer 12 for forming a conductor pattern is formed by sputtering.
00 nm Cu films were sequentially formed and laminated. Then
Using the power supply layer 13, a periodic reverse current pulse copper plating manufactured by Meltex Co., Ltd. (additive: Copperglyme PP
R, brightener: PPR-AM, carrier: PPR
-CM). The operating conditions are as follows:
Reverse direction = 1: 3, energization time forward direction: reverse direction = 10
/0.5 (msec), to form an electrolytic plating layer 14 having a thickness of 10 μm in which the concave portion 12a is buried.
【００２３】最後に、バフ研磨法を用いて導体パターン
形成用絶縁層１２が露出するまで研磨し、表面を平坦化
した。また、研磨時に銅ののびが発生した場合は、銅エ
ッチング液によりエッチングを行うことで整えた。Finally, the surface was flattened by using a buffing method until the insulating layer 12 for forming a conductor pattern was exposed. Further, when copper growth occurred during polishing, it was adjusted by performing etching with a copper etching solution.
【００２４】（第２実施の形態）第２実施の形態は、第
１実施の形態における電解めっきを無電解めっきとした
点が大きく異なっており、基本的には第１実施の形態と
同様である。図２の（ａ）乃至（ｄ）は、本実施形態の
基本的な導体形成方法を部分断面図を用いて示してい
る。各図にしたがい工程の説明を行う。なお、各工程間
に適宜に洗浄および熱処理を行う。図１と同一構成要素
には同一の符号を付してその説明を省略することがある
（以下、同様）。まず図２（ａ）に示すように、前記第
１実施の形態と同様にして、絶縁基板１１上に、フルオ
レン樹脂からなる導体パターン形成用絶縁層１２を形成
する。(Second Embodiment) The second embodiment is largely different from the first embodiment in that the electroplating in the first embodiment is replaced by an electroless plating, and is basically the same as the first embodiment. is there. 2A to 2D show a basic conductor forming method of the present embodiment using partial cross-sectional views. The process will be described with reference to each figure. Note that cleaning and heat treatment are appropriately performed between each step. The same components as those in FIG. 1 are denoted by the same reference numerals and description thereof may be omitted (the same applies hereinafter). First, as shown in FIG. 2A, an insulating layer 12 for forming a conductive pattern made of a fluorene resin is formed on an insulating substrate 11 in the same manner as in the first embodiment.
【００２５】次に図２（ｂ）に示すように、導体パター
ン形成用絶縁層１２が設けられた絶縁基板１１の表面全
面に、無電解めっき用の触媒層１５を形成する。触媒層
１５として、例えば、通常の無電解めっきで用いられて
いるＰｄ、Ａｕ、Ａｇ、Ｐｔなどを触媒化処理により形
成することができる。あるいは、スパッタ法を用いてＣ
ｕ、Ｐｄ、Ａｕ、Ａｇ、Ｐｔなどを形成してもよい。触
媒層１５をスパッタ法で形成する場合は、導体パターン
形成用絶縁層１２との密着が良好なクロム、チタン、モ
リブデン、ニオブ、タンタルなどのＩＶａ族，Ｖａ族，
ＶＩａ族の遷移金属およびそれらの合金を下層とし、そ
の上に無電解めっきにおける触媒として好適な上層を積
層してもよい。また、次の工程で行う無電解めっきと導
体パターン形成用絶縁層１２との密着を確保するため
に、導体パターン形成用絶縁層１２の表面を粗化しても
かまわない。Next, as shown in FIG. 2B, a catalyst layer 15 for electroless plating is formed on the entire surface of the insulating substrate 11 provided with the insulating layer 12 for forming a conductor pattern. As the catalyst layer 15, for example, Pd, Au, Ag, Pt, or the like used in normal electroless plating can be formed by a catalyzing treatment. Alternatively, the C
u, Pd, Au, Ag, Pt, etc. may be formed. When the catalyst layer 15 is formed by a sputtering method, the group IVa, Va, or tantalum, such as chromium, titanium, molybdenum, niobium, and tantalum, having good adhesion to the insulating layer 12 for forming a conductive pattern.
A transition metal of Group VIa and an alloy thereof may be used as a lower layer, and an upper layer suitable as a catalyst in electroless plating may be laminated thereon. Further, in order to ensure the close contact between the electroless plating performed in the next step and the insulating layer 12 for forming a conductive pattern, the surface of the insulating layer 12 for forming a conductive pattern may be roughened.
【００２６】次いで図２（ｃ）に示すように、触媒層１
５を形成した後、絶縁基板１１上の全面に対して凹部１
２ａが埋まる厚みまで無電解めっきを行い、無電解めっ
き層１６を形成する。無電解めっき層１６の材料として
は、銅および銅合金が最適である。この後、図２（ｄ）
に示すように、表面研磨を行って、表面の余分な無電解
めっき層１６および触媒層１５を切削し、パターン形成
用絶縁層１２を露出させるとともに、表面を平坦化す
る。また、研磨後、無電解めっき層１６や触媒層１５を
構成する金属の伸びを除去するために、エッチングを行
っても構わない。Next, as shown in FIG.
5 is formed, and the entire surface of the insulating substrate 11 is
Electroless plating is performed to a thickness at which 2a is buried to form an electroless plating layer 16. As the material of the electroless plating layer 16, copper and a copper alloy are optimal. After this, FIG.
As shown in (2), the surface is polished to cut off the excess electroless plating layer 16 and catalyst layer 15 on the surface, thereby exposing the insulating layer 12 for pattern formation and flattening the surface. After polishing, etching may be performed to remove the elongation of the metal constituting the electroless plating layer 16 and the catalyst layer 15.
【００２７】（第２実施例）本発明の第２実施例を図面
を参照して説明する。第２実施例は第２実施の形態に対
応するものである。図２を参照して、第２実施例である
導体形成方法を説明する。絶縁基板１１としてガラス繊
維強化有機基板（ＦＲ−５）を用い、表面を清浄化し
た。導体パターン形成用絶縁層１２としては、ネガ型の
フルオレン樹脂Ｖ−２５９ＰＡを用いた。このネガ型フ
ルオレン樹脂を、絶縁基板１１上にスピンコータ法によ
り膜厚１０μmで塗布し、熱対流式乾燥機で乾燥を施
し、フォトリソプロセスである露光、現像を行って、得
ようとする導体パターンに対応する凹部１２ａを形成
し、熱処理を施して硬化させて導体パターン形成用絶縁
層１２を形成した。(Second Embodiment) A second embodiment of the present invention will be described with reference to the drawings. The second example corresponds to the second embodiment. With reference to FIG. 2, a conductor forming method according to a second embodiment will be described. A glass fiber reinforced organic substrate (FR-5) was used as the insulating substrate 11, and the surface was cleaned. As the insulating layer 12 for forming a conductive pattern, a negative type fluorene resin V-259PA was used. This negative-type fluorene resin is applied on the insulating substrate 11 to a thickness of 10 μm by a spin coater method, dried by a thermal convection dryer, and exposed and developed by a photolithography process to obtain a conductor pattern to be obtained. Corresponding concave portions 12a were formed, heat-treated and cured to form conductive pattern forming insulating layer 12.
【００２８】その後、過マンガン酸カリ溶液にて導体パ
ターン形成用絶縁層１２の表面を粗化し、無電解銅めっ
き用のパラジウム触媒層１５を形成した。次いで、無電
解銅めっきを用いて凹部１２ａが埋まり込む厚さ１０μ
mの無電解めっき層１６を形成した。Thereafter, the surface of the conductor pattern forming insulating layer 12 was roughened with a potassium permanganate solution to form a palladium catalyst layer 15 for electroless copper plating. Next, a thickness of 10 μm for embedding the concave portion 12a using electroless copper plating.
m of electroless plating layer 16 was formed.
【００２９】最後に、研磨により表面を平滑に研磨して
導体パターン形成用絶縁層１２を露出させた。また、研
磨時に銅ののびが発生した場合は、銅エッチング液によ
りエッチングを行うことで整えた。Finally, the surface was polished smoothly by polishing to expose the insulating layer 12 for forming a conductor pattern. Further, when copper growth occurred during polishing, it was adjusted by performing etching with a copper etching solution.
【００３０】（第３実施の形態）第３実施の形態は、第
１実施の形態と基本的には同じであるが、基板１１上に
配線パターン１７およびビアホール１８ａを形成した後
に導体パターンを形成する点で大きく異なっている。図
３の（ａ）乃至（ｅ）は、本実施形態の基本的な導体形
成方法を部分断面図を用いて示している。各図にしたが
い工程の説明を行う。なお、各工程間に適宜に洗浄およ
び熱処理を行う。(Third Embodiment) The third embodiment is basically the same as the first embodiment, except that a wiring pattern 17 and a via hole 18a are formed on a substrate 11, and then a conductor pattern is formed. It is very different. 3A to 3E show a basic conductor forming method of the present embodiment using partial cross-sectional views. The process will be described with reference to each figure. Note that cleaning and heat treatment are appropriately performed between each step.
【００３１】まず図３（ａ）に示すように、絶縁基板１
１上に配線パターン１７を形成し、その上に、配線パタ
ーン１７を露出させるためのビアホール１８ａを形成す
るビアホール形成用絶縁層１８を設ける。配線パターン
１７を形成する方法は、サブトラクティブ法、セミアデ
ィティブ法、フルアディティブ法、ドライエッチング
法、リフトオフ法のいずれかでもよく、あるいは本発明
の導体形成方法を用いてもよい。ビアホール形成用絶縁
層１８を構成する絶縁材料は、フルオレン樹脂が最適で
あるが、エポキシ樹脂、エポキシアクリレート樹脂、ウ
レタンアクリレート樹脂、ポリエステル樹脂、フェノー
ル樹脂、ポリイミド樹脂、ＢＣＢ（ｂｅｎｚｏｃｙｃｌ
ｏｂｕｔｅｎｅ）、ＰＢＯ（ｐｏｌｙｂｅｎｚｏｘａｚ
ｏｌｅ）等も適している。ビアホール形成用絶縁層１８
を形成する方法は、液状ならばスピンコート法、ダイコ
ート法、カーテンコート法、印刷法等で塗布し、あるい
はドライフィルムであればラミネート法等で積層し、乾
燥等の処理を施してかためた後、感光性であればフォト
リソプロセスなどで、非感光であればレーザ加工法およ
び感光性レジストもしくはメタルマスクにより所定形状
のパターンを形成した後、ドライエッチングなどを用い
てビアホール１８ａを形成する。First, as shown in FIG.
1, a wiring pattern 17 is formed, and a via hole forming insulating layer 18 for forming a via hole 18a for exposing the wiring pattern 17 is provided thereon. The method for forming the wiring pattern 17 may be any of a subtractive method, a semi-additive method, a full-additive method, a dry etching method, a lift-off method, or the conductor forming method of the present invention. As the insulating material forming the insulating layer 18 for forming the via hole, a fluorene resin is optimal, but an epoxy resin, an epoxy acrylate resin, a urethane acrylate resin, a polyester resin, a phenol resin, a polyimide resin, a BCB (benzocycl)
obutene), PBO (polybenzoxaz)
ole) and the like are also suitable. Via hole forming insulating layer 18
Is formed by spin coating, die coating, curtain coating, printing or the like in the case of a liquid, or lamination by a lamination method in the case of a dry film, and is subjected to a treatment such as drying. After that, if photosensitive, a photolithographic process or the like is used, if non-photosensitive, a pattern of a predetermined shape is formed by a laser processing method and a photosensitive resist or metal mask, and then the via hole 18a is formed by dry etching or the like.
【００３２】次に図３（ｂ）に示すように、ビアホール
形成用絶縁層１８の上に、導体パターンに対応する凹部
１２ａを有する導体パターン形成用絶縁層１２を設け
る。導体パターン形成用絶縁層１２の材料にはフルオレ
ン樹脂が用いられ、スピンコート法、ダイコート法、カ
ーテンコート法、印刷法等で塗布し、乾燥等の処理を施
してかためた後、フォトリソプロセスで所定形状のパタ
ーンを形成し、ドライエッチングなどを用いて凹部１２
ａを形成する。Next, as shown in FIG. 3B, a conductor pattern forming insulating layer 12 having a recess 12a corresponding to the conductor pattern is provided on the via hole forming insulating layer 18. A fluorene resin is used as a material of the insulating layer 12 for forming a conductive pattern, and is applied by a spin coating method, a die coating method, a curtain coating method, a printing method, and the like, and is subjected to a treatment such as drying and the like, and then is cured by a photolithography process. A pattern having a predetermined shape is formed, and the recess 12 is formed by dry etching or the like.
a is formed.
【００３３】次に図３（ｃ）に示すように、導体パター
ン形成用絶縁層１２が形成された絶縁基板１１の表面全
面に、電解めっき時の給電層１３を、前記第１実施の形
態と同様にして形成する。次いで図３（ｄ）に示すよう
に、給電層１３形成後、絶縁基板１１上の全面に対し
て、ビアホール１８ａおよび凹部１２ａが埋まる厚みま
で、前記第１実施の形態と同様にして周期的逆電流パル
スめっきを行い、電解めっき層１４を形成する。電解め
っき層１４の材料としては、銅および銅合金が最適であ
る。この後、図３（ｅ）に示すように、電解めっき層１
４を形成したのち、表面の余分な電解めっき層１４およ
び給電層１３を研磨により切削し、導体パターン形成用
絶縁層１２を露出させることによって導体パターンの形
成が完了する。この研磨により表面を平坦化することが
できる。また、研磨後、電解めっき層１４や給電層１３
を構成する金属の伸びを除去するために、エッチングを
行っても構わない。Next, as shown in FIG. 3C, a power supply layer 13 at the time of electrolytic plating is formed on the entire surface of the insulating substrate 11 on which the insulating layer 12 for forming a conductor pattern is formed, according to the first embodiment. It forms similarly. Next, as shown in FIG. 3D, after the power supply layer 13 is formed, the entire surface of the insulating substrate 11 is periodically inverted until the via hole 18a and the concave portion 12a are filled in the same manner as in the first embodiment. Current pulse plating is performed to form the electrolytic plating layer 14. Copper and copper alloy are most suitable as the material of the electrolytic plating layer 14. Thereafter, as shown in FIG.
After the formation of the conductive pattern 4, the excess electrolytic plating layer 14 and the power supply layer 13 on the surface are cut by polishing to expose the conductive pattern forming insulating layer 12, thereby completing the formation of the conductive pattern. The surface can be flattened by this polishing. After polishing, the electrolytic plating layer 14 and the power supply layer 13 are polished.
Etching may be performed in order to remove the elongation of the metal that constitutes.
【００３４】（第３実施例）本発明の第３実施例を図面
を参照して説明する。第３実施例は第３実施の形態に対
応するものである。図３を参照して、第３実施例である
導体形成方法を説明する。表面上に配線パターン１７が
形成された絶縁基板１１を用意した。絶縁基板１１とし
てはガラス繊維強化有機基板（ＦＲ−５）を用い、配線
パターン１７はサブトラクティブ法により銅を用いて形
成した。配線パターン１７を備えた絶縁基板１１の表面
を清浄化させた後、ビアホール形成用絶縁層１８とし
て、ネガ型のフルオレン樹脂Ｖ−２５９ＰＡをスピンコ
ータ法により膜厚２０μmで塗布し、熱対流式乾燥機で
乾燥を施し、フォトリソプロセスである露光、現像を行
ってビアホール１８ａを形成し、熱処理を施して硬化さ
せてビアホール形成用絶縁層１８を形成した。ビアホー
ル１８ａのアスペクト比（パターン深さ／開口幅）は
１．０とした。(Third Embodiment) A third embodiment of the present invention will be described with reference to the drawings. The third example corresponds to the third embodiment. Third Embodiment A conductor forming method according to a third embodiment will be described with reference to FIG. An insulating substrate 11 having a wiring pattern 17 formed on the surface was prepared. A glass fiber reinforced organic substrate (FR-5) was used as the insulating substrate 11, and the wiring pattern 17 was formed using copper by a subtractive method. After the surface of the insulating substrate 11 provided with the wiring pattern 17 is cleaned, a negative type fluorene resin V-259PA is applied with a thickness of 20 μm by a spin coater method as an insulating layer 18 for forming a via hole. Then, exposure and development as photolithography processes were performed to form via holes 18a, and heat treatment was performed to cure the via holes 18a, thereby forming via hole forming insulating layers 18. The aspect ratio (pattern depth / opening width) of the via hole 18a was set to 1.0.
【００３５】その上に、ネガ型のフルオレン樹脂（Ｖ−
２５９ＰＡ）をスピンコータ法により膜厚１０μmで塗
布し、熱対流式乾燥機で乾燥を施し、フォトリソプロセ
スである露光、現像を行って得ようとする導体パターン
に対応する凹部１２ａを形成し、熱処理を施して硬化さ
せて導体パターン形成用絶縁層１２を形成した。その
後、導体パターン形成用絶縁層１２が形成されている基
板１１の表面全面に、給電層１３として、スパッタ法に
より膜厚８０ｎｍのＴｉＷ膜と膜厚２００ｎｍのＣｕ膜
を順次形成して積層させた。続いて、給電層１３を用
い、前記実施例１と同様にして周期的逆電流パルス銅め
っきを行い、ビアホール１８ａと凹部１２ａが埋まり込
む厚さ３０μmの電解めっき層１４を形成した。最後
に、研磨により表面を平滑に研磨して導体パターン形成
用絶縁層１２を露出させた。また、研磨時に銅ののびが
発生した場合は、銅エッチング液によりエッチングを行
うことで整えた。On top of that, a negative type fluorene resin (V-
259PA) is applied by a spin coater method to a film thickness of 10 μm, dried by a thermal convection dryer, and exposed and developed by a photolithographic process to form a concave portion 12a corresponding to a conductor pattern to be obtained. The resultant was applied and cured to form an insulating layer 12 for forming a conductive pattern. Thereafter, a TiW film having a thickness of 80 nm and a Cu film having a thickness of 200 nm were sequentially formed and laminated as a power supply layer 13 on the entire surface of the substrate 11 on which the insulating layer 12 for forming a conductive pattern was formed by sputtering. . Subsequently, using the power supply layer 13, periodic reverse current pulse copper plating was performed in the same manner as in Example 1 to form an electrolytic plating layer 14 having a thickness of 30 μm in which the via holes 18 a and the recesses 12 a were filled. Finally, the surface was polished smoothly by polishing to expose the insulating layer 12 for forming a conductor pattern. Further, when copper growth occurred during polishing, it was adjusted by performing etching with a copper etching solution.
【００３６】（第４実施の形態）第４実施の形態は、第
３実施の形態における電解めっきを無電解めっきとした
点が大きく異なっており、基本的には第３実施の形態と
同様である。図４の（ａ）乃至（ｅ）は、本実施形態の
基本的な導体形成方法を部分断面図を用いて示してい
る。各図にしたがい工程の説明を行う。なお、各工程間
に適宜に洗浄および熱処理を行う。まず図４（ａ）に示
すように、前記第３実施の形態と同様にして、絶縁基板
１１上に配線パターン１７を形成し、その上に、配線パ
ターン１７を露出させるためのビアホール１８ａを形成
するビアホール形成用絶縁層１８を設ける。(Fourth Embodiment) The fourth embodiment is largely different from the third embodiment in that electroplating is replaced by electroless plating, and is basically the same as the third embodiment. is there. 4A to 4E show a basic method of forming a conductor according to the present embodiment using partial cross-sectional views. The process will be described with reference to each figure. Note that cleaning and heat treatment are appropriately performed between each step. First, as shown in FIG. 4A, a wiring pattern 17 is formed on an insulating substrate 11 and a via hole 18a for exposing the wiring pattern 17 is formed thereon in the same manner as in the third embodiment. A via hole forming insulating layer 18 is provided.
【００３７】次に図４（ｂ）に示すように、ビアホール
形成用絶縁層１８の上に、フルオレン樹脂からなり、導
体パターンに対応する凹部１２ａを有する導体パターン
形成用絶縁層１２を、前記第３の実施形態と同様にして
形成する。次に図４（ｃ）に示すように、導体パターン
形成用絶縁層１２が形成された絶縁基板１１上の全面
に、無電解めっき用の触媒層１５を、前記第２実施の形
態と同様にして形成する。続いて図４（ｄ）に示すよう
に、触媒層１５を形成した後、絶縁基板１１上の全面に
対してビアホール１８ａと凹部１２ａが埋まる厚みまで
無電解めっきを行い。無電解めっき層１６を形成する。
無電解めっき層１６の材料としては、銅および銅合金が
最適である。Next, as shown in FIG. 4B, the conductor pattern forming insulating layer 12 made of fluorene resin and having a concave portion 12a corresponding to the conductor pattern is formed on the via hole forming insulating layer 18 by the first step. It is formed in the same manner as in the third embodiment. Next, as shown in FIG. 4C, a catalyst layer 15 for electroless plating is formed on the entire surface of the insulating substrate 11 on which the insulating layer 12 for forming a conductive pattern is formed in the same manner as in the second embodiment. Formed. Subsequently, as shown in FIG. 4D, after the catalyst layer 15 is formed, the entire surface of the insulating substrate 11 is subjected to electroless plating until the via hole 18a and the concave portion 12a are filled. An electroless plating layer 16 is formed.
As the material of the electroless plating layer 16, copper and a copper alloy are optimal.
【００３８】この後、図４（ｅ）に示すように、表面研
磨を行って、表面の余分な無電解めっき層１６および触
媒層１５を切削し、パターン形成用絶縁層１２を露出さ
せるとともに、表面を平坦化する。また、研磨後、無電
解めっき層１６や触媒層１５を構成する金属の伸びを除
去するために、エッチングを行っても構わない。、無電
解めっき１６を形成したのち、表面研磨を行う。また、
研磨後の金属の伸びを除去するために、エッチングを行
っても構わない。Thereafter, as shown in FIG. 4 (e), the surface is polished to cut off the unnecessary electroless plating layer 16 and catalyst layer 15 on the surface to expose the pattern forming insulating layer 12. Flatten the surface. After polishing, etching may be performed to remove the elongation of the metal constituting the electroless plating layer 16 and the catalyst layer 15. After the electroless plating 16 is formed, the surface is polished. Also,
Etching may be performed to remove elongation of the metal after polishing.
【００３９】（第４実施例）本発明の第４実施例を図面
を参照して説明する。第４実施例は第４実施の形態に対
応するものである。図４を参照して、第４実施例である
導体形成方法を説明する。絶縁基板１１としてガラス繊
維強化有機基板（ＦＲ−５）を用い、その上にサブトラ
クティブ法により銅からなる配線パターン１７を形成し
た。表面を清浄化させた後、ビアホール形成用絶縁層１
８を形成するために、ネガ型のフルオレン樹脂のＶ−２
５９ＰＡをスピンコータ法により膜厚２０μmで塗布
し、熱対流式乾燥機で乾燥を施し、フォトリソプロセス
である露光、現像を行ってビアホール１８ａを形成し、
熱処理を施して硬化させた。ビアホール１８ａのアスペ
クト比（パターン深さ／開口幅）は１．０とした。次
に、導体パターン形成用絶縁層１２を形成するために、
ネガ型のフルオレン樹脂（Ｖ−２５９ＰＡ）をスピンコ
ータ法により膜厚１０μmで塗布し、熱対流式乾燥機で
乾燥を施し、フォトリソプロセスである露光、現像を行
って得ようとする導体パターンに対応する凹部１２ａを
形成し、熱処理を施して硬化させた。(Fourth Embodiment) A fourth embodiment of the present invention will be described with reference to the drawings. The fourth example corresponds to the fourth embodiment. Fourth Embodiment A conductor forming method according to a fourth embodiment will be described with reference to FIG. A glass fiber reinforced organic substrate (FR-5) was used as the insulating substrate 11, and a wiring pattern 17 made of copper was formed thereon by a subtractive method. After the surface is cleaned, the insulating layer 1 for forming a via hole is formed.
In order to form No. 8, a negative type fluorene resin V-2
59PA is applied to a thickness of 20 μm by a spin coater method, dried by a thermal convection dryer, and exposed and developed by a photolithography process to form a via hole 18a,
Heat treatment was applied to cure. The aspect ratio (pattern depth / opening width) of the via hole 18a was set to 1.0. Next, in order to form the insulating layer 12 for forming a conductor pattern,
A negative-type fluorene resin (V-259PA) is applied in a thickness of 10 μm by a spin coater method, dried by a thermal convection dryer, and exposed to light and developed as a photolithographic process, corresponding to a conductor pattern to be obtained. The concave portion 12a was formed, and was cured by performing a heat treatment.
【００４０】その後、過マンガン酸カリ溶液にてビアホ
ール形成用絶縁層１８および導体パターン形成用絶縁層
１２の表面を粗化し、無電解銅めっき用のパラジウム触
媒層１５を形成した。次いで、無電解銅めっきを用いて
ビアホール１８ａと凹部１２ａが埋まり込むめっき厚み
３０μmの無電解めっき層１６を形成した。Thereafter, the surfaces of the insulating layer 18 for forming via holes and the insulating layer 12 for forming a conductor pattern were roughened with a potassium permanganate solution to form a palladium catalyst layer 15 for electroless copper plating. Next, an electroless plating layer 16 having a plating thickness of 30 μm in which the via holes 18a and the concave portions 12a were filled was formed by using electroless copper plating.
【００４１】最後に、研磨により表面を平滑に研磨して
導体パターン形成用絶縁層１２を露出させた。また、研
磨時に銅ののびが発生した場合は、銅エッチング液によ
りエッチングを行うことで整えた。Finally, the surface was polished by polishing to expose the insulating layer 12 for forming a conductor pattern. Further, when copper growth occurred during polishing, it was adjusted by performing etching with a copper etching solution.
【００４２】なお、上記各実施の形態および各実施例の
導体形成方法はいずれも、多層配線基板を製造する際に
好適に用いられるものであり、配線が高密度に形成され
た多層配線基板にも適用可能である。必要に応じて異な
る実施形態または実施例の導体形成方法を組み合わせて
もよい。The conductor forming method of each of the above embodiments and examples is preferably used when manufacturing a multilayer wiring board, and is applied to a multilayer wiring board on which wirings are formed at a high density. Is also applicable. If necessary, conductor forming methods of different embodiments or examples may be combined.
【００４３】[0043]
【発明の効果】本発明の導体形成方法によれば、得よう
とする導体パターンに対応した凹部を形成しておき、該
凹部内にめっき層を充填することによって導体を形成す
るので、層間の電気的接続が確実であり、導体の接続信
頼性が高い。またビアホールを設ける場合には、ビアホ
ール内部にめっき層を充填するため、ビアホールの上に
ビアホールを形成することが可能となり、高密度なパタ
ーン形成が可能となる。したがって本発明によれば、高
密度でかつ信頼性の高い導体形成方法および多層配線基
板の製造方法が提供される。According to the conductor forming method of the present invention, the conductor is formed by forming a recess corresponding to the conductor pattern to be obtained and filling the recess with a plating layer. The electrical connection is secure, and the connection reliability of the conductor is high. When a via hole is provided, the inside of the via hole is filled with a plating layer, so that the via hole can be formed on the via hole, and a high-density pattern can be formed. Therefore, according to the present invention, a method for forming a conductor with high density and high reliability and a method for manufacturing a multilayer wiring board are provided.
【００４４】また、導体パターン形成用絶縁層の凹部内
に導体を構成するめっき層を形成した後、切削を行うこ
とで導体パターン形成用絶縁層の表面を露出させるた
め、形成される回路表面が平坦となり、多層配線基板を
形成する場合の歩留まりや信頼性の向上につながる。さ
らに、周期的逆電流めっきおよび無電解めっきを用いる
ことで、必要最小限のめっき析出量で凹部内にめっき層
を形成することができるので、無駄が少なく、最終の切
削量を少なくすることができ、信頼性向上やスループッ
ト向上につながる。また、導体パターン形成用絶縁層を
フルオレン樹脂で形成することにより、高い解像度が得
られるため、微細な導体パターンも精度良く形成するこ
とができる。さらに、導体形成工程において、エッチン
グやめっき用のレジストを用いないため、コストをさら
に下げることができる。また、電解めっきを用いる際、
セミアディティブ法などでは開口面積から正確なめっき
条件を計算や予備実験などで検討しなければならない
が、本発明の製造方法ではめっき析出面積は用いる基板
表面積となるため、めっき条件を容易に決定することが
できる。Further, after the plating layer constituting the conductor is formed in the concave portion of the insulating layer for forming the conductor pattern, the surface of the insulating layer for forming the conductor pattern is exposed by cutting, so that the surface of the circuit to be formed is reduced. It becomes flat, which leads to improvement in yield and reliability when forming a multilayer wiring board. Furthermore, by using the periodic reverse current plating and the electroless plating, the plating layer can be formed in the concave portion with the minimum required amount of plating deposition, so that there is little waste and the final cutting amount can be reduced. To improve reliability and throughput. In addition, by forming the insulating layer for forming a conductor pattern with a fluorene resin, high resolution can be obtained, so that a fine conductor pattern can be formed with high accuracy. Furthermore, in the conductor forming step, since a resist for etching or plating is not used, the cost can be further reduced. Also, when using electrolytic plating,
In the semi-additive method, etc., accurate plating conditions must be examined by calculation or preliminary experiments from the opening area. However, in the manufacturing method of the present invention, the plating deposition area is the substrate surface area to be used, so that the plating conditions are easily determined. be able to.
【図１】本発明第１実施例の製造方法を示す部分断面
図。FIG. 1 is a partial sectional view showing a manufacturing method according to a first embodiment of the present invention.
【図２】本発明第２実施例の製造方法を示す部分断面
図。FIG. 2 is a partial sectional view showing a manufacturing method according to a second embodiment of the present invention.
【図３】本発明第３実施例の製造方法を示す部分断面
図。FIG. 3 is a partial sectional view showing a manufacturing method according to a third embodiment of the present invention.
【図４】本発明第４実施例の製造方法を示す部分断面
図。FIG. 4 is a partial sectional view showing a manufacturing method according to a fourth embodiment of the present invention.
１１…絶縁基板 １２…導体パターン形成用絶縁層 １２ａ…凹部 １３…給電層 １４…電解めっき層 １５…触媒層 １６…無電解めっき層 １７…配線パターン １８…ビアホール形成用絶縁層 １８ａ…ビアホール DESCRIPTION OF SYMBOLS 11 ... Insulating substrate 12 ... Conductive pattern forming insulating layer 12a ... Depression 13 ... Power supply layer 14 ... Electroplating layer 15 ... Catalyst layer 16 ... Electroless plating layer 17 ... Wiring pattern 18 ... Via hole forming insulating layer 18a ... Via hole
───────────────────────────────────────────────────── フロントページの続き (72)発明者 松井 孝二 東京都港区芝五丁目７番１号 日本電気株 式会社内 Ｆターム(参考） 2H025 AA02 AA03 AA18 AA20 AB15 AB16 AD01 BC13 BC74 BC83 BC86 FA28 FA39 FA43 4J027 AE04 CC04 CC05 CD10 5E343 AA02 AA12 AA22 BB02 BB24 BB44 CC62 CC65 CC71 DD25 DD33 DD43 DD44 DD47 EE01 EE33 EE43 ER01 ER12 ER18 FF01 GG20 5E346 AA12 AA15 AA43 BB11 CC09 CC32 CC37 DD03 DD25 DD33 DD44 EE33 EE35 FF01 GG15 GG17 GG18 GG22 GG40 HH25 ────────────────────────────────────────────────── ─── Continued on the front page (72) Koji Matsui, Inventor 5-7-1 Shiba, Minato-ku, Tokyo F-term within NEC Corporation (reference) 2H025 AA02 AA03 AA18 AA20 AB15 AB16 AD01 BC13 BC74 BC83 BC86 FA28 FA39 FA43 4J027 AE04 CC04 CC05 CD10 5E343 AA02 AA12 AA22 BB02 BB24 BB44 CC62 CC65 CC71 DD25 DD33 DD43 DD44 DD47 EE01 EE33 EE43 ER01 ER12 ER18 FF01 GG20 5E346 AA12 AA15 AA43 BB11 GG11 GG03 DD33 CC33
Claims (7)
部を有する導体パターン形成用絶縁層を形成する工程
と、 前記導体パターン形成用絶縁層が形成された前記基板上
に電解めっき用の給電層を形成する工程と、 前記給電層が形成された前記基板上に、前記凹部が埋ま
る厚みまで周期的逆電流パルスめっきを行って電解めっ
き層を形成する工程と、 前記電解めっき層形成後、前記導体パターン形成用絶縁
層が露出するまで切削する工程とを含むことを特徴とす
る導体形成方法。1. A step of forming an insulating layer for forming a conductive pattern having a concave portion corresponding to a conductive pattern on an insulating substrate; and supplying power for electrolytic plating on the substrate on which the insulating layer for forming a conductive pattern is formed. Forming a layer, on the substrate on which the power supply layer is formed, performing periodic reverse current pulse plating until the recesses are filled to form an electrolytic plating layer, and after forming the electrolytic plating layer, Cutting until the insulating layer for forming a conductor pattern is exposed.
部を有する導体パターン形成用絶縁層を形成する工程
と、 前記導体パターン形成用絶縁層が形成された前記基板上
に無電解めっき用の触媒層を形成する工程と、 前記触媒層が形成された前記基板上に、前記凹部が埋ま
る厚みまで無電解めっきを行って無電解めっき層を形成
する工程と、 前記無電解めっき層形成後、前記導体パターン形成用絶
縁層が露出するまで切削する工程とを含むことを特徴と
する導体形成方法。A step of forming an insulating layer for forming a conductive pattern having a concave portion corresponding to the conductive pattern on the insulating substrate; and forming an insulating layer for electroless plating on the substrate on which the insulating layer for forming the conductive pattern is formed. A step of forming a catalyst layer, a step of forming an electroless plating layer on the substrate on which the catalyst layer is formed by performing electroless plating until the recesses are filled, and after forming the electroless plating layer, Cutting until the insulating layer for forming a conductor pattern is exposed.
程と、 前記配線パターンが形成された前記基板上にビアホール
形成用絶縁層を形成する工程と、 前記ビアホール形成用絶縁層に、前記配線パターンを露
出させるビアホールを形成する工程と、 前記ビアホールが形成された前記基板上に、導体パター
ンに対応する凹部を有する導体パターン形成用絶縁層を
形成する工程と、 前記導体パターン形成用絶縁層が形成された前記基板上
に電解めっき用の給電層を形成する工程と、 前記給電層が形成された前記基板上に、前記凹部および
前記ビアホールが埋まる厚みまで周期的逆電流パルスめ
っきを行って電解めっき層を形成する工程と、 前記電解めっき層形成後、前記導体パターン形成用絶縁
層が露出するまで切削する工程とを含むことを特徴とす
る導体形成方法。A step of forming a wiring pattern on an insulating substrate; a step of forming an insulating layer for forming a via hole on the substrate on which the wiring pattern is formed; and forming the wiring pattern on the insulating layer for forming a via hole. Forming a via hole exposing a conductive pattern; forming a conductive pattern forming insulating layer having a recess corresponding to the conductive pattern on the substrate on which the via hole is formed; forming the conductive pattern forming insulating layer. Forming a power supply layer for electrolytic plating on the formed substrate; and performing periodic reverse current pulse plating on the substrate on which the power supply layer is formed until the concave portion and the via hole are buried. Forming a layer, and cutting after the formation of the electrolytic plating layer until the insulating layer for forming a conductor pattern is exposed. Characteristic conductor forming method.
と、 前記配線パターンが形成された前記基板上にビアホール
形成用絶縁層を形成する工程と、 前記ビアホール形成用絶縁層に、前記配線パターンを露
出させるビアホールを形成する工程と、 前記ビアホールが形成された前記基板上に、導体パター
ンに対応する凹部を有する導体パターン形成用絶縁層を
形成する工程と、 前記導体パターン形成用絶縁層が形成された前記基板上
に無電解めっき用の触媒層を形成する工程と、 前記触媒層が形成された前記基板上に、前記凹部および
前記ビアホールが埋まる厚みまで無電解めっきを行って
無電解めっき層を形成する工程と、 前記無電解めっき層形成後、前記導体パターン形成用絶
縁層が露出するまで切削する工程とを含むことを特徴と
する導体形成方法。4. A step of forming a wiring pattern on an insulating substrate, a step of forming an insulating layer for forming a via hole on the substrate on which the wiring pattern is formed, and a step of forming the wiring pattern on the insulating layer for forming a via hole. Forming a via hole exposing a conductive pattern; forming a conductive pattern forming insulating layer having a recess corresponding to the conductive pattern on the substrate on which the via hole is formed; forming the conductive pattern forming insulating layer. Forming a catalyst layer for electroless plating on the substrate that has been formed, and performing electroless plating on the substrate on which the catalyst layer is formed until the recesses and the via holes are filled with the electroless plating layer. Forming the electroless plating layer, and cutting until the conductive pattern forming insulating layer is exposed. Conductor forming method.
深さ／開口幅）が０．５以上２．０以下であることを特
徴とする請求項３または４のいずれかに記載の導体形成
方法。5. The conductor forming method according to claim 3, wherein an aspect ratio (pattern depth / opening width) of the via hole is 0.5 or more and 2.0 or less.
般式（Ｉ）で表されるフルオレン骨格を有するエポキシ
アクリレートを主原料とする感光性樹脂からなることを
特徴とする請求項１乃至５のいずれかに記載の導体形成
方法。 【化１】 6. The conductive pattern-forming insulating layer is made of a photosensitive resin mainly composed of epoxy acrylate having a fluorene skeleton represented by the following general formula (I). The method for forming a conductor according to any one of the above. Embedded image
成方法を用いて、多層配線基板を製造する方法。7. A method for manufacturing a multilayer wiring board by using the method for forming a conductor according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001043792A JP2002246744A (en) | 2001-02-20 | 2001-02-20 | Conductor-forming method, and multilayer wiring board manufacturing method using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001043792A JP2002246744A (en) | 2001-02-20 | 2001-02-20 | Conductor-forming method, and multilayer wiring board manufacturing method using the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002246744A true JP2002246744A (en) | 2002-08-30 |
Family
ID=18905901
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001043792A Pending JP2002246744A (en) | 2001-02-20 | 2001-02-20 | Conductor-forming method, and multilayer wiring board manufacturing method using the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002246744A (en) |
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| JP2006210473A (en) * | 2005-01-26 | 2006-08-10 | Kyocera Corp | Multilayer wiring substrate |
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| JP2007134458A (en) * | 2005-11-09 | 2007-05-31 | Shinko Electric Ind Co Ltd | Manufacturing method of wiring board and manufacturing method of semiconductor device |
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| EP2083294A3 (en) * | 2008-01-24 | 2009-08-12 | Nitto Denko Corporation | Manufacturing method of opto-electric hybrid board and opto-electric hybrid board obtained thereby |
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