JP2007335803A - Method for manufacturing wiring board - Google Patents

Method for manufacturing wiring board Download PDF

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JP2007335803A
JP2007335803A JP2006168758A JP2006168758A JP2007335803A JP 2007335803 A JP2007335803 A JP 2007335803A JP 2006168758 A JP2006168758 A JP 2006168758A JP 2006168758 A JP2006168758 A JP 2006168758A JP 2007335803 A JP2007335803 A JP 2007335803A
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wiring
layer
manufacturing
wiring board
forming
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JP4730222B2 (en
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Yoshiyuki Hitsuoka
祥之 櫃岡
Koji Ichikawa
浩二 市川
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Toppan Inc
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Toppan Printing Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a wiring board for easily forming a wiring layer shaped so that it is possible to easily peel a resist. <P>SOLUTION: This method for manufacturing a wiring board is provided with: a process for forming a conductive layer on an insulating film; a process for forming a mask for a pattern on the conductive layer; and a process for forming the conductive layer by PR electrolytic plating treatment for periodically reversing a current direction in a region which is not covered with the mask for a pattern on the conductive layer, and characterized so that the current rate (I<SB>F</SB>/I<SB>R</SB>) of forward currents I<SB>F</SB>and reverse currents I<SB>R</SB>in the PR electrolytic plating treatment can be set so as to be ranging from 1:3 to 1:1, and that the conductive layer can have an almost rectangular cross-sectional shape. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、プリント基板や半導体パッケージ基板などの配線基板の製造方法に関する。  The present invention relates to a method of manufacturing a wiring board such as a printed board or a semiconductor package board.

従来より、例えば樹脂製配線基板の表面に配線パターンを形成するには、通常、エッチングによるサブトラクティブ法が採られている。しかし、近年の配線の細線化・高密度化に伴い、電解めっきによって配線パターンを形成するセミアディティブ法による微細配線形成技術が期待されている。  Conventionally, for example, in order to form a wiring pattern on the surface of a resin wiring substrate, a subtractive method by etching is usually employed. However, with the recent thinning and high density of wiring, a fine wiring forming technique by a semi-additive method for forming a wiring pattern by electrolytic plating is expected.

このセミアディティブ法によれば、例えば、以下のような手法で銅からなる配線層が形成される。  According to this semi-additive method, for example, a wiring layer made of copper is formed by the following method.

即ち、まず、基板表面全面にパラジウムからなるめっき触媒核を形成する。次いで、無電解銅めっきにより、基板表面全体に無電解銅めっき層(以下シード層とする)を形成する。次に、シード層上に感光性レジストをラミネートし、露光・現像を行い、レジストパターンを形成する。  That is, first, a plating catalyst nucleus made of palladium is formed on the entire surface of the substrate. Next, an electroless copper plating layer (hereinafter referred to as a seed layer) is formed on the entire surface of the substrate by electroless copper plating. Next, a photosensitive resist is laminated on the seed layer, and exposure and development are performed to form a resist pattern.

その後、基板端に電極をつけて、露出したシード層上に電解銅めっき（硫酸銅めっき）を行い、シード層上に電解銅めっき層を形成する。次いで、感光性レジストを剥離し、クイックエッチングにより電解めっき層で覆われていないシード層を除去することにより、銅配線パターンが形成される。このような従来の配線層の形成方法は、例えば特許文献１に記載されている。  Thereafter, an electrode is attached to the edge of the substrate, electrolytic copper plating (copper sulfate plating) is performed on the exposed seed layer, and an electrolytic copper plating layer is formed on the seed layer. Next, the photosensitive resist is peeled off, and the seed layer not covered with the electrolytic plating layer is removed by quick etching to form a copper wiring pattern. Such a conventional method for forming a wiring layer is described in Patent Document 1, for example.

このように、従来のセミアディティブ工法においては、シード層の形成、レジストパターンの形成、及び直流（ＤＣ）電流による金属の電解めっきによって配線を形成していた。しかし、直流（ＤＣ）電流によるめっき法では、得られためっき層がレジストの側面を押し、図１１に示すように、配線の断面形状が太鼓型になるという問題がある。  As described above, in the conventional semi-additive method, the wiring is formed by forming a seed layer, forming a resist pattern, and electroplating a metal with a direct current (DC) current. However, the plating method using a direct current (DC) current has a problem that the obtained plating layer pushes the side surface of the resist, and the cross-sectional shape of the wiring becomes a drum shape as shown in FIG.

配線パターンの形成後、水酸化ナトリウムを主とする剥離剤によるフォトレジストの剥離を行うが、このような太鼓型の断面形状の配線では、配線パターンが細く、かつ高密度である場合には、例えば特許文献２，３に記載されているような従来の剥離剤によっては、レジスト残渣が生じ易くなってしまう。  After the wiring pattern is formed, the photoresist is peeled off using a release agent mainly composed of sodium hydroxide.In such a drum-shaped wiring, the wiring pattern is thin and dense, For example, depending on conventional stripping agents as described in Patent Documents 2 and 3, a resist residue is likely to occur.

このレジスト残渣の問題を解決するために、近年、水酸化ナトリウムに代わり、アミン系の剥離剤を用いてフォトレジストを剥離する方法が用いられ始め、これにより微細な配線パターンの形成が期待されている。  In order to solve this resist residue problem, a method of stripping a photoresist using an amine-based stripping agent instead of sodium hydroxide has recently started to be used, which is expected to form a fine wiring pattern. Yes.

この方法は、微細な配線パターンを形成する上で優れている。しかし、使用する剥離剤が従来の剥離剤に比べて５〜１０倍の価格であること、剥離剤自体が危険であることなどのデメリットもあるため、従来の剥離剤でも良好な剥離性が得られる方法が求められている。  This method is excellent in forming a fine wiring pattern. However, there are also disadvantages such as the release agent used is 5 to 10 times more expensive than conventional release agents, and the release agent itself is dangerous. There is a need for a method that can be used.

また、例えば配線形成を行った後に、レジスト残渣をより効果的に除去するために、レジスト除去工程とその後の水洗工程において超音波を用いる方法も提案されている(例えば、特許文献４参照)。しかし、この方法では、従来の方法より工程数が増え、製造コストが増加してしまう。
特開平０８−１８１４０２号公報 ＷＯ０１−０９２９５８号公報 特開平１１−２１４５７２号公報 特開平０５−１９８９２７号公報 In addition, for example, a method of using ultrasonic waves in the resist removal step and the subsequent water washing step has been proposed in order to more effectively remove the resist residue after wiring formation (see, for example, Patent Document 4). However, in this method, the number of steps increases as compared with the conventional method, and the manufacturing cost increases.
Japanese Patent Laid-Open No. 08-181402 WO01-092958 JP-A-11-214572 JP 05-198927 A

以上のように、レジスト残渣の問題を、安価な水酸化ナトリウムのような剥離剤を用い、工程数を増やすことなく解決することが求められている。  As described above, it is required to solve the problem of resist residues without increasing the number of steps by using an inexpensive stripping agent such as sodium hydroxide.

本発明は、以上のような事情の下になされ、レジストの剥離を容易に行うことができる形状の配線層を容易に形成することを可能とした配線基板の製造方法を提供することを目的とする。  An object of the present invention is to provide a method of manufacturing a wiring board which can be easily formed with a wiring layer having a shape capable of easily performing resist peeling under the circumstances as described above. To do.

上記課題を解決するため、本発明は、絶縁層上に通電層を形成する工程と、前記通電層上にパターン用マスクを形成する工程と、前記通電層上の前記パターン用マスクで覆われていない領域に、電流方向を周期的に反転させて行うＰＲ電解メッキ処理により導体層を形成する工程とを備え、前記ＰＲ電解メッキ処理における正電流ＩＦと逆電流ＩＲの電流比（ＩＦ／ＩＲ）は、１：３〜１：１であり、前記導体層は、ほぼ長方形の断面形状を有することを特徴とする配線基板の製造方法を提供する。 In order to solve the above problems, the present invention is covered with a step of forming a conductive layer on an insulating layer, a step of forming a pattern mask on the conductive layer, and the pattern mask on the conductive layer. the area without, and forming a conductive layer by PR electrolytic plating process performed by the current direction periodically reverses, the current ratio of the positive current I F and the reverse current I R in the PR electrolytic plating process (I F / I R ) is 1: 3 to 1: 1, and the conductor layer has a substantially rectangular cross-sectional shape.

以上のように構成される回路基板の製造方法において、ＰＲ電解メッキ処理における正電流の通電時間ＴＦと逆電流の通電時間ＴＲの比（ＴＦ／ＴＲ）は、５：１〜５０：１であることが望ましい。   In the method of manufacturing a circuit board configured as described above, the ratio (TF / TR) of the energizing time TR of the positive current and the energizing time TR of the reverse current in the PR electroplating process is 5: 1 to 50: 1. It is desirable.

本発明の配線基板の製造方法によると、導体層と前記パターン用マスクの厚さを、ほぼ同一とすることができる。また、パターン用マスクの幅を、８μｍ以下とすることができる。  According to the method for manufacturing a wiring board of the present invention, the thickness of the conductor layer and the pattern mask can be made substantially the same. Further, the width of the pattern mask can be 8 μm or less.

本発明によれば、ＰＲ電解メッキ処理における正電流ＩＦと逆電流ＩＲの電流比（ＩＦ／ＩＲ）を、１：３〜１：１に制御することにより、ほぼ長方形の断面形状を有する導体層を得ることができ、そのため、従来の太鼓型の断面形状の導体層の場合に比べ、例えば水酸化ナトリウム水溶液などの通常の剥離剤によっても容易にパターン用マスクを剥離することができる。 According to the present invention, the current ratio of the positive current I F and the reverse current I R in the PR electroplating processes (I F / I R), 1: 3~1: By controlling the 1, substantially rectangular cross-sectional shape As a result, the pattern mask can be easily peeled off with a normal stripper such as an aqueous solution of sodium hydroxide, as compared with the case of a conventional drum-shaped conductor layer having a cross-sectional shape. it can.

また、３０μm以下の狭いピッチでの銅配線を形成する場合に剥離液として水酸化ナトリウムを用いても、レジスト残渣の問題がなく、配線形成を行うことが可能である。  Further, when copper wiring is formed at a narrow pitch of 30 μm or less, even if sodium hydroxide is used as a stripping solution, there is no problem of resist residue, and wiring can be formed.

以下、発明を実施するための最良の形態について説明する。   The best mode for carrying out the invention will be described below.

本発明の一態様に係る配線基板の製造方法は、セミアディティブ法により配線を形成するに際し、電流の極性を反転させて電解めっきを行うＰＲ(periodic reverse)法を用い、その電解めっき条件として、正電流ＩＦと逆電流ＩＲの電流比（ＩＦ／ＩＲ）を１：３〜１：１とすることを特徴とする。 The method for manufacturing a wiring board according to an aspect of the present invention uses a PR (periodic reverse) method in which electrolytic plating is performed by reversing the polarity of a current when forming a wiring by a semi-additive method. current ratio of the positive current I F and the reverse current I R a (I F / I R) 1 : 3~1: characterized by one.

このように、ＩＦ／ＩＲを制御して電解めっきを行うことにより、ほぼ長方形の断面形状を有する配線層を形成することができる。そして、長方形の断面形状を有する配線層を形成することにより、電解めっき後のパターン用マスク（レジストパターン）の除去を、レジスト残渣が残ることなく確実に行うことができる。従って、高価な剥離剤を用いることなく、水酸化ナトリウム等の従来用いられている通常の剥離剤によっても、何ら支障なくパターン用マスクの除去を行うことができる。 Thus, by performing electrolytic plating by controlling the I F / I R, it is possible to form a wiring layer having a substantially rectangular cross-sectional shape. Then, by forming a wiring layer having a rectangular cross-sectional shape, it is possible to reliably remove the pattern mask (resist pattern) after electrolytic plating without leaving a resist residue. Therefore, the pattern mask can be removed without any trouble by using a conventionally used normal release agent such as sodium hydroxide without using an expensive release agent.

ＩＦ／ＩＲが上記範囲を外れ、ＩＦ／ＩＲが１：１よりも大きくなる場合には、太鼓型ないしドーム型の断面形状の配線となり、パターン用マスクの除去が困難となり、逆に、ＩＦ／ＩＲが１：３よりも小さくなる場合には、側面が傾斜して、台形型の断面形状の配線となる。 I F / I R is outside the above range, I F / I R 1: if greater than 1 becomes a drum-type or dome-shaped cross section of the wiring, it is difficult to remove the pattern mask, the reverse a, I F / I R 1: if smaller than 3, and side surfaces inclined, a trapezoidal cross-sectional shape of the wiring.

ＰＲ電解メッキ処理における正電流の通電時間ＴＦと逆電流の通電時間ＴＲの比（ＴＦ／ＴＲ）は、５：１〜５０：１であることが望ましい。ＴＦ／ＴＲがこの範囲より大きい場合には、配線形状はドーム型となり、小さい場合には、形状は上記のいずれかをとることができるが、めっき表面にざらつきなどを生じ、使用できない。 The ratio of the energization time T R of the positive current supply time T F and the reverse current of the PR electroplating treatment (T F / T R) is 5: 1 to 50: most preferably 1. If T F / T R is greater than this range, the wiring form becomes dome-shaped, if small, shape may take any of the above, produce such as roughness on the plated surface, can not be used.

本発明の一態様に係る配線基板の製造方法によると、パターン用マスクの厚さが従来よりも薄くても、所定の高さの導体層を形成することができ、例えば、導体層と前記パターン用マスクの厚さを、ほぼ同一とすることができる。このようにパターン用マスクの厚さを薄くすることにより、微細な、例えば８μｍ以下の幅のパターン用マスクを形成することができる。  According to the method for manufacturing a wiring board according to one aspect of the present invention, a conductive layer having a predetermined height can be formed even if the thickness of the pattern mask is thinner than the conventional one. For example, the conductive layer and the pattern The thickness of the masks for use can be made substantially the same. By reducing the thickness of the pattern mask in this way, a fine pattern mask having a width of, for example, 8 μm or less can be formed.

以下、図面を参照して、本発明の実施形態について説明する。  Embodiments of the present invention will be described below with reference to the drawings.

第１の実施形態
図１は、本発明の第１の実施形態に係る配線基板の製造方法を工程順に示す断面図である。まず、図１（ａ）に示すように、回路基板（図示せず）上に形成された絶縁層１上に、めっきリードとなるシード層２を形成するとともに、フォトレジストをラミネートおよび露光・現像処理することにより、シード層２の不要部分をマスキングするレジストパターン３を形成した。 First Embodiment FIG. 1 is a cross-sectional view showing a method of manufacturing a wiring board according to a first embodiment of the present invention in the order of steps. First, as shown in FIG. 1A, a seed layer 2 serving as a plating lead is formed on an insulating layer 1 formed on a circuit board (not shown), and a photoresist is laminated, exposed and developed. By processing, a resist pattern 3 for masking unnecessary portions of the seed layer 2 was formed.

図１（ａ）で用いている回路基板は一般的なもので良く、絶縁層１としては、エポキシ樹脂、ＢＴレジン、ポリイミド樹脂など、通常用いられる材料を用いることができる。なお、本実施形態では、絶縁層１としてポリイミド樹脂を用いた。シード層２としては、絶縁層１上に直接無電解銅めっきにより１μｍ程度の厚みで析出させた銅を用いた。  The circuit board used in FIG. 1A may be a general one, and the insulating layer 1 may be a commonly used material such as an epoxy resin, a BT resin, or a polyimide resin. In the present embodiment, a polyimide resin is used as the insulating layer 1. As the seed layer 2, copper deposited on the insulating layer 1 with a thickness of about 1 μm by electroless copper plating was used.

直流（ＤＣ）電解めっきを用いたセミアディティブ法では、一般的に１５μｍ厚の銅めっきの層を得るために必要なフォトレジストの厚さは約２５μｍであるが、このレジスト厚では、フォトレジストの解像限界は１０μｍ幅以上になってしまう。ＰＲ法を用いる本発明の方法では、１５μｍの銅めっきの層に対してフォトレジストの厚さを１５μｍまで薄くすることができ、解像限界も６μｍ幅まで小さくすることができるため、微細配線の形成において有利となる。  In the semi-additive method using direct current (DC) electrolytic plating, the thickness of the photoresist required to obtain a copper plating layer having a thickness of 15 μm is generally about 25 μm. The resolution limit is 10 μm or more. In the method of the present invention using the PR method, the thickness of the photoresist can be reduced to 15 μm and the resolution limit can be reduced to 6 μm with respect to the 15 μm copper plating layer. It is advantageous in forming.

次に、図１（ｂ）に示すように、レジストパターン３の開口部内にＰＲ法による電解銅めっきにより、所望の厚さの回路配線４を形成した。なお、ＰＲ法による電解銅めっきの条件は、下記の通りである。  Next, as shown in FIG. 1B, a circuit wiring 4 having a desired thickness was formed in the opening of the resist pattern 3 by electrolytic copper plating by the PR method. The conditions for electrolytic copper plating by the PR method are as follows.

正電流
電流値：２Ａ／ｄｍ２
時間：２０ｍｓｅｃ
逆電流
電流値：２Ａ／ｄｍ２
時間：１ｍｓｅｃ
以上の条件で得られた銅めっき厚は、１５μｍであった。 Positive current Current value: 2 A / dm 2
Time: 20msec
Reverse current Current value: 2 A / dm 2
Time: 1msec
The copper plating thickness obtained under the above conditions was 15 μm.

次いで、図１（ｃ）に示すように、剥離液として水酸化ナトリウムを用いてレジストパターン３の剥離を行った。本実施形態の場合、配線の断面形状が長方形であるため、めっき銅の間のフォトレジスト残渣が残りにくくなるという利点がある。  Next, as shown in FIG. 1C, the resist pattern 3 was peeled off using sodium hydroxide as a peeling solution. In the case of the present embodiment, since the cross-sectional shape of the wiring is rectangular, there is an advantage that the photoresist residue between the plated coppers hardly remains.

その後、クイックエッチングを行い、露出するシード層２を除去することにより、図１（ｄ）に示すように、長方形の断面形状を有する配線回路配線４を得た。なお、クイックエッチングは、硫酸過水（硫酸と過酸化水素水との混合液）系のエッチング液を用いた。  Thereafter, quick etching was performed to remove the exposed seed layer 2 to obtain a wiring circuit wiring 4 having a rectangular cross-sectional shape as shown in FIG. In addition, the quick etching used the sulfuric acid perwater (mixed liquid of sulfuric acid and hydrogen peroxide water) type etching liquid.

このように、ＰＲ法を用いて形成した回路配線４の断面形状を図２に示す。  The cross-sectional shape of the circuit wiring 4 formed by using the PR method is shown in FIG.

図２に示すように、回路配線の断面形状は長方形であり、図１１に示す従来のＤＣ法によって形成された太鼓型の断面形状の配線とは大きく異なっていることがわかる。  As shown in FIG. 2, it can be seen that the cross-sectional shape of the circuit wiring is rectangular, which is greatly different from the drum-shaped cross-sectional wiring formed by the conventional DC method shown in FIG.

第２の実施形態
次に、本発明を半導体パッケージ基板の製造に適用した第２の実施形態について説明する。 Second Embodiment Next, a second embodiment in which the present invention is applied to the manufacture of a semiconductor package substrate will be described.

まず、図３（ａ）に示すように、基材として２５μｍ厚のポリイミド樹脂層１１の両面に６μｍ厚の銅箔１２ａ，１２ｂを被覆した基材を用意した。次いで、図３（ｂ）に示すように、この基材の一方の面に対し、レーザーを用いて穴あけ加工を行い、ビア１３を形成した。その後、ビア加工において発生したスミアを除去するためデスミア処理を行った後、無電解銅めっきを行い、ビアの内側に給電層（図示せず）を形成した。  First, as shown in FIG. 3A, a base material in which 6 μm thick copper foils 12a and 12b were coated on both sides of a 25 μm thick polyimide resin layer 11 was prepared as a base material. Next, as shown in FIG. 3B, drilling was performed on one surface of the base material using a laser to form a via 13. Thereafter, desmear treatment was performed to remove smear generated in via processing, and then electroless copper plating was performed to form a power feeding layer (not shown) inside the via.

次に、図３（ｃ）に示すように、ビアフィリングめっきにより、ビア１３の内部を銅めっきで充填して、フィルドビア１４とすると共に銅箔１２ａ，１２ｂ上にもめっきを行い、シード層１２ａ’，１２ｂ’とした。その後、シード層１２ａ’，１２ｂ’の上にレジスト１５ａ，１５ｂをラミネーターにより貼付した。そして、レジスト１５ａ，１５ｂに対し、露光及び現像を行い、図３（ｄ）に示すように、レジストパターン１６ａ，１６ｂを形成した。  Next, as shown in FIG. 3C, the inside of the via 13 is filled with copper plating by via filling plating to form a filled via 14 and plating is also performed on the copper foils 12a and 12b to form the seed layer 12a. ', 12b'. Thereafter, resists 15a and 15b were stuck on the seed layers 12a 'and 12b' by a laminator. The resists 15a and 15b were exposed and developed to form resist patterns 16a and 16b as shown in FIG.

その後、ＰＲ法により銅の電解めっきを行い、図４（ａ）に示すように、銅の配線層１７ａ，１７ｂを形成した。次いで、図４（ｂ）に示すように、レジストパターン１６ａ，１６ｂを剥離し、クイックエッチングを行い、図４（ｃ）に示すように、シード層１２ａ’，１２ｂ’の露出する部分を除去した。  Thereafter, copper electroplating was performed by the PR method to form copper wiring layers 17a and 17b as shown in FIG. Next, as shown in FIG. 4B, the resist patterns 16a and 16b are peeled off, quick etching is performed, and exposed portions of the seed layers 12a ′ and 12b ′ are removed as shown in FIG. 4C. .

次に、得られた構造の両面に、接着剤層１８ａ，１８ｂを介して、片面銅箔基材１９ａ，１９ｂを同時に貼り合わせ、図５（ａ）に示すように、４層板を形成した。片面銅箔基材１９ａ，１９ｂはそれぞれポリイミド樹脂層１９１ａ，１９１ｂと銅箔１９２ａ，１９２ｂを備えている。  Next, single-sided copper foil base materials 19a and 19b were simultaneously bonded to both sides of the obtained structure via adhesive layers 18a and 18b, and a four-layer plate was formed as shown in FIG. 5 (a). . The single-sided copper foil base materials 19a and 19b include polyimide resin layers 191a and 191b and copper foils 192a and 192b, respectively.

次いで、図５（ｂ）に示すように、この４層板の両面に対し、レーザーを用いて穴あけ加工を行い、ビア２０ａ，２０ｂを形成した。  Next, as shown in FIG. 5B, holes were drilled using a laser on both sides of the four-layer plate to form vias 20a and 20b.

その後、図６（ａ）に示すように、デスミア処理、無電解銅めっきの後、ビアフィリングめっきを行い、ビア２０ａ，２０ｂの内部を銅めっきで充填してフィルドビア２１ａ，２１ｂとすると共に銅箔１９２ａ，１９２ｂ上にもめっきを行い、シード層１９２ａ’，１９２ｂ’とした。その後、シード層１９２ａ’，１９２ｂ’の上にレジスト（図示せず）を貼付し、露光、現像を行い、レジストパターン２２ａ，２２ｂを形成した。  After that, as shown in FIG. 6A, after desmearing and electroless copper plating, via filling plating is performed to fill the vias 20a and 20b with copper plating to form filled vias 21a and 21b and copper foil. Plating was also performed on 192a and 192b to form seed layers 192a ′ and 192b ′. Thereafter, a resist (not shown) was stuck on the seed layers 192a 'and 192b', and exposure and development were performed to form resist patterns 22a and 22b.

その後、ＰＲ法により銅の電解めっきを行い、レジストパターン２２ａ，２２ｂを剥離し、クイックエッチングを行って露出する銅箔を除去し、図６（ｂ）に示すように、銅の配線層２３ａ，２３ｂを形成した。  Thereafter, copper electroplating is performed by the PR method, the resist patterns 22a and 22b are peeled off, and the exposed copper foil is removed by performing a quick etching. As shown in FIG. 23b was formed.

図面では省略したが、同様にして、片面銅箔基材の貼り付け、配線層の形成を繰り返し、６層や８層の多層配線基板を形成した。  Although omitted in the drawings, a single-sided copper foil base material and wiring layer formation were repeated in the same manner to form a 6-layer or 8-layer multilayer wiring board.

そして、図７に示すように、最外層にソルダーレジスト２４ａ，２４ｂを形成し、図８に示すように、その開口部にＮｉ／金めっき層２５ａ，２５ｂを形成した。次いで、図９に示すように、Ｎｉ／金めっき層２５ｂにはんだバンプ２６を形成し、半導体パッケージ基板を得た。  Then, as shown in FIG. 7, solder resists 24a and 24b were formed in the outermost layer, and as shown in FIG. 8, Ni / gold plating layers 25a and 25b were formed in the openings. Next, as shown in FIG. 9, solder bumps 26 were formed on the Ni / gold plating layer 25b to obtain a semiconductor package substrate.

このような半導体パッケージ基板を用いた、電子部品の一形態の模式図を図１０に示す。   FIG. 10 shows a schematic diagram of an embodiment of an electronic component using such a semiconductor package substrate.

次に、本発明者らは、PR法による電解めっきにおける条件として、正電流と逆電流の比（ＩＦ／ＩＲ）及び時間の比（ＴＦ／ＴＲ）を種々変化させて、銅のめっきを行い、配線を形成した。その結果、得られた配線の断面形状は、下記表に示す通りとなった。

Figure 2007335803
Next, the present inventors changed the ratio of positive current to reverse current (I F / I R ) and the ratio of time (T F / T R ) as conditions in electrolytic plating by the PR method, Then, wiring was formed. As a result, the cross-sectional shape of the obtained wiring was as shown in the following table.
Figure 2007335803

上記表から、ＩＦ／ＩＲが１：１、ＴＦ／ＴＲが１０：１のときに、長方形の断面形状が得られることがわかる。一方、ＩＦ／ＩＲが１：２、ＴＦ／ＴＲが１０：１では、断面形状は台形となり、ＩＦ／ＩＲが１：５、ＴＦ／ＴＲが１０：１では、断面形状はＭ形となり、正電流のみを流した場合には、断面形状はドーム型となった。 From Table, I F / I R is 1: 1, T F / T R 10: when 1, it can be seen that the rectangular cross-sectional shape is obtained. On the other hand, I F / I R is 1: 2, T F / T R 10: In 1, the cross-sectional shape becomes a trapezoid, I F / I R is 1: 5, T F / T R 10: In 1, The cross-sectional shape was M-shaped, and when only a positive current was passed, the cross-sectional shape was a dome shape.

なお、例１及び２の長方形及び台形の断面形状では、中央部分の膜厚が周辺部と比較して±０．５μｍ以内であり、例３のＭ形の断面形状では、中央部分の膜厚が周辺部と比較して０．５μｍ以上低く、例４のドーム形の断面形状では、中央部分の膜厚が周辺部と比較して０．５μｍ以上高い結果が得られた。  In the rectangular and trapezoidal cross-sectional shapes of Examples 1 and 2, the thickness of the central portion is within ± 0.5 μm compared to the peripheral portion, and in the M-shaped cross-sectional shape of Example 3, the thickness of the central portion is Was lower by 0.5 μm or more than the peripheral part, and in the dome-shaped cross-sectional shape of Example 4, the result was that the film thickness of the central part was higher by 0.5 μm or more than the peripheral part.

本発明の第１の実施形態に係る配線基板の製造方法を工程順に示す断面図である。It is sectional drawing which shows the manufacturing method of the wiring board which concerns on the 1st Embodiment of this invention in order of a process. 本発明の第１の実施形態に係る配線基板の製造方法により得た配線の断面を示す写真図である。It is a photograph figure which shows the cross section of the wiring obtained by the manufacturing method of the wiring board which concerns on the 1st Embodiment of this invention. 本発明の第２の実施形態に係る半導体パッケージ基板の製造方法を工程順に示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor package substrate which concerns on the 2nd Embodiment of this invention in process order. 本発明の第２の実施形態に係る半導体パッケージ基板の製造方法を工程順に示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor package substrate which concerns on the 2nd Embodiment of this invention in process order. 本発明の第２の実施形態に係る半導体パッケージ基板の製造方法を工程順に示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor package substrate which concerns on the 2nd Embodiment of this invention in process order. 本発明の第２の実施形態に係る半導体パッケージ基板の製造方法を工程順に示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor package substrate which concerns on the 2nd Embodiment of this invention in process order. 本発明の第２の実施形態に係る半導体パッケージ基板の製造方法を工程順に示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor package substrate which concerns on the 2nd Embodiment of this invention in process order. 本発明の第２の実施形態に係る半導体パッケージ基板の製造方法を工程順に示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor package substrate which concerns on the 2nd Embodiment of this invention in process order. 本発明の第２の実施形態に係る半導体パッケージ基板の製造方法を工程順に示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor package substrate which concerns on the 2nd Embodiment of this invention in process order. 本発明の第２の実施形態に係る方法により得た半導体パッケージ基板を示す断面図である。It is sectional drawing which shows the semiconductor package board | substrate obtained by the method concerning the 2nd Embodiment of this invention. 従来の直流（ＤＣ）電流によるめっき法により得た配線の断面を示す写真図である。It is a photograph figure which shows the cross section of the wiring obtained by the plating method by the conventional direct current (DC) electric current.

符号の説明Explanation of symbols

１…絶縁層、２，１２ａ’，１２ｂ’，１９２ａ’，１９２ｂ’…シード層、３，１６ａ，１６ｂ，２２ａ，２２ｂ…レジストパターン、４，１７ａ，１７ｂ，２３ａ，２３ｂ…配線層、１１，１９１ａ，１９１ｂ…ポリイミド樹脂層、１２ａ，１２ｂ，１９２ａ，１９２ｂ…銅箔、１３，２０ａ，２０ｂ…ビア、１４，２１ａ，２１ｂ…フィルドビア、１５ａ，１５ｂ…レジスト、１８ａ，１８ｂ…接着剤層、１９ａ，１９ｂ…片面銅箔基材、２４ａ，２４ｂ…ソルダーレジスト、２５ａ，２５ｂ…Ｎｉ／金めっき層、２６…はんだバンプ。  DESCRIPTION OF SYMBOLS 1 ... Insulating layer, 2, 12a ', 12b', 192a ', 192b' ... Seed layer, 3, 16a, 16b, 22a, 22b ... Resist pattern, 4, 17a, 17b, 23a, 23b ... Wiring layer, 11, 191a, 191b ... polyimide resin layer, 12a, 12b, 192a, 192b ... copper foil, 13, 20a, 20b ... via, 14, 21a, 21b ... filled via, 15a, 15b ... resist, 18a, 18b ... adhesive layer, 19a , 19b: single-sided copper foil base material, 24a, 24b ... solder resist, 25a, 25b ... Ni / gold plating layer, 26 ... solder bumps.

Claims (4)

絶縁層上に通電層を形成する工程と、
前記通電層上にパターン用マスクを形成する工程と、
前記通電層上の前記パターン用マスクで覆われていない領域に、電流方向を周期的に反転させて行うＰＲ電解メッキ処理により導体層を形成する工程と
を備え、
前記ＰＲ電解メッキ処理における正電流ＩＦと逆電流ＩＲの電流比（ＩＦ／ＩＲ）は、１：３〜１：１であり、前記導体層は、ほぼ長方形の断面形状を有することを特徴とする配線基板の製造方法。 Forming a conductive layer on the insulating layer;
Forming a pattern mask on the conductive layer;
Forming a conductor layer by PR electrolytic plating performed by periodically reversing the current direction in a region not covered with the pattern mask on the conductive layer, and
Current ratio of the positive current I F and the reverse current I R in the PR electrolytic plating process (I F / I R) is 1: 3 to 1: 1, the conductor layer may have a substantially rectangular cross-sectional shape A method of manufacturing a wiring board characterized by the above. 前記ＰＲ電解メッキ処理における正電流の通電時間ＴＦと逆電流の通電時間ＴＲの比（ＴＦ／ＴＲ）は、５：１〜５０：１であることを特徴とする請求項１に記載の配線基板の製造方法。 The ratio of the energization time T R of the PR conduction time of the positive current in the electrolytic plating process T F and the reverse current (T F / T R) is 5: 1 to 50: to claim 1, characterized in that one The manufacturing method of the wiring board as described. 前記導体層と前記パターン用マスクの厚さは、ほぼ同一であることを特徴とする請求項１または２に記載の配線基板の製造方法。  The method for manufacturing a wiring board according to claim 1, wherein the conductor layer and the pattern mask have substantially the same thickness. 前記パターン用マスクの幅は、８μｍ以下であることを特徴とする請求項１〜３のいずれかに記載の配線基板の製造方法。   The width of the said pattern mask is 8 micrometers or less, The manufacturing method of the wiring board in any one of Claims 1-3 characterized by the above-mentioned.
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JP2017034279A (en) * 2016-10-31 2017-02-09 京セラ株式会社 Wiring board manufacturing method

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JP2002076591A (en) * 2000-08-28 2002-03-15 Matsushita Electric Works Ltd Printed wiring board and its producing method
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JP2009272571A (en) * 2008-05-09 2009-11-19 Mitsui Mining & Smelting Co Ltd Printed circuit board and method of manufacturing the same
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JP2015026775A (en) * 2013-07-29 2015-02-05 京セラサーキットソリューションズ株式会社 Wiring board
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