JP2002184942A - Mounting board - Google Patents
Mounting boardInfo
- Publication number
- JP2002184942A JP2002184942A JP2000378933A JP2000378933A JP2002184942A JP 2002184942 A JP2002184942 A JP 2002184942A JP 2000378933 A JP2000378933 A JP 2000378933A JP 2000378933 A JP2000378933 A JP 2000378933A JP 2002184942 A JP2002184942 A JP 2002184942A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- face
- circuit board
- external circuit
- type semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、実装基板に関し、
特に、半導体素子を有する半導体装置が外部回路基板の
両面に実装された実装基板に関するものである。TECHNICAL FIELD The present invention relates to a mounting board,
In particular, the present invention relates to a mounting board in which a semiconductor device having a semiconductor element is mounted on both sides of an external circuit board.
【０００２】[0002]
【従来技術】近年、半導体素子の高速化および高集積
化、ならびに携帯機器の急速な普及に伴い、電子機器の
小型、軽量化の要求が高まっており、半導体素子や電子
部品の高密度実装技術の開発が進められているが、電子
機器の内部の実装面積は限られており、伝送速度に関す
る考慮から半導体素子同士を近接して設置することが要
求され、よりコンパクトな実装技術が必要となってい
る。2. Description of the Related Art In recent years, with the increase in speed and integration of semiconductor devices and the rapid spread of portable devices, there has been an increasing demand for smaller and lighter electronic devices, and high-density mounting technology for semiconductor devices and electronic components. However, the mounting area inside an electronic device is limited, and it is required to install semiconductor elements close to each other in consideration of transmission speed, and more compact mounting technology is required. ing.
【０００３】近年、高密度実装に対応した配線基板とし
て、配線基板の下面にハンダや導電性接着剤からなる接
合剤を格子状に配置したボールグリッドアレイパッケー
ジ（ＢＧＡ）や、ＢＧＡをより小型化したチップスケー
ルパッケージ（ＣＳＰ）が用いられている。In recent years, as a wiring board corresponding to high-density mounting, a ball grid array package (BGA) in which a bonding agent made of solder or a conductive adhesive is arranged in a lattice pattern on the lower surface of the wiring board, or a BGA having a smaller size. A chip scale package (CSP) is used.
【０００４】そして、これらのＢＧＡやＣＳＰには、図
７（ａ）に示すようなフェイスアップ型半導体装置６１
や、図７（ｂ）に示すようなフェイスダウン型半導体装
置６３が知られており、半導体素子６５の放熱方式や、
接地電源線の強化等による配線設計のちがいによって区
別して用いられている。[0004] These BGA and CSP have a face-up type semiconductor device 61 as shown in FIG.
Further, a face-down type semiconductor device 63 as shown in FIG.
It is used differently depending on the difference in wiring design due to reinforcement of the ground power supply line and the like.
【０００５】このフェイスアップ型半導体装置６１は、
一般に図７（ａ）に示すように、半導体素子６５の搭載
面と反対側の配線基板６７の面に接合剤６９が設けられ
ており、これらの接合剤６９を介してフェイスアップ型
半導体装置６１が外部回路基板７１に接合されている。
一方、フェイスダウン型半導体装置６３は、一般に図７
（ｂ）に示すように、半導体素子６５の搭載面と同じ側
の配線基板６７の面に接合剤６９が設けられており、こ
れらの接合剤６９を介して配線基板６７が外部回路基板
７１に接合されている。これらの半導体装置６１、６３
は、表面実装が可能で、伝送速度および放熱性も良好で
ある。[0005] This face-up type semiconductor device 61
Generally, as shown in FIG. 7A, a bonding agent 69 is provided on the surface of the wiring board 67 opposite to the mounting surface of the semiconductor element 65, and the face-up type semiconductor device 61 is provided via these bonding agents 69. Are joined to the external circuit board 71.
On the other hand, the face-down type semiconductor device 63 is generally
As shown in (b), a bonding agent 69 is provided on the surface of the wiring board 67 on the same side as the mounting surface of the semiconductor element 65, and the wiring substrate 67 is connected to the external circuit board 71 via these bonding agents 69. Are joined. These semiconductor devices 61 and 63
Can be surface-mounted and have good transmission speed and heat dissipation.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、従来、
外部回路基板７１の片側だけに半導体装置６１、６３を
実装していたので、実装密度に限界があった。そこで、
外部回路基板７１への実装密度を向上するには、半導体
装置６１、６３を外部回路基板７１の両面に実装するこ
とが考えられる。However, conventionally,
Since the semiconductor devices 61 and 63 are mounted on only one side of the external circuit board 71, the mounting density is limited. Therefore,
In order to improve the mounting density on the external circuit board 71, it is conceivable to mount the semiconductor devices 61 and 63 on both sides of the external circuit board 71.
【０００７】このように、外部回路基板７１の両面に表
面実装型の半導体装置６１、６３を実装すると、半導体
装置６１、６３や電子部品の実装密度を高めることがで
きるとともに、従来の片面にのみ実装した場合よりも、
半導体装置６１、６３間の配線長を短縮できることか
ら、半導体素子６５の駆動回路から発信される伝送速度
の高速化を図ることができる。As described above, when the surface-mounted semiconductor devices 61 and 63 are mounted on both surfaces of the external circuit board 71, the mounting density of the semiconductor devices 61 and 63 and the electronic components can be increased, and only the conventional single-sided device can be mounted. Rather than implementing
Since the wiring length between the semiconductor devices 61 and 63 can be reduced, the transmission speed transmitted from the drive circuit of the semiconductor element 65 can be increased.
【０００８】しかしながら、ＢＧＡやＣＳＰに半導体素
子６５を搭載した半導体装置６１、６３を、ガラス−エ
ポキシ樹脂複合材料やガラス−ポリイミド樹脂複合材料
などの有機樹脂を含む外部回路基板７１の両側に単に実
装しただけでは、使用環境、半導体素子６５の駆動と停
止に伴う発熱、冷却の繰返しによって、外部回路基板７
１と半導体装置６１、６３との接続性が損なわれ、従来
の片面実装型の実装基板に比べて、長期にわたり安定な
接続を維持できないという問題がある。However, the semiconductor devices 61 and 63 having the semiconductor element 65 mounted on a BGA or CSP are simply mounted on both sides of an external circuit board 71 containing an organic resin such as a glass-epoxy resin composite material or a glass-polyimide resin composite material. If only this is done, the use environment, the heat generated by driving and stopping the semiconductor element 65, and the repetition of cooling will cause the external circuit board 7
There is a problem that the connectivity between the semiconductor device 1 and the semiconductor devices 61 and 63 is impaired, and a stable connection cannot be maintained for a long time as compared with a conventional single-sided mounting substrate.
【０００９】これは主として半導体装置６１、６３を構
成する配線基板６７と外部回路基板７１との熱膨張係数
差に起因する熱応力が接合剤６９に繰り返し作用するこ
とにより、接合剤６９が疲労し、最終的にクラックが発
生するためと考えられる。[0009] This is mainly because the thermal stress caused by the difference in thermal expansion coefficient between the wiring board 67 and the external circuit board 71 constituting the semiconductor devices 61 and 63 repeatedly acts on the bonding agent 69, and the bonding agent 69 becomes fatigued. It is considered that cracks eventually occur.
【００１０】しかるに、半導体装置６１、６３が外部回
路基板７１の片面にのみ実装される方式であれば、実装
基板の剛性はさほど高くないため、配線基板６７の反り
によって熱膨張差を緩和することができるが、両面に半
導体装置６１、６３を積層した実装基板では、実装基板
全体の剛性が高いため、反りによって熱膨張差を緩和す
ることができず、熱応力による接合剤６９の熱疲労破壊
が発生しやすいという問題があった。However, if the semiconductor devices 61 and 63 are mounted on only one surface of the external circuit board 71, the rigidity of the mounting board is not so high. However, in a mounting substrate in which the semiconductor devices 61 and 63 are stacked on both surfaces, the rigidity of the entire mounting substrate is high, so that the difference in thermal expansion cannot be reduced due to the warpage, and the thermal stress causes thermal fatigue fracture of the bonding agent 69 due to thermal stress. There is a problem that is easy to occur.
【００１１】従って、本発明は、外部回路基板の両面に
半導体装置を実装しても、外部回路基板との電気的接続
性に優れ、信頼性の高い実装基板を提供することを目的
とする。Accordingly, an object of the present invention is to provide a highly reliable mounting board which has excellent electrical connectivity with the external circuit board even when semiconductor devices are mounted on both surfaces of the external circuit board.
【００１２】[0012]
【課題を解決するための手段】本発明の実装基板では、
配線基板に半導体素子を搭載してなる半導体装置を、外
部回路基板の対向する主面に、それぞれ接合剤により実
装してなるとともに、前記外部回路基板の一方主面に実
装された半導体装置がフェイスアップ型半導体装置とさ
れ、他方主面に実装された半導体装置がフェイスダウン
型半導体装置とされていることを特徴とするものであ
る。According to the mounting board of the present invention,
A semiconductor device having a semiconductor element mounted on a wiring board is mounted on an opposing main surface of an external circuit board with a bonding agent, respectively, and the semiconductor device mounted on one main surface of the external circuit board has a face. The semiconductor device is an up-type semiconductor device, and the semiconductor device mounted on the other main surface is a face-down semiconductor device.
【００１３】一般に、配線基板の半導体素子側の面が、
半導体素子を固着していない面よりも熱膨張が小さいた
め、フェイスアップ型半導体装置は外部回路基板に対し
て凸状に変形し、一方、フェイスダウン型半導体装置は
外部回路基板に対して凹状に変形することにより、外部
回路基板の両面に対向して実装された半導体装置を同じ
方向に反り変形させることができる。Generally, the surface of the wiring board on the semiconductor element side is
Since the thermal expansion is smaller than the surface on which the semiconductor element is not fixed, the face-up type semiconductor device deforms convexly with respect to the external circuit board, while the face-down type semiconductor device deforms concavely with respect to the external circuit board. Due to the deformation, the semiconductor devices mounted opposite to both surfaces of the external circuit board can be warped and deformed in the same direction.
【００１４】これにより、フェイスアップ型半導体装置
やフェイスダウン型半導体装置と、外部回路基板との間
に形成された接合剤に発生する応力を低減でき、ハンダ
等の接合剤の疲労断線を抑え、接続信頼性を飛躍的に向
上できる。Thus, the stress generated in the bonding agent formed between the face-up type semiconductor device or the face-down type semiconductor device and the external circuit board can be reduced, and the fatigue breakage of the bonding agent such as solder can be suppressed. Connection reliability can be dramatically improved.
【００１５】本発明の実装基板では、フェイスアップ型
半導体装置を構成する配線基板の熱膨張係数をα１、フ
ェイスダウン型半導体装置を構成する配線基板の熱膨張
係数をα２とした時、α２＞α１の関係を満足すること
が望ましい。In the mounting board of the present invention, when the thermal expansion coefficient of the wiring board constituting the face-up type semiconductor device is α1, and the thermal expansion coefficient of the wiring board constituting the face-down type semiconductor device is α2, α2> α1 It is desirable to satisfy the following relationship.
【００１６】このようにすることによって、外部回路基
板に対して凹変形するフェイスダウン型半導体装置の熱
膨張が、外部回路基板に対して凸変形するフェイスアッ
プ型半導体装置の熱膨張よりも大きくなり、フェイスダ
ウン型半導体装置の反り形状がフェイスアップ型半導体
装置の反り形状に追従しやすくなるため、外部回路基板
と半導体装置を接続している接合剤の熱膨張差による歪
や応力を、さらに小さくすることができ、外部回路基板
と半導体装置を接続している接合剤の接続信頼性をさら
に向上できる。By doing so, the thermal expansion of the face-down type semiconductor device that is concavely deformed with respect to the external circuit board is larger than the thermal expansion of the face-up type semiconductor device that is convexly deformed with respect to the external circuit board. Since the warped shape of the face-down type semiconductor device can easily follow the warped shape of the face-up type semiconductor device, the distortion and stress due to the difference in thermal expansion of the bonding agent connecting the external circuit board and the semiconductor device can be further reduced. The connection reliability of the bonding agent connecting the external circuit board and the semiconductor device can be further improved.
【００１７】本発明の実装基板では、外部回路基板の熱
膨張係数をα０としたときに、α２＞α０＞α１の関係
を満足することが望ましい。In the mounting board of the present invention, when the thermal expansion coefficient of the external circuit board is α0, it is desirable that the relationship α2>α0> α1 is satisfied.
【００１８】外部回路基板の熱膨張係数をフェイスダウ
ン型半導体装置とフェイスアップ型半導体装置との中間
の値とすることにより、外部回路基板を含めてフェイス
ダウン型半導体装置の反り形状が、さらにフェイスアッ
プ型半導体装置の反り形状に追従しやすくなるため、接
合剤の接続信頼性をさらに向上できる。By setting the coefficient of thermal expansion of the external circuit board to an intermediate value between the face-down type semiconductor device and the face-up type semiconductor device, the warped shape of the face-down type semiconductor device including the external circuit board further reduces the face. Since it becomes easier to follow the warped shape of the up-type semiconductor device, the connection reliability of the bonding agent can be further improved.
【００１９】本発明の実装基板では、フェイスアップ型
半導体装置の、外部回路基板と反対側の位置に放熱体を
設けるとともに、フェイスアップ型半導体装置を構成す
る配線基板の熱膨張係数をα１、外部回路基板の熱膨張
係数をα０、および放熱体の熱膨張係数をα３とした時
に、α０＞α１＞α３の関係を満足することが望まし
い。In the mounting board according to the present invention, a heat radiator is provided at a position of the face-up type semiconductor device opposite to the external circuit board, and the thermal expansion coefficient of the wiring board constituting the face-up type semiconductor device is α1, When the thermal expansion coefficient of the circuit board is α0 and the thermal expansion coefficient of the radiator is α3, it is desirable to satisfy the relationship α0>α1> α3.
【００２０】このような構成を採用することにより、放
熱体により半導体装置からの放熱性を向上できるととも
に、外部回路基板、フェイスアップ型半導体装置、放熱
体の熱膨張係数を、上記の順になるように小さくしたの
で、実装基板が放熱体を含めても、これら放熱体、半導
体装置および外部回路基板の反り形状をさらに近づける
ことができ、接合剤の接続信頼性を向上できる。By adopting such a configuration, the heat radiation from the semiconductor device can be improved by the heat radiator, and the thermal expansion coefficients of the external circuit board, the face-up type semiconductor device, and the heat radiator are set in the above order. Therefore, even if the mounting substrate includes a radiator, the warped shapes of the radiator, the semiconductor device, and the external circuit board can be further approximated, and the connection reliability of the bonding agent can be improved.
【００２１】[0021]
【発明の実施の形態】（構造）本発明の実装基板の一形
態について、図１の概略断面図をもとに詳細に説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS (Structure) One embodiment of the mounting board of the present invention will be described in detail with reference to the schematic sectional view of FIG.
【００２２】本発明の実装基板は、外部回路基板３の対
向する主面に、フェイスアップ型半導体装置５とフェイ
スダウン型半導体装置７が、複数の接合剤９を介して接
合されている。In the mounting board of the present invention, a face-up type semiconductor device 5 and a face-down type semiconductor device 7 are joined to a main surface of the external circuit board 3 facing each other through a plurality of joining agents 9.
【００２３】フェイスアップ型半導体装置５は、配線基
板１１の上面に半導体素子１３が搭載され、この半導体
素子１３を気密封止するための蓋体１７が配線基板１１
の上面に設けられている。また、配線基板１１の下面に
は複数の接合剤９が形成されている。In the face-up type semiconductor device 5, a semiconductor element 13 is mounted on an upper surface of a wiring board 11, and a lid 17 for hermetically sealing the semiconductor element 13 is provided on the wiring board 11.
Is provided on the upper surface. A plurality of bonding agents 9 are formed on the lower surface of the wiring board 11.
【００２４】一方、フェイスダウン型半導体装置７は、
配線基板１８の上面中央部にキャビティ部２１が形成さ
れ、半導体素子１３が収容されている。そして、配線基
板１８の下面にはＣｕを含む材料からなる放熱板２３が
接合されている。On the other hand, the face-down type semiconductor device 7
A cavity 21 is formed at the center of the upper surface of the wiring board 18 and houses the semiconductor element 13. A heat radiating plate 23 made of a material containing Cu is joined to the lower surface of the wiring board 18.
【００２５】フェイスアップ型半導体装置５やフェイス
ダウン型半導体装置７（以後、半導体装置５、７とす
る）を構成している配線基板１１、１８は、絶縁基板２
５の内部に導体層２７が形成され、また、その上面ある
いは下面には複数の接続パッド２９が形成され、導体層
２７と接続パッド２９とはビアホール導体３１を介して
接続されている。さらに、配線基板１１に搭載された半
導体素子１３とキャビティ２１内の接続パッド２９とは
ワイヤ３３によって接続されている。The wiring boards 11 and 18 constituting the face-up type semiconductor device 5 and the face-down type semiconductor device 7 (hereinafter, referred to as semiconductor devices 5 and 7) include an insulating substrate 2
5, a conductor layer 27 is formed, and a plurality of connection pads 29 are formed on the upper or lower surface thereof. The conductor layer 27 and the connection pads 29 are connected via via-hole conductors 31. Further, the semiconductor element 13 mounted on the wiring board 11 and the connection pad 29 in the cavity 21 are connected by a wire 33.
【００２６】（材料および製法）本発明の実装基板にお
いて、半導体装置５、７を構成する絶縁基板２５の材質
としては、アルミナ、ムライト等のセラミックス、ある
いは低温焼成のガラスセラミックスなどの電気絶縁材料
のいずれであっても良いが、半導体装置５、７が実装さ
れた構造においては、部品相互の熱膨張差を緩和し、発
生する応力を低減する上で絶縁基板２５がガラスセラミ
ック焼結体からなることが望ましく、これらの材料を用
いて構成された配線基板１１、１８の熱膨張係数は６〜
１５×１０ -6（／℃）の範囲であることが望ましい。(Material and Manufacturing Method)
And the material of the insulating substrate 25 forming the semiconductor devices 5 and 7
There are ceramics such as alumina and mullite
Or electrical insulating materials such as glass ceramics fired at low temperatures
May be used, but the semiconductor devices 5 and 7 are mounted.
In such a structure, the difference in thermal expansion between
In order to reduce the generated stress, the insulating substrate 25 is made of glass ceramic.
It is preferable to use these materials.
The thermal expansion coefficient of the wiring boards 11 and 18 thus configured is 6 to
15 × 10 -6(/ ° C.).
【００２７】尚、一般に、配線基板１１、１８に半導体
素子１３を搭載している半導体装置５、７では、半導体
素子１３のサイズに比べて、配線基板１１、１８のサイ
ズが大きく、それらの面積比率が大きくなっているため
に、半導体装置５、７の熱膨張係数は主に配線基板１１
の熱膨張係数で決定される。Generally, in the semiconductor devices 5 and 7 in which the semiconductor elements 13 are mounted on the wiring boards 11 and 18, the sizes of the wiring boards 11 and 18 are larger than the size of the semiconductor elements 13. Since the ratio is large, the thermal expansion coefficients of the semiconductor devices 5 and 7 are mainly
Is determined by the coefficient of thermal expansion.
【００２８】また、接合剤９はハンダを含有する金属材
料が主に用いられ、配線基板１１、１８の表面に形成さ
れた接続パッド２９とは、金、錫、ニッケルのうち少な
くとも１種を含有する金属層を介して接続されている。The bonding material 9 is mainly made of a metal material containing solder, and the connection pads 29 formed on the surfaces of the wiring boards 11 and 18 contain at least one of gold, tin and nickel. Are connected via a metal layer.
【００２９】また、外部回路基板３は、いわゆるプリン
ト基板からなり、ガラス・エポキシ樹脂、ガラス・ポリ
イミド樹脂複合材料、およびアラミド繊維などの有機樹
脂を含む材料からなる絶縁体の表面および内部に、Ｃ
ｕ、Ａｕ、Ａｌ、Ｎｉ、Ｓｎ−Ｐｂなどの金属からなる
配線導体が被着形成されたものであり、熱膨張係数は１
２〜２５×１０-6（／℃）の範囲が望ましい。The external circuit board 3 is made of a so-called printed board, and has a surface and inside of an insulator made of a material containing an organic resin such as a glass-epoxy resin, a glass-polyimide resin composite material, and aramid fiber.
A wiring conductor made of a metal such as u, Au, Al, Ni, or Sn—Pb is adhered and formed, and has a thermal expansion coefficient of 1
A range of 2 to 25 × 10 −6 (/ ° C.) is desirable.
【００３０】また、外部回路基板３の厚みは、配線基板
１１の熱膨張によって反り変形し、応力を低減できると
ともに、破壊しない程度の機械的強度を保持するため
に、０．５〜２ｍｍの範囲が望ましい。また、このプリ
ント基板はフェイスダウン型半導体装置７用の配線基板
１８の材料として用いることができる。The thickness of the external circuit board 3 is in the range of 0.5 to 2 mm in order to warp and deform due to the thermal expansion of the wiring board 11 and to reduce the stress, and to maintain the mechanical strength to such a degree that it is not broken. Is desirable. This printed board can be used as a material for the wiring board 18 for the face-down type semiconductor device 7.
【００３１】そして、実装面の平坦性を保持したり、実
装操作での変形を防止するために、外部回路基板３のヤ
ング率は、１０〜３０ＧＰａが望ましい。The Young's modulus of the external circuit board 3 is desirably 10 to 30 GPa in order to maintain the flatness of the mounting surface and prevent deformation during the mounting operation.
【００３２】（作用）本発明の実装基板では、外部回路
基板３の対向する主面に外部回路基板３の一方主面にフ
ェイスアップ型半導体装置５を、他方主面にフェイスダ
ウン型半導体装置７を接合剤９を介して外部回路基板３
に接合したので、図２に示すように、外部回路基板３と
ともに、その上面に設けられたフェイスアップ型半導体
装置５が外部回路基板３に対して凸状に変形するととも
に、フェイスダウン型半導体装置７もフェイスアップ型
半導体装置５に追従して凹状に変形しやすくなり、これ
らの半導体装置５、７と外部回路基板３との間の接合剤
９に作用する歪みや応力を低減でき、ハンダ等の接合剤
の疲労断線を抑え、接続信頼性を飛躍的に向上できる。(Operation) In the mounting board of the present invention, the face-up type semiconductor device 5 is provided on one main surface of the external circuit board 3 on the opposite main surface of the external circuit board 3 and the face-down type semiconductor device 7 is provided on the other main surface. To the external circuit board 3 via the bonding agent 9
As shown in FIG. 2, the external circuit board 3 and the face-up type semiconductor device 5 provided on the upper surface thereof are deformed into a convex shape with respect to the external circuit board 3 as shown in FIG. 7 also easily deforms into a concave shape following the face-up type semiconductor device 5, and can reduce distortion and stress acting on the bonding agent 9 between these semiconductor devices 5, 7 and the external circuit board 3. Can suppress the fatigue disconnection of the bonding agent and greatly improve the connection reliability.
【００３３】また、フェイスアップ型半導体装置５を構
成している配線基板１１の上面に設けられている蓋体１
７の熱膨張係数を配線基板１１と同じかそれ以下とする
ことにより、外部回路基板３側に凸状に変形し易くなり
蓋体１７の影響を軽減することができる。The cover 1 provided on the upper surface of the wiring board 11 constituting the face-up type semiconductor device 5
By setting the coefficient of thermal expansion of 7 to be equal to or less than that of the wiring board 11, it is easy to deform into a convex shape on the external circuit board 3 side, and the influence of the lid 17 can be reduced.
【００３４】一方、フェイスダウン型半導体装置７を構
成している配線基板１８の外部回路基板３の反対側に設
けられている放熱板２３の熱膨張係数を配線基板１８と
同じかもしくはそれ以上とすることにより、外部回路基
板３側に対して凹状に変形し易くなり放熱板２３の影響
を抑えることができる。On the other hand, the heat expansion coefficient of the heat radiating plate 23 provided on the side opposite to the external circuit board 3 of the wiring board 18 constituting the face-down type semiconductor device 7 is equal to or higher than that of the wiring board 18. By doing so, it is easy to deform into a concave shape with respect to the external circuit board 3 side, and the influence of the heat sink 23 can be suppressed.
【００３５】また、半導体装置５、７と外部回路基板３
を接続している接合剤９は、その高さ方向に応力緩和す
る作用を有するように略柱状に形成されることが望まし
い。The semiconductor devices 5 and 7 and the external circuit board 3
Is desirably formed in a substantially columnar shape so as to have an action of relaxing stress in the height direction.
【００３６】また、接合剤９は、配線基板１１面に格子
状に形成することにより、接合剤９に発生する応力を分
散し、且つ低減することができる。Further, by forming the bonding agent 9 in a lattice on the surface of the wiring board 11, the stress generated in the bonding agent 9 can be dispersed and reduced.
【００３７】また、外部回路基板３の両面に対向して実
装される半導体装置５、７のサイズは、面積比が同じ
か、もしくは１０％以内であれば、両面の半導体装置
５、７の反り変形の度合を近づけることができ接合剤９
に発生する歪みや応力を低くすることができる。The size of the semiconductor devices 5 and 7 mounted on both surfaces of the external circuit board 3 so as to be opposed to each other is the same if the area ratio is the same or within 10%. The degree of deformation can be approximated and the bonding agent 9
Can be reduced.
【００３８】さらに、配線基板１１の主面ならびにキャ
ビティ２１内に実装される半導体素子１３のサイズは主
面の面積比で５０％以内であることが、半導体素子１３
の熱膨張の影響を軽減できる。Further, the size of the semiconductor element 13 mounted on the main surface of the wiring board 11 and the cavity 21 is preferably within 50% by area ratio of the main surface.
Can reduce the influence of thermal expansion.
【００３９】また、フェイスアップ型半導体装置５を構
成する配線基板１１の熱膨張係数をα１、フェイスダウ
ン型半導体装置７を構成する配線基板１８の熱膨張係数
をα２とした時、α２＞α１の関係を満足することが望
ましい。When the thermal expansion coefficient of the wiring board 11 constituting the face-up type semiconductor device 5 is α1, and the thermal expansion coefficient of the wiring board 18 constituting the face-down type semiconductor device 7 is α2, α2> α1 It is desirable to satisfy the relationship.
【００４０】フェイスダウン型半導体装置７の熱膨張係
数α２が、フェイスアップ型半導体装置５の熱膨張係数
α１よりも大きければ、フェイスダウン型半導体装置７
の反り形状がフェイスアップ型半導体装置５の反り形状
に追従しやすくなるため、外部回路基板３と半導体装置
５、７を接続している接合剤９の熱膨張差による歪や応
力を、さらに小さくすることができ、外部回路基板３と
半導体装置５、７を接続している接合剤９の接続信頼性
をさらに向上できる。特に、フェイスダウン型半導体装
置７の熱膨張係数が、フェイスアップ型半導体装置５の
熱膨張係数よりも２×１０-6（／℃）以上大きいこと
が、特に望ましい。If the thermal expansion coefficient α2 of the face-down type semiconductor device 7 is larger than the thermal expansion coefficient α1 of the face-up type semiconductor device 5,
Since the warp shape of the semiconductor device 5 easily follows the warp shape of the face-up type semiconductor device 5, the distortion and stress due to the difference in thermal expansion of the bonding agent 9 connecting the external circuit board 3 and the semiconductor devices 5 and 7 are further reduced. The connection reliability of the bonding agent 9 connecting the external circuit board 3 and the semiconductor devices 5 and 7 can be further improved. In particular, it is particularly desirable that the thermal expansion coefficient of the face-down type semiconductor device 7 is larger than the thermal expansion coefficient of the face-up type semiconductor device 5 by 2 × 10 −6 (/ ° C.) or more.
【００４１】また、外部回路基板の熱膨張係数をα０と
したときに、α２＞α０＞α１の関係を満足することが
望ましい。When the coefficient of thermal expansion of the external circuit board is α0, it is desirable to satisfy the relationship α2>α0> α1.
【００４２】外部回路基板３として、例えば、熱膨張係
数が１２〜２５×１０-6（／℃）のプリント基板を用い
た場合に、フェイスアップ型半導体装置５として、熱膨
張係数が外部回路基板３よりも小さいセラミック製の配
線基板１１やガラスセラミックス製の配線基板１１を用
い、対向するフェイスダウン型半導体装置７の配線基板
１８として、ガラス繊維やアラミド繊維にエポキシ樹脂
やポリイミド樹脂などの熱硬化性樹脂を含浸して作製し
た熱膨張係数が外部回路基板３よりも大きいプリント基
板を用いることにより、実装基板を構成する配線基板１
１と外部回路基板３の熱膨張係数をフェイスダウン型半
導体装置７＞外部回路基板３＞フェイスアップ型半導体
装置５の順に小さくすることができ、外部回路基板３の
両面に設けた半導体装置５、７の反りを外部回路基板３
とともに追従させることができる。For example, when a printed circuit board having a thermal expansion coefficient of 12 to 25 × 10 −6 (/ ° C.) is used as the external circuit board 3, the face-up type semiconductor device 5 has a thermal expansion coefficient of the external circuit board. Using a ceramic wiring board 11 or a glass ceramic wiring board 11 smaller than 3 as the wiring board 18 of the opposed face-down type semiconductor device 7, glass fiber or aramid fiber and thermosetting epoxy resin or polyimide resin. By using a printed circuit board having a thermal expansion coefficient larger than that of the external circuit board 3 made by impregnating the conductive resin, the wiring board 1 constituting the mounting board is used.
1 and the thermal expansion coefficient of the external circuit board 3 can be reduced in the order of the face-down type semiconductor device 7> the external circuit board 3> the face-up type semiconductor device 5, and the semiconductor devices 5 provided on both surfaces of the external circuit board 3. 7 warps the external circuit board 3
Can be followed.
【００４３】図３は、本発明の他の実装基板を示すもの
で、フェイスアップ型半導体装置５の蓋体１７には半導
体素子１３から発生する熱を放熱するために放熱体１９
が設けられている。FIG. 3 shows another mounting substrate according to the present invention. A radiator 19 for radiating heat generated from the semiconductor element 13 is provided on a lid 17 of the face-up type semiconductor device 5.
Is provided.
【００４４】この放熱体１９はコバールやＡｌＳｉＣか
らなる比較的熱膨張係数の小さい材料が好適に用いら
れ、その熱膨張係数は５〜１５×１０-6（／℃）の範囲
であり、用いられる配線基板１１、１８の熱膨張係数や
ヤング率に応じて変更することができる。The radiator 19 is preferably made of a material having a relatively small coefficient of thermal expansion, such as Kovar or AlSiC, and has a coefficient of thermal expansion in the range of 5 to 15 × 10 −6 (/ ° C.). It can be changed according to the thermal expansion coefficient and Young's modulus of the wiring boards 11 and 18.
【００４５】以上のように構成された実装基板では、フ
ェイスアップ型半導体装置５と外部回路基板３との熱膨
張係数差に起因した反り（撓み）変形を阻害しないため
には、フェイスアップ型半導体装置５の放熱体１９の熱
膨張係数は、同配線基板１１の熱膨張係数よりも小さい
方がより好適であり、フェイスアップ型半導体装置５を
構成する配線基板１１の熱膨張係数をα１、外部回路基
板３の熱膨張係数をα０、および放熱体１９の熱膨張係
数をα３とした時に、α０＞α１＞α３の関係を満足す
ることが望ましい。In the mounting board configured as described above, in order not to inhibit the warpage (bending) deformation caused by the difference in the thermal expansion coefficient between the face-up type semiconductor device 5 and the external circuit board 3, the face-up type semiconductor It is more preferable that the thermal expansion coefficient of the radiator 19 of the device 5 is smaller than the thermal expansion coefficient of the wiring substrate 11. The thermal expansion coefficient of the wiring substrate 11 constituting the face-up type semiconductor device 5 is α1, When the thermal expansion coefficient of the circuit board 3 is α0 and the thermal expansion coefficient of the radiator 19 is α3, it is desirable that the relationship α0>α1> α3 is satisfied.
【００４６】例えば、熱膨張係数が外部回路基板３より
も小さいセラミック製の配線基板１１からなるフェイス
アップ型半導体装置５の上面側に、例えば、熱膨張係数
がこのフェイスアップ型半導体装置５を構成している配
線基板１１よりも小さいコバールやＡｌＳｉＣ等からな
る放熱体１９を接合することにより実装基板１を構成す
る配線基板１１と外部回路基板３の熱膨張係数を、外部
回路基板３＞フェイスアップ型半導体装置５＞放熱体１
９の順に小さくすることができるため、放熱体１９を含
めても外部回路基板３とその両面に設けられた半導体装
置５、７の反り変形をさらに追従させることができる。For example, the face-up type semiconductor device 5 having a thermal expansion coefficient smaller than that of the external circuit board 3 is formed on the upper surface side of the face-up type semiconductor device 5 comprising the ceramic wiring board 11. The thermal expansion coefficient of the wiring board 11 and the external circuit board 3 constituting the mounting board 1 by joining a heat radiator 19 made of Kovar, AlSiC, or the like smaller than the wiring board 11 that is smaller than the external circuit board 3> face-up Type semiconductor device 5> radiator 1
9, the warping deformation of the external circuit board 3 and the semiconductor devices 5 and 7 provided on both surfaces thereof can be further followed even when the heat radiator 19 is included.
【００４７】また、半導体素子１３の上面に放熱体１９
を設置することで、半導体装置５、の放熱性を高め、温
度変化を小さくできるため、半導体装置５、７を構成す
る配線基板１８の熱膨張を抑制し、半導体装置５、７と
外部回路基板３とを接合している接合剤９の歪を小さく
することができ、接合剤９の断線を防止し、接続信頼性
をさらに高めることができる。この放熱体１９は半導体
装置５、７の両方、もしくは片方に設けることができ
る。The radiator 19 is provided on the upper surface of the semiconductor element 13.
Since the heat dissipation of the semiconductor device 5 can be enhanced and the temperature change can be reduced by installing the semiconductor device 5, the thermal expansion of the wiring board 18 constituting the semiconductor devices 5 and 7 is suppressed, and the semiconductor devices 5 and 7 and the external circuit board are connected. Distortion of the bonding agent 9 that joins the bonding member 3 can be reduced, disconnection of the bonding agent 9 can be prevented, and connection reliability can be further improved. The heat radiator 19 can be provided on both or one of the semiconductor devices 5 and 7.
【００４８】尚、本発明は、上記例に限定されるもので
はなく、要旨を変更しない範囲で変更可能である。例え
ば、フェイスダウン型半導体装置７に用いられる配線基
板１８として、図１に示したような貫通していないキャ
ビティ部２１を有する非貫通型の配線基板１８の他に、
図４に示すように、貫通されたキャビティ２１を有する
貫通型の配線基板４１があり、配線遅延等対策のための
接地電源線強化を重視する場合に非中貫型配線基板が、
一方、配線基板１８の放熱性を重視する場合には貫通型
の配線基板４１が好適に用いられる。It should be noted that the present invention is not limited to the above example, and can be changed without changing the gist. For example, as the wiring board 18 used in the face-down type semiconductor device 7, in addition to the non-penetrating type wiring board 18 having the cavity 21 not penetrating as shown in FIG.
As shown in FIG. 4, there is a through-type wiring substrate 41 having a penetrated cavity 21, and when emphasis is placed on ground power supply lines for measures such as wiring delay, a non-penetrating type wiring substrate is used.
On the other hand, when importance is placed on the heat dissipation of the wiring board 18, a through-type wiring board 41 is preferably used.
【００４９】また、接合剤９に関し、図５（ａ）、
（ｂ）、（ｃ）に示すように配列された複数の接合剤９
からなる接合剤群１５の外周部に、配線基板１１、１８
内の導体層２７と接合していない、いわば機械的に接合
するための補助接合剤３９を設けてもよく、その大きさ
（面積）、間隔および配列は任意に変えることができ
る。As for the bonding agent 9, FIG.
(B) A plurality of bonding agents 9 arranged as shown in (c)
The wiring boards 11 and 18 are provided on the outer periphery of the bonding agent group 15 made of
An auxiliary bonding agent 39 that is not bonded to the inner conductor layer 27, that is, may be provided for mechanical bonding, so to say, may be arbitrarily changed in size (area), interval, and arrangement.
【００５０】また、これらの接合剤９や補助接合剤３９
がハンダペーストで形成される際に、溶融したハンダ
が、表面張力によって上下のパッドの位置を補正するセ
ルフアライメント効果をより高めることができる。The bonding agent 9 and the auxiliary bonding agent 39
When the solder paste is formed with the solder paste, the molten solder can enhance the self-alignment effect of correcting the positions of the upper and lower pads by the surface tension.
【００５１】また、補助接合剤３９が半導体装置５、７
と外部回路基板３との間でスペーサの役割を担い、接合
剤９に加えて接続部の面積を大きくでき、そして、ハン
ダボール自身が半導体装置５、７や外部回路基板３の変
形による圧縮応力を緩和することができる。The auxiliary bonding agent 39 is used for the semiconductor devices 5 and 7.
Plays a role of a spacer between the semiconductor device 5 and the external circuit board 3, and can increase the area of the connection portion in addition to the bonding agent 9. Can be alleviated.
【００５２】さらに、この補助接合剤３９は電気的な導
通を有していないため、たとえ熱疲労によって破壊して
もパッケージの信頼性には影響しない。Further, since the auxiliary bonding agent 39 has no electrical conduction, even if it is broken by thermal fatigue, it does not affect the reliability of the package.
【００５３】また、半導体素子１３を実装する他の方法
として、図６に示すように、その一方主面に形成された
端子部と配線基板１１に形成された接続パッドとの間に
ハンダバンプ５１を形成して接続され、さらに、半導体
素子１３と配線基板１１との間に有機樹脂を含有するア
ンダーフィル充填剤５３を流し込んで封止するフリップ
チップ方式の接合法を用いることもできる。As another method for mounting the semiconductor element 13, as shown in FIG. 6, a solder bump 51 is provided between a terminal portion formed on one main surface and a connection pad formed on the wiring board 11. A flip-chip bonding method in which an underfill filler 53 containing an organic resin is poured between the semiconductor element 13 and the wiring board 11 for sealing is formed.
【００５４】[0054]
【実施例】表１に示す３種類の絶縁材料を用いて、フェ
イスアップ型半導体装置５用及びフェイスダウン型半導
体装置７用の配線基板１１、１８を作製した。また、こ
の配線基板１１、１８の切出片を用いて、超音波法によ
りヤング率を、熱機械分析法により熱膨張係数を温度−
５０〜１５０℃の範囲で測定した。EXAMPLE Using three kinds of insulating materials shown in Table 1, wiring boards 11 and 18 for the face-up type semiconductor device 5 and the face-down type semiconductor device 7 were manufactured. Using the cut pieces of the wiring boards 11 and 18, the Young's modulus was determined by the ultrasonic method, and the coefficient of thermal expansion was determined by the thermomechanical analysis method.
It measured in the range of 50 to 150 ° C.
【００５５】半導体素子１３の載置方法は、いずれもフ
リップチップ方式を用いた。パッケージサイズは１７ｍ
ｍ×１７ｍｍ×１．０ｍｍ、半導体素子１３サイズは１
１ｍｍ×１１ｍｍ×０．２７ｍｍである。底面には、接
合剤９を形成するための２５６個の接続パッド２９を設
けた。The mounting method of the semiconductor element 13 used the flip chip method in all cases. Package size is 17m
mx 17 mm x 1.0 mm, semiconductor element 13 size is 1
It is 1 mm × 11 mm × 0.27 mm. On the bottom surface, 256 connection pads 29 for forming the bonding agent 9 were provided.
【００５６】そして上記配線基板１１の接続パッド２９
にハンダ（Ｓｎ６３％−Ｐｂ３７％）ペーストをスクリ
ーン印刷により塗布し、ハンダボール搭載後に加熱溶融
してハンダの層を形成させた。The connection pads 29 on the wiring board 11
A solder (Sn 63% -Pb 37%) paste was applied by screen printing and heated and melted after mounting a solder ball to form a solder layer.
【００５７】一方、外部回路基板３として、ガラス−エ
ポキシ樹脂からなる絶縁材料の両面に銅箔からなる接続
パッド２９を形成し、熱膨張係数が１４×１０-6／℃の
プリント基板を準備した。On the other hand, as the external circuit board 3, connection pads 29 made of copper foil were formed on both surfaces of an insulating material made of glass-epoxy resin, and a printed board having a thermal expansion coefficient of 14 × 10 -6 / ° C. was prepared. .
【００５８】そして、この外部回路基板３の片面の接続
パッド２９にハンダ（Ｓｎ６３％−Ｐｂ３７％）ペース
トをスクリーン印刷により塗布した後、上記の配線基板
１１の接続パッド２９とこの外部回路基板３の接続パッ
ド２９とを位置合わせし、加熱溶融させて実装した。そ
の後、外部回路基板３の反対面の接続パッド２９にハン
ダペーストをスクリーン印刷により塗布し、配線基板１
１のランドを位置合わせし、加熱溶融させて図1に示す
実装基板を作製した。Then, after solder (Sn 63% -Pb 37%) paste is applied to the connection pads 29 on one side of the external circuit board 3 by screen printing, the connection pads 29 of the wiring board 11 and the The connection pads 29 were aligned and heated and melted for mounting. Thereafter, a solder paste is applied to the connection pads 29 on the opposite surface of the external circuit board 3 by screen printing, and
The lands of No. 1 were aligned and heated and melted to produce the mounting substrate shown in FIG.
【００５９】次に、上記のようにして作製した実装基板
を、−４０℃と１２５℃の各温度になるように到達した
恒温槽に試験サンプルを投入し、２５分／２５分の保持
を1サイクルとして最高２０００サイクルまで繰り返し
行った。Next, the test sample is put into the thermostat having reached the respective temperatures of −40 ° C. and 125 ° C., and the holding substrate manufactured as described above is held for 25 minutes / 25 minutes. The cycle was repeated up to 2000 cycles.
【００６０】そして、１００サイクル終了毎に外部回路
基板３と配線基板１１、１８との電気抵抗を測定し、電
気抵抗に＋２０％以上の変化が現れるまでのサイクル数
を評価し、表２に示した。The electrical resistance between the external circuit board 3 and the wiring boards 11 and 18 was measured every 100 cycles, and the number of cycles until the electrical resistance changed by + 20% or more was evaluated. Was.
【００６１】[0061]
【表１】 [Table 1]
【００６２】[0062]
【表２】 [Table 2]
【００６３】表１、２より明らかなように、外部回路基
板３の両面に対向して、フェイスアップ型半導体装置５
とフェイスダウン型半導体装置７を実装した本発明の実
装基板では、１０００サイクルを超えても抵抗変化は全
く認められず、極めて安定で良好な電気的接続状態を維
持できた。これに対して、フェイスアップ型半導体装置
５を外部回路基板３の両面に実装して作製した実装基板
（試料Ｎｏ．１）では、５００サイクルの早い段階から
抵抗変化が検出され、実装信頼性が低いことがわかっ
た。As is clear from Tables 1 and 2, the face-up type semiconductor device 5
In the mounting board of the present invention on which the face-down type semiconductor device 7 was mounted, no change in resistance was observed even after exceeding 1000 cycles, and an extremely stable and good electrical connection state could be maintained. On the other hand, in a mounting board (sample No. 1) manufactured by mounting the face-up type semiconductor device 5 on both surfaces of the external circuit board 3, a change in resistance is detected as early as 500 cycles, and the mounting reliability is reduced. It turned out to be low.
【００６４】さらに、フェイスダウン型半導体装置７を
構成する配線基板１８の熱膨張係数をフェイスアップ型
半導体装置５を構成する配線基板１１の熱膨張係数より
も大きくした試料Ｎｏ．３、Ｎｏ．４およびＮｏ．５で
は、１５００サイクルを超えても抵抗変化は全く認めら
れなかった。特に、α２＞α０＞α１の試料Ｎｏ．５で
は、特に疲労寿命が長くなった。Further, in the sample No. 5 in which the thermal expansion coefficient of the wiring board 18 constituting the face-down type semiconductor device 7 was larger than the thermal expansion coefficient of the wiring board 11 constituting the face-up type semiconductor device 5. 3, No. 4 and no. In No. 5, no resistance change was observed even after 1500 cycles. In particular, sample No. of α2>α0> α1. In No. 5, the fatigue life was particularly prolonged.
【００６５】また、フェイスアップ型半導体装置５の上
部にコバール（熱膨張係数５×１０ -6（／℃）製の放熱
体１９を設けて作製した実装基板の試料Ｎｏ．７では、
抵抗変化の寿命が１５００〜１７００サイクルとなり、
一方、放熱体にＡｌＳｉＣ（熱膨張係数１０×１０
-6（／℃）を用いた試料Ｎｏ．６の１１００〜１２００
サイクルよりも疲労寿命が長かった。Further, on the face-up type semiconductor device 5,
Kovar (coefficient of thermal expansion 5 × 10 -6(/ ° C) heat radiation
Sample No. of the mounting board manufactured by providing the body 19 In 7,
The life of the resistance change becomes 1500 to 1700 cycles,
On the other hand, AlSiC (coefficient of thermal expansion 10 × 10
-6(/ ° C.) 6 of 1100-1200
The fatigue life was longer than the cycle.
【００６６】[0066]
【発明の効果】以上詳述したように、本発明の実装基板
は、外部回路基板の一方主面にフェイスアップ型半導体
装置を実装し、一方、他方主面に対向してフェイスダウ
ン型半導体装置を実装することにより、半導体装置の半
導体素子側の面が、半導体素子を固着していない面より
も熱膨張が小さいため、フェイスアップ型半導体装置は
外部回路基板に対して凸状に変形し、一方、フェイスダ
ウン型半導体装置は外部回路基板に対して凹状に変形
し、これにより、外部回路基板の両面に対向して実装さ
れたこれらの半導体装置が同じ方向に反り変形させるこ
とができる。As described in detail above, the mounting board of the present invention has a face-up type semiconductor device mounted on one main surface of an external circuit board, and a face-down type semiconductor device facing one other main surface. By mounting, the surface of the semiconductor device on the semiconductor element side has a smaller thermal expansion than the surface to which the semiconductor element is not fixed, so that the face-up type semiconductor device is deformed in a convex shape with respect to the external circuit board, On the other hand, the face-down type semiconductor device is deformed concavely with respect to the external circuit board, so that these semiconductor devices mounted on both sides of the external circuit board can be warped and deformed in the same direction.
【００６７】このため、半導体装置と外部回路基板との
間に形成された接合剤に発生する応力を低減でき、接合
剤におけるハンダの疲労断線を抑え、接続信頼性を飛躍
的に向上できる。For this reason, the stress generated in the bonding agent formed between the semiconductor device and the external circuit board can be reduced, the fatigue disconnection of the solder in the bonding agent can be suppressed, and the connection reliability can be dramatically improved.
【図１】本発明の実装基板を示す概略断面図である。FIG. 1 is a schematic sectional view showing a mounting board of the present invention.
【図２】本発明の実装基板が反り変形した状態を示す模
式図である。FIG. 2 is a schematic diagram showing a state in which the mounting board of the present invention is warped and deformed.
【図３】本発明の蓋体の上部に放熱体を設けた実装基板
を示す概略断面図である。FIG. 3 is a schematic cross-sectional view showing a mounting substrate provided with a heat radiator on an upper portion of a lid according to the present invention.
【図４】キャビティ部を中貫した配線基板で構成された
フェイスダウン型半導体装置を示す概略断面図である。FIG. 4 is a schematic cross-sectional view showing a face-down type semiconductor device constituted by a wiring substrate having a cavity portion penetrating therethrough.
【図５】接合剤および補助接合剤の配置例を示す図であ
る。FIG. 5 is a diagram showing an example of arrangement of a bonding agent and an auxiliary bonding agent.
【図６】半導体素子をフリップチップ接合した半導体装
置を外部回路基板の両面に設けた本発明の実装基板を示
す概略断面図である。FIG. 6 is a schematic cross-sectional view showing a mounting board of the present invention in which semiconductor devices in which semiconductor elements are flip-chip bonded are provided on both surfaces of an external circuit board.
【図７】（ａ）は外部回路基板の片面にフェイスアップ
型半導体装置を実装した実装基板、（ｂ）はフェイスダ
ウン型半導体装置を実装した実装基板の概略断面図であ
る。7A is a schematic cross-sectional view of a mounting board on which a face-up type semiconductor device is mounted on one surface of an external circuit board, and FIG.
３、７１ 外部回路基板 ５、６１ フェイスアップ型半導体装置 ７、６３ フェイスダウン型半導体装置 ９、６９ 接合剤 １１、１８、４１、６７ 配線基板 １３、６５ 半導体素子 １５ 接合剤群 １７ 蓋体 １９ 放熱体 ２１ キャビティ ２３ 放熱板 ２５ 絶縁基板 ２７ 導体層 ２９ 接続パッド ３１ ビアホール導体 ３３ ワイヤ ３９ 補助接合剤 3, 71 External circuit board 5, 61 Face-up type semiconductor device 7, 63 Face-down type semiconductor device 9, 69 Bonding agent 11, 18, 41, 67 Wiring board 13, 65 Semiconductor element 15 Bonding agent group 17 Cover 19 Heat radiation Body 21 Cavity 23 Heat sink 25 Insulating substrate 27 Conductive layer 29 Connection pad 31 Via hole conductor 33 Wire 39 Auxiliary bonding agent
Claims (4)
体装置を、外部回路基板の対向する主面に、それぞれ接
合剤により実装してなるとともに、前記外部回路基板の
一方主面に実装された半導体装置がフェイスアップ型半
導体装置とされ、他方主面に実装された半導体装置がフ
ェイスダウン型半導体装置とされていることを特徴とす
る実装基板。1. A semiconductor device having a semiconductor element mounted on a wiring board is mounted on an opposing main surface of an external circuit board with a bonding agent, and is mounted on one main surface of the external circuit board. Wherein the semiconductor device is a face-up type semiconductor device, and the semiconductor device mounted on the other main surface is a face-down type semiconductor device.
線基板の熱膨張係数をα１、フェイスダウン型半導体装
置を構成する配線基板の熱膨張係数をα２とした時、α
２＞α１の関係を満足することを特徴とする請求項１記
載の実装基板。2. The thermal expansion coefficient of a wiring board constituting a face-up type semiconductor device is α1, and the thermal expansion coefficient of a wiring board constituting a face-down type semiconductor device is α2.
2. The mounting board according to claim 1, wherein a relationship of 2> α1 is satisfied.
きに、α２＞α０＞α１の関係を満足することを特徴と
する請求項１または２記載の実装基板。3. The mounting board according to claim 1, wherein a relationship of α2>α0> α1 is satisfied when a thermal expansion coefficient of the external circuit board is α0.
基板と反対側の位置に放熱体を設けるとともに、前記フ
ェイスアップ型半導体装置を構成する配線基板の熱膨張
係数をα１、前記外部回路基板の熱膨張係数をα０、お
よび前記放熱体の熱膨張係数をα３とした時に、α０＞
α１＞α３の関係を満足することを特徴とする請求項１
乃至３のうちいずれかに記載の実装基板。4. A heat radiator is provided at a position of the face-up type semiconductor device opposite to the external circuit board, a coefficient of thermal expansion of a wiring board constituting the face-up type semiconductor device is α1, and the external circuit board has When the thermal expansion coefficient is α0 and the thermal expansion coefficient of the radiator is α3, α0>
2. The relationship of α1> α3 is satisfied.
4. The mounting board according to any one of the above aspects.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000378933A JP4577980B2 (en) | 2000-12-13 | 2000-12-13 | Mounting board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000378933A JP4577980B2 (en) | 2000-12-13 | 2000-12-13 | Mounting board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002184942A true JP2002184942A (en) | 2002-06-28 |
| JP4577980B2 JP4577980B2 (en) | 2010-11-10 |
Family
ID=18847407
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000378933A Expired - Fee Related JP4577980B2 (en) | 2000-12-13 | 2000-12-13 | Mounting board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4577980B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006196874A (en) * | 2004-12-13 | 2006-07-27 | Canon Inc | Semiconductor device |
| JP2009070891A (en) * | 2007-09-11 | 2009-04-02 | Sumitomo Bakelite Co Ltd | Semiconductor device |
| KR101190920B1 (en) | 2010-10-18 | 2012-10-12 | 하나 마이크론(주) | Stacked semiconductor package and method of manufacturing thereof |
| KR101247138B1 (en) * | 2005-09-14 | 2013-03-29 | 하테체 베타일리궁스 게엠베하 | Flip-chip module and method of producing a flip-chip module |
| US9254653B2 (en) | 2013-02-26 | 2016-02-09 | Seiko Epson Corporation | Wiring structure, method of manufacturing wiring structure, liquid droplet ejecting head, and liquid droplet ejecting apparatus |
| US9579892B2 (en) | 2013-02-26 | 2017-02-28 | Seiko Epson Corporation | Wiring structure, method of manufacturing wiring structure, liquid droplet ejecting head, and liquid droplet ejecting apparatus |
| JP2019174587A (en) * | 2018-03-28 | 2019-10-10 | 住友大阪セメント株式会社 | Optical waveguide element module |
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| JPH04280695A (en) * | 1991-03-08 | 1992-10-06 | Hitachi Ltd | High integrated semiconductor device and semiconductor module provided therewith |
| JPH1079405A (en) * | 1996-09-04 | 1998-03-24 | Hitachi Ltd | Semiconductor device and electronic component mounting the same |
| WO2001071806A1 (en) * | 2000-03-21 | 2001-09-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device, method of manufacturing electronic device, electronic device, and portable information terminal |
-
2000
- 2000-12-13 JP JP2000378933A patent/JP4577980B2/en not_active Expired - Fee Related
Patent Citations (4)
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| JPH04280696A (en) * | 1991-03-08 | 1992-10-06 | Hitachi Ltd | High integrated semiconductor device |
| JPH04280695A (en) * | 1991-03-08 | 1992-10-06 | Hitachi Ltd | High integrated semiconductor device and semiconductor module provided therewith |
| JPH1079405A (en) * | 1996-09-04 | 1998-03-24 | Hitachi Ltd | Semiconductor device and electronic component mounting the same |
| WO2001071806A1 (en) * | 2000-03-21 | 2001-09-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device, method of manufacturing electronic device, electronic device, and portable information terminal |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006196874A (en) * | 2004-12-13 | 2006-07-27 | Canon Inc | Semiconductor device |
| KR101247138B1 (en) * | 2005-09-14 | 2013-03-29 | 하테체 베타일리궁스 게엠베하 | Flip-chip module and method of producing a flip-chip module |
| JP2009070891A (en) * | 2007-09-11 | 2009-04-02 | Sumitomo Bakelite Co Ltd | Semiconductor device |
| KR101190920B1 (en) | 2010-10-18 | 2012-10-12 | 하나 마이크론(주) | Stacked semiconductor package and method of manufacturing thereof |
| US9254653B2 (en) | 2013-02-26 | 2016-02-09 | Seiko Epson Corporation | Wiring structure, method of manufacturing wiring structure, liquid droplet ejecting head, and liquid droplet ejecting apparatus |
| US9579892B2 (en) | 2013-02-26 | 2017-02-28 | Seiko Epson Corporation | Wiring structure, method of manufacturing wiring structure, liquid droplet ejecting head, and liquid droplet ejecting apparatus |
| JP2019174587A (en) * | 2018-03-28 | 2019-10-10 | 住友大阪セメント株式会社 | Optical waveguide element module |
| JP7059749B2 (en) | 2018-03-28 | 2022-04-26 | 住友大阪セメント株式会社 | Optical waveguide element module |
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|---|---|
| JP4577980B2 (en) | 2010-11-10 |
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