JP3561671B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP3561671B2
JP3561671B2 JP2000024694A JP2000024694A JP3561671B2 JP 3561671 B2 JP3561671 B2 JP 3561671B2 JP 2000024694 A JP2000024694 A JP 2000024694A JP 2000024694 A JP2000024694 A JP 2000024694A JP 3561671 B2 JP3561671 B2 JP 3561671B2
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semiconductor element
heat spreader
semiconductor device
wiring
resin
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JP2001210769A (en
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奈柄 米田
英生 三浦
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Renesas Technology Corp
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Renesas Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は，ヒートスプレッダを用いた半導体装置に関する。
【０００２】
【従来の技術】
フェイスダウンチップの周囲に外部電極をマトリックス状に設けるＦａｎ−ｏｕｔタイプのＢＧＡの放熱性を高める構造の従来技術を紹介する。Ｆａｎ−ｏｕｔ ＢＧＡでは，一般に，薄い絶縁テープか，樹脂基板に銅配線を引き回し，半導体素子との電気接続はこの銅配線を延長させたビーム状のリードか，ワイヤボンディングで行う。薄い絶縁テープを用いる場合は，金属製のスティフナに貼り付けて使用することで，外部電極の平坦性を保つ。本構造で高放熱化する場合には，平成９年９月号の「電子材料（３７ページ）」に掲載されるＦａｎ−ｏｕｔ型のＢＧＡのようにスティフナと半導体素子の裏面を面位置にしてヒートスプレッダを貼る，もしくは，特開平７ー２８３３３６号公報や特開平８ー２０３９５８号公報に開示されるように，スティフナを用いずにキャビティを設けたヒートスプレッダだけを装着する。平成９年９月号の「電子材料（６５〜６６ページ）」にはスティフナに要求される特性として十分な剛性を有することが必要であり，一般的に０．２５ ｍｍから０．３５ ｍｍの厚みの銅合金かステンレス鋼が採用されていると記載されている。さらに，スティフナと併用されるヒートスプレッダの素材は無酸素銅や高熱伝導銅合金であると記載されている。また，特開平９ー２１３８３７号公報に開示されるように，ヒートスプレッダとして銅，アルミニウム，またはこれらの合金を用いたＦａｎ−ｏｕｔタイプのＢＧＡの構造がある。
【０００３】
一方，日経マイクロデバイス（１９８９年９月号９６〜９９ページ）によれば，従来のリードフレームを使用した樹脂封止型のＱｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ （ＱＦＰ）やＳＯＰ （Ｓｍａｌｌ Ｏｕｔｌｉｎｅ Ｐａｃｋａｇｅ）では，銅合金製のヒートスプレッダをリードフレームのタイバーにかしめる，あるいはダイパッド部に接着するなどして，半導体装置の高放熱化を図る例が紹介されている。これらのヒートスプレッダは，耐湿性の問題から封止樹脂中に内蔵させるタイプと，その上にアルミフィンを後付けする，あるいは実装基板にはんだ実装するために表面に露出させるタイプがある。銅合金は半導体素子との線膨張係数差が大きいため，ヒートスプレッダの接合材としては，ヤング率低いエポキシ系あるいはポリイミド系の接着材が用いられている。
【０００４】
【発明が解決しようとする課題】
上記半導体装置の部材の線膨張係数は，ヒートスプレッダ材として用いられる銅合金が１７×１０￣６／℃，アルミニウムが２２×１０￣６／℃，ステンレスが１７×１０￣６／℃，半導体素子であるシリコンが３×１０￣６／℃，封止樹脂が１２〜２５×１０￣６／℃と互いに大きく異なっている。このため，樹脂封止からの冷却や，信頼性試験のための温度サイクル試験などでは，半導体装置内部に熱応力が発生する。温度サイクル試験では，この熱応力が繰り返し負荷されるため，ダイパッドやリードフレームの端部から樹脂に疲労き裂が発生したり，ボンディングワイヤやテープ上の配線等が疲労により断線することがある。また，基板実装後の温度サイクル試験や電子機器内でのオン・オフの繰り返しでは，半導体装置と実装基板の線膨張係数差によって，リードのはんだ接合部やはんだバンプなどにも疲労破壊が生じることがある。
【０００５】
また，比較的チップサイズや発熱量の大きいマイコンやＡＳＩＣを搭載する多ピン系のＱＦＰでは，自己インダクタンスが小さく高周波動作に向き，放熱性が高いことから，銅合金系のリードフレームが使用されてきた。しかしながら，素子との線膨張係数差が大きいため，ぺ付け材には，ヤング率低いエポキシ系の接着材（銀ペーストなど）しか使用できす，小さいチップで用いられているように熱伝導率の大きいはんだで接着することが困難である。
【０００６】
最近の小型携帯機器では，Ｃｈｉｐ Ｓｃａｌｅ Ｐａｃｋａｇｅ（ＣＳＰ）と呼ばれる構造のはんだバンプで電気接続をとる小型の半導体装置が増えている。ＣＳＰは，半導体装置に占める素子の体積比率が大きく，見かけの線膨張係数が素子側に近い。このため，ＣＳＰが多数搭載される小型携帯機器の実装基板では，線膨張係数を従来の１５×１０￣６／℃程度から８×１０￣６／℃程度に小さした低熱膨張基板の使用が一般化し，使用される樹脂も低熱膨張な材料が多くなっている。このため，銅合金を用いたヒートスプレッダが装着，あるいは内蔵された半導体装置では，低膨張基板との線膨張係数差は増すため，はんだ接続部の寿命低下や樹脂クラックが生じる懸念がある。
【０００７】
本発明の目的は，上記の問題点のすくなくとも一つを解決することにより、強度信頼性を確保しつつ，放熱性も高い半導体装置を提供することにある。
【０００８】
【課題を解決するための手段】
上記の目的は、例えば、樹脂封止型半導体装置を以下のように構成することにより解決される。すなわち，ヒートスプレッダ材として従来より使用されてきた銅合金並の高い熱伝導率を持ちながら，銅合金に比べて小さい線膨張係数を持つように焼結されたＣｕ２ＯとＣｕの複合合金を用いる。Ｃｕ／Ｃｕ２Ｏ複合合金では，Ｃｕ２Ｏの配合を増やすと線膨張係数，熱伝導率，ヤング率が小さくなる（図９）。Ｃｕ／Ｃｕ２Ｏ複合合金の物性を調査した範囲は，Ｃｕ２Ｏの配合比率で２０〜８０ｖｏｌ．％で，このとき熱伝導率は２８０〜４１Ｗ／（ｍＫ），線膨張係数は１３．８〜５．５×１０￣６／℃であった。たとえば，高放熱化のために半導体で用いられている銅合金に匹敵する熱伝導率１５０Ｗ／（ｍＫ）以上が必要な場合は，Ｃｕ２Ｏの配合比を２０〜４６％にすれば良い。このとき，Ｃｕ／Ｃｕ２Ｏ複合合金の線膨張係数は１３．８〜１０．５×１０￣６／℃程度となり，銅合金の線膨張係数１７×１０￣６／℃に比べチップの線膨張係数３×１０￣６／℃に近くなる。しかしながら，応力緩和のために４２ａｌｌｏｙ並の線膨張係数４〜５×１０￣６／℃が必要な場合は，Ｃｕ／Ｃｕ２Ｏ複合合金のＣｕ２Ｏの配合比を８０％にすれば，線膨張係数で５．５×１０￣６／℃，熱伝導率で４１Ｗ／（ｍＫ）が得られる。これは，４２ａｌｌｏｙの熱伝導率１５Ｗ／（ｍＫ）に比べ，２．７倍も大きい。このように，目的によって配合比率を自由に調整すればよい。
【０００９】
【発明の実施の形態】
本発明の第一実施例の半導体装置の断面図を図１に示す。半導体素子１は絶縁テープ２の表面に形成された配線３から延長されたビームリード４と素子電極５で電気的に接続されており，バンプランド６以外の配線３はレジスト７で被覆されている。バンプランド６には外部端子としてバンプ状電極８が接続されている。ビームリード４と半導体素子１の電極５との接続部は樹脂９によって封止されている。絶縁テープ２の配線形成面の裏面には，接着層１０を介して金属製のスティフナ１１が接着されている。スティフナ材料としては銅合金，アルミ合金，ステンレスなどが一般的である。スティフナ１１と半導体素子１の上表面の一部には，Ｃｕ／Ｃｕ２Ｏ複合合金製の平板状のヒートスプレッダ１２が接着層１３を介して接着されている。バンプ状電極８は，実装基板２３のフットプリント２５に電気的に接続される。半導体素子１への電気的なアクセスによって生じる熱は半導体素子１の裏面からヒートスプレッダ１２を介してスティフナ１１へ伝導し，バンプ状電極９を介して実装基板２３へ放熱される。バンプ状電極９には，例えば，はんだを用いる。この実装基板２３が線膨張係数が８×１０￣６／℃程度の低熱膨張基板である場合，第一実施例の構成の半導体装置を用いれば，構成部材間の線膨張係数差は縮小され，温度サイクル試験時や実環境でのオン・オフサイクルに対し，はんだの接続寿命を向上させることができる。図１の実施例において，金属製のスティフナ１１の線膨張係数は１７〜２２×１０￣６／℃であるが，ヒートスプレッダと同じＣｕ／Ｃｕ２Ｏ複合合金であれば，ヒートスプレッダ，および絶縁テープ（線膨張係数が約９×１０￣６／℃）との線膨張係数差が小さくなり，半導体パッケージの信頼性をさらに高めることができる。
【００１０】
本発明の第二実施例の半導体装置の断面図を図２に示す。半導体素子１は絶縁テープ２の表面に形成された配線３から延長されたビームリード４と素子電極５で電気的に接続されており，バンプランド６以外の配線３はレジスト７で被覆されている。バンプランド６には外部端子としてバンプ状電極８が接続されている。ビームリード４と半導体素子１の電極５との接続部は樹脂９によって封止されている。絶縁テープ２の配線形成面の裏面と半導体素子１の裏面には，接着層１０および接着層１２を介してキャビティを設けたＣｕ／Ｃｕ２Ｏ複合合金製のヒートスプレッダ１２が接着されている。キャビティは均一な厚さの板の切削加工か，あるいは型で焼結するなどして形成することができる。図２では，スティフナとヒートスプレッダが一体となった構成であり，接着層が一層削減されている。このため，放熱性は図１の構成より優れる。
【００１１】
本発明の第三実施例の半導体装置の断面図を図３に示す。半導体素子１は絶縁テープ２の表面に形成された配線３から延長されたビームリード４と素子電極５で電気的に接続されており，バンプランド６以外の配線３はレジスト７で被覆されている。バンプランド６には外部端子としてバンプ状電極８が接続されている。ビームリード４と半導体素子１の電極５との接続部は樹脂９によって封止されている。絶縁テープ２の配線形成面の裏面と半導体素子１の裏面には，接着層１０および接着層１２を介してキャビティを設けたＣｕ／Ｃｕ２Ｏ複合合金製のヒートスプレッダ１２が接着されている。キャビティは均一な厚さの板を曲げ加工するなどして形成することができる。図３では，ヒートスプレッダの厚さが均一であり，軽量化の点から図２の構成より優れている。
【００１２】
本発明の第四実施例の半導体装置の断面図を図４に示す。半導体素子１は樹脂基板１７の表面に形成された配線３から延長されたビームリード４と素子電極５で電気的に接続されており，バンプランド６以外の配線３はレジスト７で被覆されている。バンプランド６には外部端子としてバンプ状電極８が接続されている。ビームリード４と半導体素子１の電極５との接続部は樹脂９によって封止されている。樹脂基板１７の裏面，および半導体素子１の裏面には，接着層１０を介してＣｕ／Ｃｕ２Ｏ複合合金製の平板状のヒートスプレッダ１２が接着されている。樹脂基板１７には内層に配線２０やスルーホール１８が設けられているため，複雑な配線の引き回しが可能であり，テープを用いた図１から図３の構成よりも多くの出力端子を設けることができ，また内層にグランドや電源を設けられることから，高周波での動作特性にも優れる。
【００１３】
本発明の第五実施例の半導体装置の断面図を図５に示す。半導体素子１は樹脂基板１７に接着層２１を介して搭載され，樹脂基板の配線２０と半導体素子１はボンディングワイヤ１６で電気的な接続を行っている。樹脂基板の下面に設けられたバンプ状電極８はスルーホール１８を介して樹脂基板上面の配線２０と電気的に接続されている。樹脂基板の上面は樹脂９で封止され，その表面には接着層１５を介してＣｕ／Ｃｕ２Ｏ複合合金製のヒートスプレッダ１２が装着されている。樹脂基板には放熱のためにサーマルビア１９が設けられ，バンプ状電極を介して放熱する。
【００１４】
本発明の第六実施例の半導体装置の断面図を図六に示す。半導体素子１はＣｕ／Ｃｕ２Ｏ複合合金からなるヒートスプレッダ１２にぺ付け材２１で接着され，ボンディングワイヤ１６でリードフレームのリード２２と電気接続が行われている。半導体素子１と電気接続部は樹脂９で封止されている。リード２２は，実装基板２３のフットプリント２５にはんだ２４で接続される。ヒートスプレッダ１２の裏面は，封止樹脂下面に露出している。このヒートスプレッダ裏面を実装基板２３にはんだ付けすることにより，高放熱化を図ることができる。ヒートスプレッダ裏面がはんだ付けされる配線にはサーマルビア２８が設けられ，基板内層の面状配線へ放熱を促進する。第三実施例の半導体装置の従来例は，銅合金をヒートスプレッダに用いたＱｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ （ＱＦＰ）やＳｍａｌｌ Ｏｕｔｌｉｎｅ Ｐａｃｋａｇｅ （ＳＯＰ）などがある。外形が２８ｍｍ角の大型のＱＦＰには，ＡＳＩＣやマイコンなど素子面積も比較的大きいものが搭載される。この場合，ぺ付け材２には，剛性の大きいはんだを用いることができず，放熱性を犠牲にして柔らかい銀ペーストを用いている。しかしながら，本発明のＣｕ／Ｃｕ２Ｏ複合合金からなるリードフレーム材を用いれば，熱伝導の良いはんだによるぺ付けも可能となり，半導体装置の更なる高放熱化が可能となる。また，通常の高放熱パッケージのリードフレームには銅合金が用いられているが，リードフレームにＣｕ／Ｃｕ２Ｏ複合合金を用いれば，さらなる半導体装置の高信頼化が図れる。
【００１５】
本発明の第七実施例の半導体装置の断面図を図７に示す。半導体素子１はＣｕ／Ｃｕ２Ｏ複合合金からなるヒートスプレッダ１２にぺ付け材２１で接着され，ボンディングワイヤ１６でリードフレームのリード２２と電気接続が行われている。半導体素子１と電気接続部は樹脂９で封止されている。ヒートスプレッダ１２は，封止樹脂に内蔵されている。
【００１６】
本発明の第八実施例の半導体装置の別の断面図を図８に示す。半導体素子１はＣｕ／Ｃｕ２Ｏ複合合金からなるヒートスプレッダ１２にフェイスダウンにぺ付け材２１で接着され，ボンディングワイヤ１６でリードフレームのリード２２と電気接続が行われている。半導体素子１と電気接続部は樹脂９で封止されている。ヒートスプレッダ１２は，封止樹脂上部に露出している。図８の場合，ヒートスプレッダ露出面に放熱フィン（図示せず）を搭載すれば，更なる高放熱化を図ることができる。
【００１７】
【発明の効果】
本発明によれば、強度信頼性を確保しつつ，放熱性も高い半導体装置を提供することができる。
【図面の簡単な説明】
【図１】本願発明の第一実施例の半導体装置において，平板状のＣｕ／Ｃｕ２Ｏ複合合金を用いたヒートスプレッダを装着したテープ式ＢＧＡが基板に実装された断面図。
【図２】本願発明の第一実施例の半導体装置において，板厚変化によってキャビティを形成したＣｕ／Ｃｕ２Ｏ複合合金を用いたヒートスプレッダを装着したテープ式ＢＧＡの断面図。
【図３】本願発明の第一実施例の半導体装置において，クランクによってキャビティを形成したＣｕ／Ｃｕ２Ｏ複合合金を用いたヒートスプレッダを装着したテープ式ＢＧＡの断面図。
【図４】本願発明の第一実施例の半導体装置において，平板状のＣｕ／Ｃｕ２Ｏ複合合金を用いたヒートスプレッダを装着した樹脂基板式ＢＧＡが基板に実装された断面図。
【図５】本願発明の第二実施例の半導体装置において，封止樹脂表面にＣｕ／Ｃｕ２Ｏ複合合金を用いたヒートスプレッダを装着した樹脂基板式ＢＧＡの断面図。
【図６】本願発明の第三実施例の半導体装置において，半導体素子下面にＣｕ／Ｃｕ２Ｏ複合合金を用いた露出型のヒートスプレッダを接着したＨＱＦＰあるいは，ＨＳＯＰの断面図。
【図７】本願発明の第三実施例の半導体装置において，半導体素子下面にＣｕ／Ｃｕ２Ｏ複合合金を用いた内蔵型のヒートスプレッダを接着したＨＱＦＰあるいは，ＨＳＯＰの断面図。
【図８】本願発明の第三実施例の半導体装置において，半導体素子をフェイスダウンに搭載し，素子上面にＣｕ／Ｃｕ２Ｏ複合合金を用いた露出型のヒートスプレッダを接着したＨＱＦＰあるいは，ＨＳＯＰの断面図。
【符号の説明】
１…半導体素子，２…絶縁テープ，３…絶縁テープ上の配線，４…ビームリード，５…半導体素子の電極，６…バンプランド，７…レジスト，８…バンプ状電極，９…樹脂，１０…絶縁テープとスティフナ間の接着層，１１…スティフナ，１２…Ｃｕ／Ｃｕ２Ｏ複合合金のヒートスプレッダ，１３…ヒートスプレッダとスティフナ間の接着層，１４…ヒートスプレッダ下と半導体素子の接着層，１５…樹脂とヒートスプレッダ間の接着層，１６…ボンディングワイヤ，１７…樹脂基板，１８…樹脂基板のスルーホール，１９…樹脂基板のサーマルビア，２０…樹脂基板の配線，２１…半導体素子と樹脂基板間の接着層，２２…リードフレーム，２３…実装基板，２４…リードと実装基板のはんだ接合部，２５…実装基板のフットプリント，２６…実装基板のスルーホール，２７…リードとヒートスプレッダの絶縁接着層，２７…実装基板のサーマルビア。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device using a heat spreader.
[0002]
[Prior art]
A conventional technology of a structure that enhances heat dissipation of a fan-out type BGA in which external electrodes are arranged in a matrix around a face-down chip will be introduced. In the fan-out BGA, copper wiring is generally routed on a thin insulating tape or a resin substrate, and electrical connection with a semiconductor element is performed by a beam-like lead obtained by extending the copper wiring or wire bonding. When a thin insulating tape is used, the flatness of the external electrodes is maintained by attaching the thin insulating tape to a metal stiffener. In order to achieve high heat dissipation with this structure, the stiffener and the back surface of the semiconductor element should be placed in the same plane as in the Fan-out type BGA described in “Electronic Materials (page 37)” in the September 1997 issue. A heat spreader is attached, or only a heat spreader provided with a cavity without using a stiffener is mounted as disclosed in JP-A-7-283336 and JP-A-8-203958. In the September 1997 issue of “Electronic Materials (pages 65 to 66)”, it is necessary that the stiffener has sufficient rigidity as a characteristic required, and in general, the stiffener has a size of 0.25 mm to 0.35 mm. It is stated that a thick copper alloy or stainless steel is employed. Furthermore, it is described that the material of the heat spreader used together with the stiffener is oxygen-free copper or a copper alloy having high thermal conductivity. Further, as disclosed in Japanese Patent Application Laid-Open No. 9-213837, there is a structure of a fan-out type BGA using copper, aluminum, or an alloy thereof as a heat spreader.
[0003]
On the other hand, according to Nikkei Micro Devices (September 1989, pp. 96-99), resin-encapsulated Quad Flat Package (QFP) and SOP (Small Outline Package) using a conventional lead frame are made of copper alloy. An example is disclosed in which the heat spreader is crimped on a tie bar of a lead frame or bonded to a die pad portion to improve the heat dissipation of the semiconductor device. These heat spreaders are classified into two types: a type in which the heat spreader is built in the sealing resin due to the problem of moisture resistance, and a type in which aluminum fins are later mounted on the heat spreader or exposed on the surface for solder mounting on a mounting board. Since the copper alloy has a large difference in linear expansion coefficient from the semiconductor element, an epoxy or polyimide adhesive having a low Young's modulus is used as a joining material for the heat spreader.
[0004]
[Problems to be solved by the invention]
Linear expansion coefficient of the member of the semiconductor device, copper alloy used as a heat spreader material 17 × 10¯ 6 / ℃, aluminum 22 × 10¯ 6 / ℃, stainless steel 17 × 10¯ 6 / ℃, in the semiconductor device A certain silicon is 3 × 10 6 / ° C., and a sealing resin is 12 to 25 × 10 6 / ° C., which are greatly different from each other. For this reason, thermal stress is generated inside the semiconductor device in cooling from resin sealing or in a temperature cycle test for a reliability test. In the temperature cycle test, since this thermal stress is repeatedly applied, a fatigue crack may be generated in the resin from the end of the die pad or the lead frame, or the bonding wire or the wiring on the tape may be broken due to fatigue. In addition, in a temperature cycle test after mounting on a board or repeated on / off in an electronic device, fatigue failure may occur in the solder joints and solder bumps of the leads due to the difference in linear expansion coefficient between the semiconductor device and the mounting board. There is.
[0005]
In addition, in a multi-pin QFP equipped with a microcomputer or ASIC having a relatively large chip size or heat generation, a copper alloy lead frame has been used because of its low self-inductance, suitable for high-frequency operation, and high heat dissipation. Was. However, since the difference in linear expansion coefficient from the element is large, only an epoxy-based adhesive (such as silver paste) with a low Young's modulus can be used as a bonding material. It is difficult to bond with large solder.
[0006]
2. Description of the Related Art In recent small portable devices, small semiconductor devices that electrically connect with solder bumps having a structure called a Chip Scale Package (CSP) are increasing. The CSP has a large volume ratio of the element in the semiconductor device, and an apparent coefficient of linear expansion is close to the element side. For this reason, a low thermal expansion board whose linear expansion coefficient is reduced from about 15 × 10 6 / ° C. to about 8 × 10 6 / ° C. is generally used for a mounting board of a small portable device on which many CSPs are mounted. And the resin used is increasing in materials with low thermal expansion. For this reason, in a semiconductor device in which a heat spreader using a copper alloy is mounted or built in, a difference in linear expansion coefficient from a low-expansion substrate increases, and there is a concern that the life of the solder connection portion may be shortened and resin cracks may occur.
[0007]
An object of the present invention is to solve at least one of the above-mentioned problems, and to provide a semiconductor device having high strength and high heat dissipation while ensuring strength reliability.
[0008]
[Means for Solving the Problems]
The above object is solved, for example, by configuring a resin-sealed semiconductor device as follows. That is, a composite alloy of Cu 2 O and Cu sintered so as to have a low thermal expansion coefficient as compared with a copper alloy while having a high thermal conductivity comparable to that of a copper alloy conventionally used as a heat spreader material is used. . In the Cu / Cu 2 O composite alloy, the linear expansion coefficient, the thermal conductivity, and the Young's modulus decrease as the content of Cu 2 O increases (FIG. 9). Range investigated the physical properties of Cu / Cu 2 O composite alloy, 20～80Vol in mixing ratio of Cu 2 O. %, The thermal conductivity was 280 to 41 W / (mK) and the coefficient of linear expansion was 13.8 to 5.5 × 10 6 / ° C. For example, when a thermal conductivity of 150 W / (mK) or more equivalent to a copper alloy used for a semiconductor is required for high heat dissipation, the mixing ratio of Cu 2 O may be set to 20 to 46%. At this time, the coefficient of linear expansion of the Cu / Cu 2 O composite alloy is about 13.8 to 10.5 × 10 6 / ° C., which is smaller than the coefficient of linear expansion of the copper alloy of 17 × 10 6 / ° C. The coefficient approaches 3 × 10 6 / ° C. However, when a coefficient of linear expansion of 4 to 5 × 10 6 / ° C. equivalent to 42 alloy is required for stress relaxation, if the compounding ratio of Cu 2 O in the Cu / Cu 2 O composite alloy is set to 80%, the linear An expansion coefficient of 5.5 × 10 6 / ° C. and a thermal conductivity of 41 W / (mK) are obtained. This is 2.7 times larger than the thermal conductivity of 15 W / (mK) of 42 alloy. Thus, the mixing ratio may be freely adjusted according to the purpose.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention. The semiconductor element 1 is electrically connected to a beam lead 4 extending from the wiring 3 formed on the surface of the insulating tape 2 and an element electrode 5, and the wiring 3 other than the bump lands 6 is covered with a resist 7. . The bump land 6 is connected to a bump electrode 8 as an external terminal. The connection between the beam lead 4 and the electrode 5 of the semiconductor element 1 is sealed with a resin 9. A metal stiffener 11 is adhered to the back surface of the wiring forming surface of the insulating tape 2 via an adhesive layer 10. As a stiffener material, a copper alloy, an aluminum alloy, stainless steel or the like is generally used. A plate-shaped heat spreader 12 made of a Cu / Cu 2 O composite alloy is adhered to the stiffener 11 and a part of the upper surface of the semiconductor element 1 via an adhesive layer 13. The bump-shaped electrode 8 is electrically connected to the footprint 25 of the mounting board 23. Heat generated by electrical access to the semiconductor element 1 is conducted from the back surface of the semiconductor element 1 to the stiffener 11 via the heat spreader 12 and is radiated to the mounting substrate 23 via the bump-shaped electrode 9. For example, solder is used for the bump-shaped electrode 9. When the mounting substrate 23 is a low thermal expansion substrate having a linear expansion coefficient of about 8 × 10 6 / ° C., the difference in the linear expansion coefficient between the constituent members is reduced by using the semiconductor device of the first embodiment, The connection life of the solder can be improved for the temperature cycle test and the on / off cycle in the actual environment. In the embodiment of FIG. 1, the linear expansion coefficient of the metal stiffener 11 is 17 to 22 × 10 6 / ° C. However, if the Cu / Cu 2 O composite alloy is the same as the heat spreader, the heat spreader and the insulating tape ( The difference between the coefficient of linear expansion and the coefficient of linear expansion is approximately 9 × 10 6 / ° C.), and the reliability of the semiconductor package can be further improved.
[0010]
FIG. 2 is a sectional view of a semiconductor device according to a second embodiment of the present invention. The semiconductor element 1 is electrically connected to a beam lead 4 extending from the wiring 3 formed on the surface of the insulating tape 2 and an element electrode 5, and the wiring 3 other than the bump lands 6 is covered with a resist 7. . The bump land 6 is connected to a bump electrode 8 as an external terminal. The connection between the beam lead 4 and the electrode 5 of the semiconductor element 1 is sealed with a resin 9. A heat spreader 12 made of a Cu / Cu 2 O composite alloy having a cavity is bonded to the back surface of the wiring forming surface of the insulating tape 2 and the back surface of the semiconductor element 1 via an adhesive layer 10 and an adhesive layer 12. The cavity can be formed by cutting a plate having a uniform thickness, or by sintering in a mold. In FIG. 2, the stiffener and the heat spreader are integrated, and the adhesive layer is further reduced. For this reason, the heat dissipation is superior to the configuration of FIG.
[0011]
FIG. 3 is a sectional view of a semiconductor device according to a third embodiment of the present invention. The semiconductor element 1 is electrically connected to a beam lead 4 extending from the wiring 3 formed on the surface of the insulating tape 2 and an element electrode 5, and the wiring 3 other than the bump lands 6 is covered with a resist 7. . The bump land 6 is connected to a bump electrode 8 as an external terminal. The connection between the beam lead 4 and the electrode 5 of the semiconductor element 1 is sealed with a resin 9. A heat spreader 12 made of a Cu / Cu 2 O composite alloy having a cavity is bonded to the back surface of the wiring forming surface of the insulating tape 2 and the back surface of the semiconductor element 1 via an adhesive layer 10 and an adhesive layer 12. The cavity can be formed by bending a plate having a uniform thickness. In FIG. 3, the thickness of the heat spreader is uniform, which is superior to the configuration of FIG. 2 in terms of weight reduction.
[0012]
FIG. 4 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention. The semiconductor element 1 is electrically connected to a beam lead 4 extending from the wiring 3 formed on the surface of the resin substrate 17 and an element electrode 5, and the wiring 3 other than the bump lands 6 is covered with a resist 7. . The bump land 6 is connected to a bump electrode 8 as an external terminal. The connection between the beam lead 4 and the electrode 5 of the semiconductor element 1 is sealed with a resin 9. A plate-shaped heat spreader 12 made of a Cu / Cu 2 O composite alloy is adhered to the back surface of the resin substrate 17 and the back surface of the semiconductor element 1 via an adhesive layer 10. Since the wiring 20 and the through-holes 18 are provided in the inner layer of the resin substrate 17, complicated wiring can be routed, and more output terminals are provided than in the configuration of FIGS. 1 to 3 using a tape. Since the ground and the power supply are provided in the inner layer, the operating characteristics at high frequencies are also excellent.
[0013]
FIG. 5 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention. The semiconductor element 1 is mounted on a resin substrate 17 via an adhesive layer 21, and the wiring 20 of the resin substrate and the semiconductor element 1 are electrically connected by bonding wires 16. The bump-shaped electrode 8 provided on the lower surface of the resin substrate is electrically connected to the wiring 20 on the upper surface of the resin substrate via the through hole 18. The upper surface of the resin substrate is sealed with a resin 9, and a heat spreader 12 made of a Cu / Cu 2 O composite alloy is mounted on the surface via an adhesive layer 15. A thermal via 19 is provided on the resin substrate for heat dissipation, and heat is dissipated through bump-shaped electrodes.
[0014]
FIG. 6 is a sectional view of a semiconductor device according to a sixth embodiment of the present invention. The semiconductor element 1 is bonded to a heat spreader 12 made of a Cu / Cu 2 O composite alloy with an adhesive 21, and is electrically connected to leads 22 of a lead frame by bonding wires 16. The semiconductor element 1 and the electrical connection are sealed with a resin 9. The lead 22 is connected to the footprint 25 of the mounting board 23 with solder 24. The back surface of the heat spreader 12 is exposed on the lower surface of the sealing resin. By soldering the back surface of the heat spreader to the mounting substrate 23, high heat radiation can be achieved. A thermal via 28 is provided in the wiring to which the back surface of the heat spreader is soldered, and promotes heat radiation to the planar wiring in the inner layer of the substrate. Conventional examples of the semiconductor device of the third embodiment include Quad Flat Package (QFP) and Small Outline Package (SOP) using a copper alloy for a heat spreader. A large QFP having an external shape of 28 mm square is mounted with an ASIC or microcomputer having a relatively large element area. In this case, a solder having high rigidity cannot be used as the bonding material 2, and a soft silver paste is used at the expense of heat dissipation. However, if the lead frame material made of the Cu / Cu 2 O composite alloy of the present invention is used, soldering with good heat conductivity can be performed, and the heat dissipation of the semiconductor device can be further increased. Further, although a copper alloy is used for the lead frame of the ordinary high heat dissipation package, if a Cu / Cu 2 O composite alloy is used for the lead frame, the reliability of the semiconductor device can be further improved.
[0015]
FIG. 7 is a sectional view of a semiconductor device according to a seventh embodiment of the present invention. The semiconductor element 1 is bonded to a heat spreader 12 made of a Cu / Cu 2 O composite alloy with an adhesive 21, and is electrically connected to leads 22 of a lead frame by bonding wires 16. The semiconductor element 1 and the electrical connection are sealed with a resin 9. The heat spreader 12 is built in the sealing resin.
[0016]
FIG. 8 shows another sectional view of the semiconductor device according to the eighth embodiment of the present invention. The semiconductor element 1 is bonded face down to a heat spreader 12 made of a Cu / Cu 2 O composite alloy with an adhesive 21, and is electrically connected to a lead 22 of a lead frame by a bonding wire 16. The semiconductor element 1 and the electrical connection are sealed with a resin 9. The heat spreader 12 is exposed above the sealing resin. In the case of FIG. 8, if a heat radiating fin (not shown) is mounted on the exposed surface of the heat spreader, higher heat radiation can be achieved.
[0017]
【The invention's effect】
According to the present invention, it is possible to provide a semiconductor device having high heat dissipation while ensuring strength reliability.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention, in which a tape-type BGA equipped with a heat spreader using a flat Cu / Cu 2 O composite alloy is mounted on a substrate.
FIG. 2 is a cross-sectional view of a tape-type BGA equipped with a heat spreader using a Cu / Cu 2 O composite alloy in which a cavity is formed by a change in plate thickness in the semiconductor device according to the first embodiment of the present invention;
FIG. 3 is a cross-sectional view of a tape-type BGA equipped with a heat spreader using a Cu / Cu 2 O composite alloy having a cavity formed by a crank in the semiconductor device according to the first embodiment of the present invention.
FIG. 4 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention, in which a resin substrate type BGA to which a heat spreader using a flat Cu / Cu 2 O composite alloy is mounted is mounted on a substrate.
FIG. 5 is a sectional view of a resin substrate type BGA in which a heat spreader using a Cu / Cu 2 O composite alloy is mounted on a sealing resin surface in a semiconductor device according to a second embodiment of the present invention.
FIG. 6 is a cross-sectional view of an HQFP or an HSOP in which an exposed heat spreader using a Cu / Cu 2 O composite alloy is adhered to a lower surface of a semiconductor element in a semiconductor device according to a third embodiment of the present invention.
FIG. 7 is a cross-sectional view of an HQFP or HSOP in which a built-in heat spreader using a Cu / Cu 2 O composite alloy is adhered to the lower surface of a semiconductor element in a semiconductor device according to a third embodiment of the present invention.
FIG. 8 shows a semiconductor device according to a third embodiment of the present invention, in which a semiconductor element is mounted face down and an HQFP or HSOP having an exposed heat spreader using a Cu / Cu 2 O composite alloy adhered to the upper surface of the element. Sectional view.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Insulating tape, 3 ... Wiring on insulating tape, 4 ... Beam lead, 5 ... Electrode of semiconductor element, 6 ... Bump land, 7 ... Resist, 8 ... Bump-shaped electrode, 9 ... Resin, 10 ... adhesive layer between the insulating tape and the stiffener, 11 ... stiffener, 12 ... Cu / Cu 2 O composite alloy heat spreader, 13 ... heat spreader and the adhesive layer between the stiffener, 14 ... adhesive layer of the heat spreader under the semiconductor element, 15 ... resin Adhesive layer between heat spreader and heat spreader, 16 bonding wire, 17 resin substrate, 18 through hole in resin substrate, 19 thermal via in resin substrate, 20 wiring in resin substrate, 21 adhesion between semiconductor element and resin substrate Layer, 22: lead frame, 23: mounting board, 24: solder joint between lead and mounting board, 25: footprint of mounting board, 6 ... mounting board through hole, 27 ... lead and the insulating adhesive layer of the heat spreader, 27 ... mounting substrate of the thermal vias.

Claims (5)

半導体素子と、
一端が前記半導体素子の回路形成面に形成された電極と電気的に接続されたリードと、
前記リードから延長された配線に電気的に接続された外部端子と、
前記半導体素子の前記回路形成面とは反対側に配設されたCu/Cu ２ O複合合金ヒートスプレッダと、
前記リードと前記電極の接続部を被覆する樹脂と、
を備えたことを特徴とする半導体装置。A semiconductor element;
A lead having one end electrically connected to an electrode formed on a circuit formation surface of the semiconductor element;
An external terminal electrically connected to wiring extended from the lead;
A Cu / Cu 2 O composite alloy heat spreader disposed on the side opposite to the circuit forming surface of the semiconductor element;
A resin covering a connection portion between the lead and the electrode ,
A semiconductor device comprising: 請求項１に記載の半導体装置において、
前記Cu/Cu 2 O複合合金のCu 2 O含有率が20〜80Vol.％であることを特徴とする半導体装置。 The semiconductor device according to claim 1 ,
Wherein a Cu 2 O content of the Cu / Cu 2 O alloy composite is 20~80Vol.%. 請求項１に記載の半導体装置において、
前記配線が絶縁性テープあるいは絶縁性樹脂基板の少なくとも一面に形成されていることを特徴とする半導体装置。 The semiconductor device according to claim 1 ,
A semiconductor device, wherein the wiring is formed on at least one surface of an insulating tape or an insulating resin substrate. 半導体素子と、
マトリックス状に配置された外部端子と、
前記半導体素子と前記外部端子とを電気的に接続する配線を有する樹脂基板とを有し、
前記半導体素子と、前記樹脂基板の前記配線を有する側とが封止樹脂によって保護され、
前記封止樹脂の表面にヒートスプレッダが搭載され、
前記ヒートスプレッダがCu 2 Oを20〜80Vol.％含むCu/Cu 2 O複合合金であることを特徴とする半導体装置。A semiconductor element;
External terminals arranged in a matrix,
And a resin substrate having a wiring which electrically connects the external terminal and said semiconductor element,
The semiconductor element and the side having the wiring of the resin substrate are protected by a sealing resin ,
A heat spreader is mounted on the surface of the sealing resin ,
Wherein a said heat spreader is a Cu / Cu 2 O composite alloy containing Cu 2 O 20~80Vol.%. 半導体素子と、
リードフレームと、
前記半導体素子と前記リードフレームとを電気的に接続するボンディングワイヤとを有し、
前記半導体素子と、前記ボンディングワイヤと前記リードフレームとの電気接続部と、が封止樹脂によって保護され、
前記半導体素子の裏面にヒートスプレッダが搭載され、
前記ヒートスプレッダがCu 2 Oを20〜80Vol.％含むCu/Cu 2 O複合合金であることを特徴とする半導体装置。A semiconductor element ;
A lead frame ,
And a bonding wire for electrically connecting the lead frame and the semiconductor element,
The semiconductor element , the electrical connection between the bonding wire and the lead frame , is protected by a sealing resin ,
A heat spreader is mounted on the back surface of the semiconductor element ,
Wherein a said heat spreader is a Cu / Cu 2 O composite alloy containing Cu 2 O 20~80Vol.%.
JP2000024694A 2000-01-28 2000-01-28 Semiconductor device Expired - Fee Related JP3561671B2 (en)

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JP4646642B2 (en) * 2005-01-27 2011-03-09 京セラ株式会社 Package for semiconductor devices
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