JP2002050758A - Compound semiconductor epitaxial wafer and transistor using the same - Google Patents
Compound semiconductor epitaxial wafer and transistor using the sameInfo
- Publication number
- JP2002050758A JP2002050758A JP2000240379A JP2000240379A JP2002050758A JP 2002050758 A JP2002050758 A JP 2002050758A JP 2000240379 A JP2000240379 A JP 2000240379A JP 2000240379 A JP2000240379 A JP 2000240379A JP 2002050758 A JP2002050758 A JP 2002050758A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- epitaxial wafer
- algan
- gan
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 150000001875 compounds Chemical class 0.000 title claims abstract description 13
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 229910002704 AlGaN Inorganic materials 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 11
- 229910052594 sapphire Inorganic materials 0.000 claims description 8
- 239000010980 sapphire Substances 0.000 claims description 8
- 239000004047 hole gas Substances 0.000 abstract description 4
- 230000006698 induction Effects 0.000 abstract description 3
- 229910002601 GaN Inorganic materials 0.000 description 26
- 239000000969 carrier Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 4
- 239000002994 raw material Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 229910017083 AlN Inorganic materials 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 2
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- -1 G aN Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000002484 cyclic voltammetry Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、化合物半導体エピ
タキシャルウェハ及びそれを用いたトランジスタに関す
る。[0001] 1. Field of the Invention [0002] The present invention relates to a compound semiconductor epitaxial wafer and a transistor using the same.
【０００２】[0002]
【従来の技術】窒化ガリウム系の電界効果トランジスタ
（以下「ＦＥＴ」という。）としては、従来、ｎ型Ｇａ
Ｎをチャンネル層とするＦＥＴ及びｎ型ＡｌＧａＮ／Ｇ
ａＮ選択ドープ構造を有するＦＥＴの研究開発が進めら
れている。2. Description of the Related Art As a gallium nitride-based field effect transistor (hereinafter, referred to as "FET"), an n-type Ga
FET with N as channel layer and n-type AlGaN / G
Research and development of FETs having an aN selective doping structure are in progress.
【０００３】[0003]
【発明が解決しようとする課題】ところで、上述した従
来技術のＦＥＴは全てデバイス動作に関わる主たるキャ
リアが電子のｎ型ＦＥＴである。ここで、正孔をキャリ
アとするｐ型ＦＥＴがあれば、Ｃ−ＭＯＳトランジスタ
のように相補型のＦＥＴが実現でき、負電源が不要にな
る。By the way, all of the above-mentioned conventional FETs are n-type FETs whose main carriers involved in device operation are electrons. Here, if there is a p-type FET using holes as carriers, a complementary FET like a C-MOS transistor can be realized, and a negative power supply is not required.
【０００４】しかしながら正孔をキャリアとするＦＥＴ
は実用化が困難である。特に、ｐ型ＡｌＧａＮ／ＧａＮ
選択ドープ構造では、ピエゾ効果のために界面に電子が
誘起され、所望の正孔を発生させることができないとい
う問題があった。However, FETs using holes as carriers
Is difficult to put into practical use. In particular, p-type AlGaN / GaN
The selective doping structure has a problem in that electrons are induced at the interface due to the piezo effect, so that desired holes cannot be generated.
【０００５】そこで、本発明の目的は、上記課題を解決
し、正孔をキャリアとする化合物半導体エピタキシャル
ウェハ及びそれを用いたトランジスタを提供することに
ある。Accordingly, an object of the present invention is to solve the above problems and to provide a compound semiconductor epitaxial wafer using holes as carriers and a transistor using the same.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するため
に本発明の化合物半導体エピタキシャルウェハは、サフ
ァイア基板上に、ＧａＮ、ＡｌＧａＮ及びＡｌＮのうち
少なくともＡｌＧａＮを有するバッファ層を形成し、バ
ッファ層の上にＧａＮ及びｐ型ＡｌＧａＮのヘテロ接合
を形成し、バッファ層のＡｌＧａＮ層の膜厚をエピタキ
シャルウェハ全体におけるＧａＮ層の膜厚より厚くした
ものである。In order to achieve the above object, a compound semiconductor epitaxial wafer of the present invention forms a buffer layer having at least AlGaN among GaN, AlGaN and AlN on a sapphire substrate, A heterojunction of GaN and p-type AlGaN is formed thereon, and the thickness of the AlGaN layer of the buffer layer is larger than the thickness of the GaN layer in the entire epitaxial wafer.
【０００７】上記構成に加え本発明の化合物半導体エピ
タキシャルウェハは、バッファ層のＡｌＧａＮのＡｌＮ
の組成比がｐ型ＡｌＧａＮのＡｌＮ組成比より高いのが
好ましい。In addition to the above structure, the compound semiconductor epitaxial wafer of the present invention provides
Is preferably higher than the AlN composition ratio of p-type AlGaN.
【０００８】本発明のトランジスタは上記構成のエピタ
キシャルウェハを用いたものである。[0008] The transistor of the present invention uses the epitaxial wafer having the above structure.
【０００９】本発明によれば、ｐ型ＡｌＧａＮ／ＧａＮ
選択ドープ構造で、界面に電子が誘起される原因は、キ
ャリア供給層であるＡｌＧａＮがチャネル層であるＧａ
Ｎより線膨張係数が大きいため、ＡｌＧａＮキャリア供
給層に成膜後の冷却中に弾性応力によって生じる引っ張
り歪である。ＡｌＧａＮキャリア供給層のピエゾ効果が
大きいため、この引っ張り歪に応じて界面にキャリアが
誘起される。ＧａＮ系の材料のエピタキシャル成長用の
基板には、通常サファイアもしくはＳｉＣの単結晶が用
いられる。この基板の上にＧａＮをｃ軸配向して成長さ
せる場合、Ｇａ面が上になるように成長（Ｇａ面成長）
させる方法が安定であることが知られている。このＧａ
面成長はピエゾ分極の方向が必ず界面に電子を誘起する
方向となり、正孔を界面に形成する阻害要因となる。界
面に正孔を誘起するためには、Ｇａ面とは反対のＮ面が
上になる成長（Ｎ面成長）が必要となるが、このＮ面成
長は不安定な成長となり、良い結晶が得られない。According to the present invention, a p-type AlGaN / GaN
In the selective doping structure, electrons are induced at the interface because the carrier supply layer AlGaN is formed by the channel layer Ga
Since the coefficient of linear expansion is larger than that of N, the tensile strain is generated by elastic stress during cooling after film formation on the AlGaN carrier supply layer. Since the piezo effect of the AlGaN carrier supply layer is large, carriers are induced at the interface according to the tensile strain. A sapphire or SiC single crystal is usually used for a substrate for epitaxial growth of a GaN-based material. When GaN is grown on this substrate with c-axis orientation, the GaN is grown so that the Ga surface faces upward (Ga surface growth)
It is known that the method for causing the above is stable. This Ga
In the plane growth, the direction of piezo polarization always becomes a direction in which electrons are induced at the interface, which is a hindrance factor for forming holes at the interface. In order to induce holes at the interface, it is necessary to grow the N-plane opposite to the Ga-plane (N-plane growth). However, this N-plane growth is unstable growth, and a good crystal is obtained. I can't.
【００１０】本発明ではチャネル層となるＧａＮ層の下
部に、ＡｌＧａＮキャリア供給層と線膨張係数が等しい
か大きいバッファ層を十分な厚さで挿入することによ
り、ＡｌＧａＮキャリア供給層に生じる引っ張り歪を緩
和し、ヘテロ界面への電子の誘起を押さえて２次元正孔
ガスを発生させることができ、この結果、正孔をキャリ
アとするｐ型ＦＥＴを実現することができる。In the present invention, the tensile strain generated in the AlGaN carrier supply layer can be reduced by inserting a buffer layer having a linear expansion coefficient equal to or larger than that of the AlGaN carrier supply layer at a sufficient thickness below the GaN layer serving as the channel layer. The two-dimensional hole gas can be generated by alleviating the relaxation and suppressing the induction of electrons at the hetero interface, and as a result, a p-type FET using holes as carriers can be realized.
【００１１】[0011]
【発明の実施の形態】以下、本発明の実施の形態を添付
図面に基づいて詳述する。Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
【００１２】図１は本発明の化合物半導体エピタキシャ
ルウェハの一実施の形態を示す構造図である。FIG. 1 is a structural view showing one embodiment of the compound semiconductor epitaxial wafer of the present invention.
【００１３】同図に示すエピタキシャルウェハ１は、サ
ファイア基板２上に、厚さ２０ｎｍのｉ−ＧａＮ層３、
厚さ５μｍのｉ−Ａｌ0.3 Ｇａ0.7 Ｎ層４、厚さ１μｍ
のチャネル層としてのｉ−ＧａＮ層５及び厚さ２０ｎｍ
のキャリア供給層としてのｐ−Ａｌ0.2 Ｇａ0.8 Ｎ層６
を順次形成したものである。An epitaxial wafer 1 shown in FIG. 1 has an i-GaN layer 3 having a thickness of 20 nm on a sapphire substrate 2.
I-Al 0.3 Ga 0.7 N layer 4 having a thickness of 5 μm and a thickness of 1 μm
I-GaN layer 5 as a channel layer and a thickness of 20 nm
P-Al 0.2 Ga 0.8 N layer 6 as a carrier supply layer
Are sequentially formed.
【００１４】ｉ−Ａｌ0.3 Ｇａ0.7 Ｎ層４及びｉ−Ｇａ
Ｎ層５でバッファ層７を形成し、ｐ−Ａｌ0.2 Ｇａ0.8
Ｎ層４及びｉ−ＧａＮ層５でヘテロ接合を形成してい
る。The i-Al 0.3 Ga 0.7 N layer 4 and the i-Ga
A buffer layer 7 is formed from the N layer 5 and p-Al 0.2 Ga 0.8
A heterojunction is formed by the N layer 4 and the i-GaN layer 5.
【００１５】このエピタキシャルウェハ１のエピタキシ
ャル成長には有機金属気相成長法を用いた。ガリウム原
料にはＴＭＧ（トリメチルガリウム）を用い、アルミニ
ウム原料にはＴＭＡ（トリメチルアルミニウム）を用
い、窒素原料にはアンモニアガスを用い、ｐ型ドーパン
トとしては、ビスシクロペンタマグネシウムを用いた。
シリコン原料にはモノシランを用いた。エピタキシャル
成長はフェイスアップの高周波誘導加熱横型減圧炉（図
示せず。）を用いて炉内圧力１７９５５Ｐａ（１３５Ｔ
ｏｒｒ）で行った。基板２にはＡ面及びＣ面のサファイ
ア単結晶基板を用いた。エピタキシャル成長時の基板温
度は１０５０℃である。For the epitaxial growth of the epitaxial wafer 1, a metal organic chemical vapor deposition method was used. TMG (trimethylgallium) was used as a gallium raw material, TMA (trimethylaluminum) was used as an aluminum raw material, ammonia gas was used as a nitrogen raw material, and biscyclopentamagnesium was used as a p-type dopant.
Monosilane was used as a silicon raw material. The epitaxial growth is performed using a face-up high-frequency induction heating horizontal vacuum furnace (not shown) with a furnace pressure of 17955 Pa (135 T).
orr). A sapphire single crystal substrate having A-plane and C-plane was used as the substrate 2. The substrate temperature during epitaxial growth is 1050 ° C.
【００１６】このようにして成長させたエピタキシャル
ウェハ１のＣ−Ｖ測定で求めたキャリア濃度プロファイ
ルを図２に示す。FIG. 2 shows a carrier concentration profile obtained by CV measurement of the epitaxial wafer 1 thus grown.
【００１７】図２は図１に示したエピタキシャルウェハ
のキャリア濃度と深さとの関係を示す図であり、横軸が
深さ軸を示し、縦軸がキャリア濃度軸を示す。FIG. 2 is a diagram showing the relationship between the carrier concentration and the depth of the epitaxial wafer shown in FIG. 1. The horizontal axis shows the depth axis, and the vertical axis shows the carrier concentration axis.
【００１８】同図よりピークは界面に２次元正孔ガスが
生じていることを示しており、従来の問題点は解決でき
ることが分った。このピークからシート正孔濃度を求
め、バッファ層７に用いられているＡｌＧａＮの組成、
膜厚との関係を示したのが表１である。FIG. 1 shows that a two-dimensional hole gas is generated at the interface, which proves that the conventional problems can be solved. From this peak, the sheet hole concentration was determined, and the composition of AlGaN used in the buffer layer 7 was determined.
Table 1 shows the relationship with the film thickness.
【００１９】[0019]
【表１】 [Table 1]
【００２０】同表より、ＡｌＧａＮのＡｌＮ組成比を供
給層の組成比より下げたり、あるいは膜厚をＧａＮの総
膜厚より薄くした場合に、２次元正孔ガスの濃度が低下
する傾向があることが分る。これは、前述のようにバッ
ファ層７のＡｌＧａＮバッファ層４の効果が薄れてＧａ
Ｎ層３の影響が相対的に高まったためと見られる。According to the table, when the AlN composition ratio of AlGaN is made lower than the composition ratio of the supply layer or the film thickness is made thinner than the total film thickness of GaN, the two-dimensional hole gas concentration tends to decrease. I understand. This is because the effect of the AlGaN buffer layer 4 of the buffer layer 7 is weakened as described above.
It is considered that the influence of the N layer 3 was relatively increased.
【００２１】図３は図１に示したエピタキシャルウェハ
を用いたトランジスタの構造図である。なお、数値につ
いては限定されるものではない。FIG. 3 is a structural diagram of a transistor using the epitaxial wafer shown in FIG. The numerical values are not limited.
【００２２】図３に示すトランジスタ１０は、サファイ
ア基板２上に、厚さ２０ｎｍのｉ−ＧａＮ層３、厚さ５
μｍのｉ−Ａｌ0.3 Ｇａ0.7 Ｎ層４、厚さ１μｍのチャ
ネル層としてのｉ−ＧａＮ層５及び厚さ２０ｎｍのキャ
リア供給層としてのｐ−Ａｌ0.2 Ｇａ0.8 Ｎ層６を順次
形成し、このｐ−Ａｌ0.2 Ｇａ0.8 Ｎ層６の上にソース
電極１１、ゲート電極（ゲート長さＬｇ＝１μｍ）１２
及びドレイン電極１３を形成したものである。The transistor 10 shown in FIG. 3 has an i-GaN layer 3 having a thickness of 20 nm and a thickness of 5 on a sapphire substrate 2.
An i-Al 0.3 Ga 0.7 N layer 4 having a thickness of 1 μm, an i-GaN layer 5 serving as a channel layer having a thickness of 1 μm, and a p-Al 0.2 Ga 0.8 N layer 6 serving as a carrier supply layer having a thickness of 20 nm are sequentially formed. A source electrode 11 and a gate electrode (gate length Lg = 1 μm) 12 on the p-Al 0.2 Ga 0.8 N layer 6
And a drain electrode 13 are formed.
【００２３】図４は図３に示したトランジスタの静特性
を示す図であり、横軸がドレイン電圧Ｖｄ軸を示し、縦
軸がドレイン電流Ｉｄ軸を示す。FIG. 4 is a diagram showing the static characteristics of the transistor shown in FIG. 3. The horizontal axis shows the drain voltage Vd axis, and the vertical axis shows the drain current Id axis.
【００２４】同図より、ｐ型ＦＥＴが通常のｎ型ＦＥＴ
と同様の静特性を有することが分る。As shown in the figure, the p-type FET is a normal n-type FET.
It can be seen that it has the same static characteristic as
【００２５】ここで、バッファ層７としては、（Ｇａ
Ｎ、ＡｌＧａＮ）、（ＡｌＮ、ＡｌＧａＮ）、（Ａｌ
Ｎ、ＧａＮ、ＡｌＧａＮ）、（ＧａＮ、ＡｌＧａＮ、Ｇ
ａＮ、ＡｌＧａＮ）、（ＡｌＮ、ＡｌＧａＮ、ＧａＮ、
ＡｌＧａＮ）、（ＧａＮ、Ａｌ0.3 Ｇａ0.1 Ｎ、Ａｌ
0.1 Ｇａ0.9 Ｎ、Ａｌ0.3 Ｇａ0.7 Ｎ）の組み合わせが
挙げられる。但し、（）内の左側が基板側、右側が電極
側になる。Here, as the buffer layer 7, (Ga
N, AlGaN), (AlN, AlGaN), (Al
N, GaN, AlGaN), (GaN, AlGaN, G
aN, AlGaN), (AlN, AlGaN, GaN,
AlGaN), (GaN, Al 0.3 Ga 0.1 N, Al
0.1 Ga 0.9 N, Al 0.3 Ga 0.7 N). However, the left side in () is the substrate side, and the right side is the electrode side.
【００２６】このように構成したことで、チャネル層５
の下部に、キャリア供給層６と線膨張係数が等しいか大
きなＡｌＧａＮバッファ層４を挿入する場合、チャネル
層５とＡｌＧａＮバッファ層４との間の格子定数の違い
に起因する臨界膜厚が存在する。この臨界膜厚を超える
厚さで挿入すると、結晶性欠陥が生じてデバイス特性の
劣化を招くおそれがある。この劣化を防止するために
は、サファイア基板２上にもしＧａＮバッファ層３を成
長させたい場合でも、このＧａＮバッファ層３を５００
℃付近で成長させる、いわゆる低温成長バッファのみと
し、その他のバッファ層はＡｌＧａＮ層とすることによ
って、積層構造全体としての線膨張係数をキャリア供給
層６に近付け、それによってＡｌＧａＮバッファ層４の
弾性歪を低減する方法が有効である。この場合はＧａＮ
バッファ層３が圧縮応力を受けるが、本発明ではＧａＮ
バッファ層３として必要な厚さが薄いため、問題が生じ
ない。With this configuration, the channel layer 5
When an AlGaN buffer layer 4 having the same or larger linear expansion coefficient as that of the carrier supply layer 6 is inserted below the carrier supply layer 6, there is a critical thickness caused by a difference in lattice constant between the channel layer 5 and the AlGaN buffer layer 4. . Insertion with a thickness exceeding this critical thickness may cause a crystalline defect to cause deterioration of device characteristics. In order to prevent this deterioration, even if it is desired to grow the GaN buffer layer 3 on the sapphire
By forming only a so-called low-temperature growth buffer grown at around 0 ° C. and using an AlGaN layer as the other buffer layer, the linear expansion coefficient of the entire laminated structure is made closer to the carrier supply layer 6, whereby the elastic strain of the AlGaN buffer layer 4 is reduced. Is effective. In this case GaN
Although the buffer layer 3 receives a compressive stress, in the present invention, GaN
Since the thickness required for the buffer layer 3 is small, no problem occurs.
【００２７】以上において本発明の化合物半導体エピタ
キシャルウェハを用いたトランジスタによるｐ型ＦＥＴ
を、ｎ型ＦＥＴと組み合わせることで相補型のトランジ
スタを構成することができ、負電源が不要になり、回路
構成が簡単になり、小形化、低コスト化が図れる。In the above, a p-type FET using a transistor using the compound semiconductor epitaxial wafer of the present invention
Can be combined with an n-type FET to form a complementary transistor, which eliminates the need for a negative power supply, simplifies the circuit configuration, and enables downsizing and cost reduction.
【００２８】[0028]
【発明の効果】以上要するに本発明によれば、次のよう
な優れた効果を発揮する。In summary, according to the present invention, the following excellent effects are exhibited.
【００２９】正孔をキャリアとする化合物半導体エピタ
キシャルウェハ及びそれを用いたトランジスタの提供を
実現することができる。It is possible to provide a compound semiconductor epitaxial wafer using holes as carriers and a transistor using the same.
【図１】本発明の化合物半導体エピタキシャルウェハの
一実施の形態を示す構造図である。FIG. 1 is a structural diagram showing one embodiment of a compound semiconductor epitaxial wafer of the present invention.
【図２】図１に示したエピタキシャルウェハのキャリア
濃度と深さとの関係を示す図である。FIG. 2 is a diagram showing a relationship between a carrier concentration and a depth of the epitaxial wafer shown in FIG.
【図３】図１に示したエピタキシャルウェハを用いたト
ランジスタの構造図である。FIG. 3 is a structural diagram of a transistor using the epitaxial wafer shown in FIG.
【図４】図３に示したトランジスタの静特性を示す図で
ある。FIG. 4 is a diagram showing static characteristics of the transistor shown in FIG.
２ サファイア基板 ３ ＧａＮ層（ＧａＮバッファ層） ４ ＡｌＧａＮ層（ＡｌＧａＮバッファ層） ５ ＧａＮ層（チャネル層） ６ ＡｌＧａＮ層（キャリア供給層） ７ バッファ層 2 Sapphire substrate 3 GaN layer (GaN buffer layer) 4 AlGaN layer (AlGaN buffer layer) 5 GaN layer (channel layer) 6 AlGaN layer (carrier supply layer) 7 Buffer layer
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 4G077 AA03 BE11 BE13 BE15 DB01 ED06 EF03 5F045 AB14 AB17 AD14 AE25 AF09 CA06 DA53 DP02 DQ06 EH11 5F102 GB01 GC01 GD01 GJ10 GK04 GL04 GM04 GQ03 GQ09 HC01 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4G077 AA03 BE11 BE13 BE15 DB01 ED06 EF03 5F045 AB14 AB17 AD14 AE25 AF09 CA06 DA53 DP02 DQ06 EH11 5F102 GB01 GC01 GD01 GJ10 GK04 GL04 GM04 GQ03 GQ09 HC01
Claims (3)
Ｎ及びＡｌＮのうち少なくともＡｌＧａＮを有するバッ
ファ層を形成し、該バッファ層の上にＧａＮ及びｐ型Ａ
ｌＧａＮのヘテロ接合を形成し、上記バッファ層のＡｌ
ＧａＮ層の膜厚をエピタキシャルウェハ全体におけるＧ
ａＮ層の膜厚より厚くしたことを特徴とする化合物半導
体エピタキシャルウェハ。1. A sapphire substrate on which GaN, AlGa
Forming a buffer layer having at least AlGaN of N and AlN, and forming GaN and p-type A on the buffer layer;
A heterojunction of lGaN is formed, and the buffer layer Al
The thickness of the GaN layer is set to G
A compound semiconductor epitaxial wafer having a thickness greater than the thickness of the aN layer.
ｌＧａＮのＡｌＮの組成比がｐ型ＡｌＧａＮのＡｌＮ組
成比より高い化合物半導体エピタキシャルウェハ。2. The buffer layer according to claim 1, wherein
A compound semiconductor epitaxial wafer wherein the composition ratio of AlN in 1GaN is higher than the composition ratio of AlN in p-type AlGaN.
ルウェハを用いた化合物半導体エピタキシャルウェハを
用いたトランジスタ。3. A transistor using a compound semiconductor epitaxial wafer using the epitaxial wafer according to claim 1 or 2.
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|---|---|---|---|
| JP2000240379A JP2002050758A (en) | 2000-08-03 | 2000-08-03 | Compound semiconductor epitaxial wafer and transistor using the same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000240379A JP2002050758A (en) | 2000-08-03 | 2000-08-03 | Compound semiconductor epitaxial wafer and transistor using the same |
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ID=18731749
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005158889A (en) * | 2003-11-21 | 2005-06-16 | Sanken Electric Co Ltd | Plate-shaped substrate for forming semiconductor element, its manufacturing method, and semiconductor element using it |
| WO2007122800A1 (en) * | 2006-03-29 | 2007-11-01 | Nec Corporation | Field effect transistor |
| US7329908B2 (en) * | 2003-09-05 | 2008-02-12 | The Furukawa Electric Co., Ltd. | Nitride-based compound semiconductor electron device including a buffer layer structure |
| JP2008135575A (en) * | 2006-11-28 | 2008-06-12 | Furukawa Electric Co Ltd:The | Semiconductor electronic device |
| JP2009289826A (en) * | 2008-05-27 | 2009-12-10 | Toyota Central R&D Labs Inc | Semiconductor device having heterojunction and manufacturing method thereof |
| JP2009289827A (en) * | 2008-05-27 | 2009-12-10 | Toyota Central R&D Labs Inc | Semiconductor device having heterojunction and manufacturing method thereof |
| JP2012069662A (en) * | 2010-09-22 | 2012-04-05 | National Institute Of Advanced Industrial & Technology | Field effect transistor |
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2000
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7329908B2 (en) * | 2003-09-05 | 2008-02-12 | The Furukawa Electric Co., Ltd. | Nitride-based compound semiconductor electron device including a buffer layer structure |
| JP2005158889A (en) * | 2003-11-21 | 2005-06-16 | Sanken Electric Co Ltd | Plate-shaped substrate for forming semiconductor element, its manufacturing method, and semiconductor element using it |
| JP4525894B2 (en) * | 2003-11-21 | 2010-08-18 | サンケン電気株式会社 | Semiconductor device forming plate-like substrate, manufacturing method thereof, and semiconductor device using the same |
| WO2007122800A1 (en) * | 2006-03-29 | 2007-11-01 | Nec Corporation | Field effect transistor |
| US8198652B2 (en) | 2006-03-29 | 2012-06-12 | Nec Corporation | Field effect transistor with reduced gate leakage current |
| US8466495B2 (en) | 2006-03-29 | 2013-06-18 | Nec Corporation | Field effect transistor with reduced gate leakage current |
| JP5223670B2 (en) * | 2006-03-29 | 2013-06-26 | 日本電気株式会社 | Field effect transistor |
| JP2008135575A (en) * | 2006-11-28 | 2008-06-12 | Furukawa Electric Co Ltd:The | Semiconductor electronic device |
| JP2009289826A (en) * | 2008-05-27 | 2009-12-10 | Toyota Central R&D Labs Inc | Semiconductor device having heterojunction and manufacturing method thereof |
| JP2009289827A (en) * | 2008-05-27 | 2009-12-10 | Toyota Central R&D Labs Inc | Semiconductor device having heterojunction and manufacturing method thereof |
| JP2012069662A (en) * | 2010-09-22 | 2012-04-05 | National Institute Of Advanced Industrial & Technology | Field effect transistor |
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