JP2001077224A - Semiconductor element housing package and mounting structure therefor - Google Patents

Semiconductor element housing package and mounting structure therefor

Info

Publication number
JP2001077224A
JP2001077224A JP24534499A JP24534499A JP2001077224A JP 2001077224 A JP2001077224 A JP 2001077224A JP 24534499 A JP24534499 A JP 24534499A JP 24534499 A JP24534499 A JP 24534499A JP 2001077224 A JP2001077224 A JP 2001077224A
Authority
JP
Japan
Prior art keywords
package
semiconductor element
insulating substrate
thermal expansion
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24534499A
Other languages
Japanese (ja)
Inventor
Kazutaka Maeda
和孝 前田
Shoichi Nakagawa
彰一 仲川
Masaya Kokubu
正也 國分
Masahiko Azuma
昌彦 東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP24534499A priority Critical patent/JP2001077224A/en
Publication of JP2001077224A publication Critical patent/JP2001077224A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element housing package and a mounting structure therefor, which are capable of maintaining rigid and stable connection with an external circuit board over a long period of time and forming lands at a high density. SOLUTION: A semiconductor element housing package A includes a metallized wiring layer 2 for electrical connection with a semiconductor element 4 formed on the surface of a ceramic insulating substrate 1, and metallized lands 3. For mounting the package A on an external circuit board B, the coefficient of thermal expansion of the substrate 1 of the package A is set to 8-18 ppm/ deg.C or less, a difference between its coefficient of thermal expansion and that of the element 4 is set to 12 ppm/ deg.C or less, the Young's modulus is set to 50-150 GPa, and the difference between the coefficient of thermal expansion of the substrate 1 and that of an insulator 11 of the board B is set to 10 ppm/ deg.C or less. As a result, superior connection reliability can be obtained, with the lands 3 being arranged at an interval x of 0.8 mm or less and a layer of conductors 10 interposed between the lands 3 and lands 12 of the board B having a thickness Y of 0.3 mm or less.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体素子を収容
搭載した半導体素子収納用パッケージと、これを外部回
路基板に対して導体層を介して接続するのに適した実装
構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device housing package for housing a semiconductor device, and a mounting structure suitable for connecting the semiconductor device to an external circuit board via a conductor layer.

【０００２】[0002]

【従来技術】従来、配線基板は絶縁基板の表面あるいは
内部にメタライズ配線層が配設された構造からなる。ま
た、この配線基板の代表的な例として半導体素子、特に
ＬＳＩ（大規模集積回路）等の半導体集積回路素子を収
納するための半導体素子収納用パッケージは、一般にセ
ラミックスからなる絶縁基板の表面に半導体素子が搭載
されまた絶縁基板の表面および内部に形成されたメタラ
イズ配線層と半導体素子が接続される。また、絶縁基板
の下面には、絶縁基板表面のメタライズ配線層と接続さ
れ、また外部回路基板と電気的に接続される接続端子部
が設けられている。2. Description of the Related Art Conventionally, a wiring board has a structure in which a metallized wiring layer is provided on or in an insulating substrate. A typical example of the wiring board is a semiconductor element housing package for housing a semiconductor element, particularly a semiconductor integrated circuit element such as an LSI (Large Scale Integrated Circuit). The semiconductor element is connected to the metallized wiring layer on which the element is mounted and formed on the surface and inside of the insulating substrate. Further, on the lower surface of the insulating substrate, there are provided connection terminal portions connected to the metallized wiring layer on the surface of the insulating substrate and electrically connected to the external circuit board.

【０００３】そしてかかる半導体素子収納用パッケージ
は、絶縁基板裏面に設けられたランド部に接続端子が取
り付けられ、外部回路基板表面に形成されたランド部と
接続端子を半田等などによって接着して電気的に接続す
ることにより実装される。In such a package for housing a semiconductor element, connection terminals are attached to lands provided on the back surface of the insulating substrate, and the lands formed on the surface of the external circuit board are bonded to the connection terminals by soldering or the like. It is implemented by connecting to each other.

【０００４】最近に至り、半導体素子の集積度が高まる
につれて、パッケージの裏面に形成される端子数が増加
し、それに伴い小型化も要求されるために、端子の高密
度化が求められている。In recent years, as the degree of integration of semiconductor devices has increased, the number of terminals formed on the back surface of the package has increased. .

【０００５】このような要求に対して、従来から接続端
子として用いられてきた金属ピンに代えて、パッケージ
の裏面にメタライズランド部を形成し、このランド部と
外部回路基板とをロウ材などによって直接接続する、い
わゆるいわゆるボールグリッドアレイ（ＢＧＡ）型やラ
ンドグリッドアレイ（ＬＧＡ）型のパッケージが開発さ
れている。また、それと同時に、パッケージ小型化への
要求が高まっており、チップ面積がパッケージ面積の５
０％以上のチップサイズパッケージ（ＣＳＰ）への移行
が進んでいる。In response to such a demand, a metallized land portion is formed on the back surface of the package in place of metal pins conventionally used as connection terminals, and the land portion and the external circuit board are joined with a brazing material or the like. A so-called ball grid array (BGA) type or land grid array (LGA) type package for direct connection has been developed. At the same time, the demand for package miniaturization is increasing, and the chip area is 5% of the package area.
The shift to a chip size package (CSP) of 0% or more is progressing.

【０００６】ＢＧＡ型パッケージは、半田などのボール
状端子をパッケージの裏面のランド部に取着し、外部回
路基板の実装時にそのボール状端子を溶融させたり、そ
のボール状端子を低融点の半田によって外部回路基板側
のランド部に実装させるものである。[0006] In the BGA type package, a ball-shaped terminal such as solder is attached to a land on the back surface of the package, and the ball-shaped terminal is melted when an external circuit board is mounted. Is mounted on the land portion on the external circuit board side.

【０００７】これに対して、ＬＧＡ型パッケージは、ボ
ール状端子を取着することなく、ランド部に付着させた
導体層を介して外部回路基板側のランド部に実装させる
ものであり、コストを削減することが可能である。On the other hand, an LGA type package is mounted on a land portion on an external circuit board side via a conductor layer attached to the land portion without mounting a ball-shaped terminal. It is possible to reduce.

【０００８】また、絶縁基板と外部回路基板とを接続す
る半田等の導体層の厚みが小さくできることから、パッ
ケージ全体の低背化に適しているとされている。また、
ＢＧＡ型パッケージの実装時のボール形状がランド部形
状よりも大きいのに対して、ランドグリッドアレイ（Ｌ
ＧＡ) 型パッケージでは導体層形状がランド形状に整合
してほぼ同一の形状であるためにランド部間距離を狭く
できるという点で低背化、高密度化に対して有利であ
る。In addition, since the thickness of a conductor layer such as solder for connecting the insulating substrate and the external circuit board can be reduced, it is said that it is suitable for reducing the height of the entire package. Also,
While the ball shape at the time of mounting the BGA type package is larger than the land shape, the land grid array (L
The GA) type package is advantageous for reduction in height and density in that the distance between lands can be reduced because the shape of the conductor layer matches the land shape and is substantially the same shape.

【０００９】[0009]

【発明が解決しようとする課題】しかしながら、絶縁基
板がアルミナなどのセラミックスからなるＬＧＡ型パッ
ケージをガラス−エポキシ樹脂複合材料、ガラス−ポリ
イミド樹脂複合材料などの有機樹脂を含むプリント基板
などの外部回路基板への実装時、または半導体素子の駆
動停止に伴う発熱、冷却が繰り返されるに従って外部回
路基板とパッケージとの接続性が損なわれ、長期にわた
り安定な接続を維持できないという問題があった。However, an LGA type package in which the insulating substrate is made of ceramics such as alumina is used as an external circuit board such as a printed circuit board containing an organic resin such as a glass-epoxy resin composite material or a glass-polyimide resin composite material. When mounted on a semiconductor device, or as heat generation and cooling are repeated due to the stop of driving of the semiconductor element, the connectivity between the external circuit board and the package is impaired, and there is a problem that stable connection cannot be maintained for a long time.

【００１０】この信頼性の低下は、主としてパッケージ
における絶縁基板と外部回路基板の熱膨張係数差に起因
する熱応力が導体層による接続部に繰り返し作用するに
従い、導体層が疲労し、最終的にクラック等が発生する
ためと考えられる。This decrease in reliability is caused mainly by the fact that as the thermal stress mainly caused by the difference between the thermal expansion coefficients of the insulating substrate and the external circuit board in the package repeatedly acts on the connection portion by the conductor layer, the conductor layer becomes fatigued, and finally, It is considered that cracks and the like occur.

【００１１】この導体層に生じる熱応力はせん断応力で
あるため、導体層の高さに依存する。そのため、導体層
の厚さを０．４ｍｍ以上に高くし、またランド部間距離
を１ｍｍ以上にして熱応力を低減する工夫がなされてい
るのが現状である。The thermal stress generated in the conductor layer is a shear stress and depends on the height of the conductor layer. For this reason, it is presently devised to increase the thickness of the conductor layer to 0.4 mm or more and to reduce the thermal stress by setting the distance between lands to 1 mm or more.

【００１２】このような接続信頼性を高める上で、パッ
ケージの絶縁基板を高熱膨張化して外部回路基板の熱膨
張特性に近づけて、絶縁基板と外部回路基板との熱膨張
係数差を低減し、熱応力を低減する試みがなされてい
る。In order to enhance the connection reliability, the insulating substrate of the package is made to have a high thermal expansion so as to approximate the thermal expansion characteristics of the external circuit board, thereby reducing the difference in thermal expansion coefficient between the insulating substrate and the external circuit board. Attempts have been made to reduce thermal stress.

【００１３】しかしながら、絶縁基板の熱膨張係数が外
部回路基板の熱膨張係数に近づけると、パッケージにお
ける絶縁基板上に搭載された半導体素子と絶縁基板との
熱膨張係数差が大きくなってしまい、この熱膨張係数差
によってパッケージの外部回路基板との上記接続部に同
様に熱応力が発生してしまい、本質的に接続部に発生す
る熱応力を低減するには至らない。However, if the coefficient of thermal expansion of the insulating substrate approaches the coefficient of thermal expansion of the external circuit board, the difference in the coefficient of thermal expansion between the semiconductor element mounted on the insulating substrate in the package and the insulating substrate increases. Similarly, thermal stress is generated at the connection portion between the package and the external circuit board due to the difference in thermal expansion coefficient, and the thermal stress generated at the connection portion cannot be essentially reduced.

【００１４】特に、この半導体素子との熱膨張係数差に
起因する熱応力は、パッケージ上に搭載する半導体素子
とパッケージのサイズが近似する、即ち半導体素子の搭
載面積がパッケージの全面積の５０％以上となるような
チップサイズパッケージにおいては特に問題となってい
た。In particular, the thermal stress caused by the difference in the thermal expansion coefficient between the semiconductor element and the semiconductor element is such that the size of the semiconductor element mounted on the package and that of the package are similar, that is, the mounting area of the semiconductor element is 50% of the total area of the package. This has been a particular problem in such chip size packages.

【００１５】パッケージの絶縁基板と外部回路基板や半
導体素子との熱膨張係数差に起因する応力をいかにして
低減するかが大きな課題となるが、これまでＬＧＡ型パ
ッケージにおいては、その応力を低減するための具体的
な方法について検討されていないのが現状であった。A major issue is how to reduce the stress caused by the difference in thermal expansion coefficient between the insulating substrate of the package and the external circuit board or the semiconductor element. At this time, no specific method has been considered.

【００１６】したがって、本発明は、半導体素子を搭載
したパッケージを外部回路基板と長期にわたり強固で安
定な接続状態を維持でき、なお且つランド部の高密度化
が可能である半導体素子収納用パッケージとその実装構
造を提供することを目的とするものである。Accordingly, the present invention provides a semiconductor device housing package capable of maintaining a strong and stable connection state of a package mounting a semiconductor device with an external circuit board for a long period of time and capable of increasing the density of lands. The purpose is to provide the mounting structure.

【００１７】[0017]

【課題を解決するための手段】本発明者らは、上記の目
的に対して種々検討を重ねた結果、半導体素子収納用パ
ッケージにおける絶縁基板の熱膨張係数を半導体素子と
の熱膨張係数差および外部回路基板との熱膨張係数差が
特定以下となるように定めると同時にヤング率を特定範
囲に調整することにより、パッケージの裏面のメタライ
ズランド部間を小さくすることができ、また外部回路基
板との接続部の導体層厚さを小さくしても長期にわたり
優れた接続信頼性が達成できることを見いだしたもので
ある。As a result of various studies on the above object, the present inventors have found that the thermal expansion coefficient of an insulating substrate in a package for housing a semiconductor element is determined by the difference between the thermal expansion coefficient of the insulating substrate and the semiconductor element. By adjusting the thermal expansion coefficient difference with the external circuit board to be less than a specific value and adjusting the Young's modulus to a specific range, the distance between the metallized lands on the back surface of the package can be reduced. It has been found that excellent connection reliability can be achieved over a long period of time even if the thickness of the conductor layer at the connection portion is reduced.

【００１８】即ち、本発明の半導体素子収納用パッケー
ジは、セラミック絶縁基板と、該絶縁基板の一表面に被
着形成され、該絶縁基板表面に搭載される半導体素子と
電気的に接続されるメタライズ配線層と、前記絶縁基板
の他表面に被着形成され、且つ外部回路基板と導体を介
して接続される複数のメタライズランド部とを具備する
半導体素子収納用パッケージであって、前記絶縁基板の
−４０〜１２５℃における熱膨張係数が８〜１８ｐｐｍ
／℃、前記半導体素子との熱膨張係数差が１２ｐｐｍ／
℃以下、ヤング率が５０〜１５０ＧＰａであり、且つ前
記メタライズランド部の隣接するランド間の中心間距離
が０．８ｍｍ以下であることを特徴とするものである。That is, the package for accommodating a semiconductor element according to the present invention is formed on a ceramic insulating substrate, and is formed on one surface of the insulating substrate so as to be electrically connected to the semiconductor element mounted on the surface of the insulating substrate. A semiconductor element housing package comprising: a wiring layer; and a plurality of metallized lands that are formed on the other surface of the insulating substrate and are connected to an external circuit board via a conductor. The thermal expansion coefficient at -40 to 125 ° C is 8 to 18 ppm
/ ° C, the difference in thermal expansion coefficient from the semiconductor element is 12 ppm /
C. or lower, the Young's modulus is 50 to 150 GPa, and the center-to-center distance between adjacent lands of the metallized land portion is 0.8 mm or less.

【００１９】また、本発明の半導体素子収納用パッケー
ジの実装構造は、セラミック絶縁基板と、該絶縁基板の
一表面に被着形成され、該絶縁基板表面に搭載される半
導体素子と電気的に接続されるメタライズ配線層と、前
記絶縁基板の他表面に被着形成された複数のメタライズ
ランド部とを具備する半導体素子収納用パッケージを、
−４０〜１２５℃における熱膨張係数が１０ｐｐｍ／℃
以上の有機樹脂を含む絶縁体の表面にランド部が被着形
成された外部回路基板上に載置し、前記パッケージにお
ける前記ランド部と前記外部回路基板の前記ランド部と
を導体層によって電気的に接続固定してなるパッケージ
の実装構造であって、前記パッケージにおける絶縁基板
の−４０〜１２５℃における熱膨張係数が８〜１８ｐｐ
ｍ／℃、前記半導体素子との熱膨張係数差が１２ｐｐｍ
／℃以下、ヤング率が５０〜１５０ＧＰａ、前記前記メ
タライズランド部の隣接するランド間の中心間距離が
０．８ｍｍ以下であり、且つ前記パッケージの絶縁基板
と前記外部回路基板の絶縁体との熱膨張係数差が１０ｐ
ｐｍ／℃以下であり、前記パッケージ側のランド部と外
部回路基板側のランド部との間に介在する前記導体層の
厚みが０．３ｍｍ以下であることを特徴とするものであ
る。Further, the mounting structure of the package for accommodating a semiconductor element according to the present invention is a ceramic insulating substrate, and is formed on one surface of the insulating substrate so as to be electrically connected to the semiconductor element mounted on the surface of the insulating substrate. A metallized wiring layer, and a plurality of metallized land portions adhered and formed on the other surface of the insulating substrate.
The thermal expansion coefficient at -40 to 125 ° C. is 10 ppm / ° C.
It is placed on an external circuit board having a land adhered to the surface of the insulator containing the organic resin, and the land in the package and the land of the external circuit board are electrically connected by a conductor layer. Wherein the thermal expansion coefficient of the insulating substrate in the package at -40 to 125 ° C. is 8 to 18 pp.
m / ° C., the difference in thermal expansion coefficient from the semiconductor element is 12 ppm
/ ° C or less, the Young's modulus is 50 to 150 GPa, the center-to-center distance between adjacent lands of the metallized land portion is 0.8 mm or less, and the heat between the insulating substrate of the package and the insulator of the external circuit substrate. Expansion coefficient difference is 10p
pm / ° C. or less, and the thickness of the conductor layer interposed between the land on the package side and the land on the external circuit board is 0.3 mm or less.

【００２０】なお、上記パッケージおよび上記実装構造
においては、前記半導体素子の実装面積がパッケージ面
積の５０％以上である場合において特にその効果が発揮
される。また、パッケージにおける前記絶縁基板として
は、ガラスセラミックス焼結体からなることが望まし
い。In the package and the mounting structure, the effect is particularly exhibited when the mounting area of the semiconductor element is 50% or more of the package area. Further, it is desirable that the insulating substrate in the package is made of a glass ceramic sintered body.

【００２１】[0021]

【発明の実施の形態】以下、本発明を一実施例を示す添
付図面に基づき詳細に説明する。図１は本発明の一例を
示す概略断面図であり、セラミック絶縁基板の表面ある
いは内部にメタライズ配線層が配設された、いわゆる配
線基板を基礎的構造とするもので、本発明における半導
体素子収納用パッケージと、その実装構造の一例を示す
ものであり、Ａはその典型例としてＬＧＡ型の半導体素
子収納用パッケージ、Ｂは外部回路基板である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the accompanying drawings showing an embodiment. FIG. 1 is a schematic cross-sectional view showing an example of the present invention, which has a basic structure of a so-called wiring board in which a metallized wiring layer is disposed on the surface or inside of a ceramic insulating substrate. FIG. 1 shows an example of a package for use and a mounting structure thereof. A is a typical example of an LGA type semiconductor element storage package, and B is an external circuit board.

【００２２】半導体素子収納用パッケージＡはセラミッ
ク絶縁基板１とメタライズ配線層２とランド部３及びパ
ッケージに搭載される半導体素子４より構成されてい
る。半導体素子４をセラミック絶縁基板１上に載置する
方法としては大きく３つの構造がある。The package A for housing a semiconductor element is composed of a ceramic insulating substrate 1, a metallized wiring layer 2, a land 3 and a semiconductor element 4 mounted on the package. There are three main methods for mounting the semiconductor element 4 on the ceramic insulating substrate 1.

【００２３】図１は半導体素子４とセラミック絶縁基板
１に配設されたメタライズ配線層２とを微小な半田など
の導体層５を介して接続され、樹脂からなるアンダーフ
ィル６によって封止する、いわゆるフリップチップ型の
接合である。FIG. 1 shows that a semiconductor element 4 and a metallized wiring layer 2 provided on a ceramic insulating substrate 1 are connected via a conductor layer 5 such as a fine solder and are sealed with an underfill 6 made of resin. This is a so-called flip-chip type bonding.

【００２４】図２及び図３は半導体素子４とセラミック
絶縁基板１に配設されたメタライズ配線層２とをＡｌ、
Ａｕなどのワイヤ７で接続するワイヤボンディング型の
接合であり、この場合には、図２のように樹脂からなる
ポッティング材８で気密封止する場合と、図３のように
蓋体９で気密封止する場合がある。2 and 3 show that the semiconductor element 4 and the metallized wiring layer 2 provided on the ceramic insulating substrate 1 are made of Al,
This is a wire bonding type connection in which wires 7 of Au or the like are used. In this case, airtight sealing is performed with a potting material 8 made of a resin as shown in FIG. It may be tightly sealed.

【００２５】上記絶縁基板１の下面にはメタライズラン
ド部３が形成され、絶縁基板１の表面および内部に配設
されたメタライズ配線層２と電気的に接続されている。
この図１の半導体素子収納用パッケージにおいては、メ
タライズランド部３には例えば、図２に示すように、絶
縁基板１の下面に形成された多数のランド部３に半田
（錫−鉛合金）などの導体層１０により取着された構造
からなる。A metallized land portion 3 is formed on the lower surface of the insulating substrate 1 and is electrically connected to the metallized wiring layer 2 disposed on the surface and inside of the insulating substrate 1.
In the package for accommodating the semiconductor element shown in FIG. 1, for example, as shown in FIG. 2, solder (tin-lead alloy) or the like is attached to a large number of lands 3 formed on the lower surface of the insulating substrate 1 as shown in FIG. Having a structure attached by the conductor layer 10.

【００２６】一方、外部回路基板Ｂはいわゆるプリント
基板からなり、ガラス−エポキシ樹脂、ガラス−ポリイ
ミド樹脂複合材料などの有機樹脂を含む材料からなる絶
縁体１１の表面に、Ｃｕ、Ａｕ、Ａｌ、Ｎｉ、Ｓｎ−Ｐ
ｂなどの金属からなるランド部１２が被着形成されたも
のであり、以下、単にプリント基板と称する場合もあ
る。On the other hand, the external circuit board B is formed of a so-called printed board, and Cu, Au, Al, Ni is formed on the surface of an insulator 11 made of a material containing an organic resin such as a glass-epoxy resin or a glass-polyimide resin composite material. , Sn-P
A land portion 12 made of a metal such as b is formed by attachment, and may hereinafter be simply referred to as a printed circuit board.

【００２７】上記半導体素子収納用パッケージＡを上記
プリント基板Ｂに実装するには、パッケージＡの絶縁基
板１下面のメタライズランド部３の表面に半田などの導
体層１０塗布した後、プリント基板Ｂのランド部１２上
に載置当接させ、しかる後、半田などの導体層１０によ
ってプリント基板Ｂ上に実装される。In order to mount the semiconductor element housing package A on the printed board B, a conductor layer 10 such as solder is applied to the surface of the metallized land 3 on the lower surface of the insulating board 1 of the package A, and then the printed board B is mounted. It is placed and contacted on the land 12 and then mounted on the printed circuit board B by the conductor layer 10 such as solder.

【００２８】このような半導体素子収納用パッケージＡ
では、ランド部３とランド部１２との接続を担う導体層
１０の絶対量が少ないため、ランド部３が円形である場
合には、導体層１０の形状は円柱型となる。従って、隣
接する導体層１０は接触しないため、メタライズランド
部３の隣接するランド部の中心間距離Ｘを狭くして高密
度化することができる。Such a package A for housing a semiconductor element
In this case, since the absolute amount of the conductor layer 10 that connects the land portion 3 and the land portion 12 is small, when the land portion 3 is circular, the shape of the conductor layer 10 is cylindrical. Therefore, since the adjacent conductor layers 10 do not come into contact with each other, the center-to-center distance X between the adjacent land portions of the metallized land portion 3 can be reduced to increase the density.

【００２９】しかし、その反面、この導体層１０に対し
て大きな熱応力が発生し、パッケージのランド部と外部
回路基板のランド部とを長期にわたり安定に電気的接続
が出来ないという問題点がある。However, on the other hand, there is a problem that a large thermal stress is generated in the conductor layer 10 and the land portion of the package and the land portion of the external circuit board cannot be stably electrically connected for a long time. .

【００３０】実装後の配線基板に搭載される半導体素子
の繰り返し作動時において、パッケージＡ側のランド部
３と外部回路基板Ｂ側のランド部１２を電気的に接続し
ている導体層１０には、パッケージＡと外部回路基板Ｂ
との熱膨張係数差により熱応力が生じている。When the semiconductor element mounted on the wiring board after mounting is repeatedly operated, the conductor layer 10 electrically connecting the land portion 3 on the package A side and the land portion 12 on the external circuit board B is provided. , Package A and external circuit board B
A thermal stress is generated due to a difference in thermal expansion coefficient from the above.

【００３１】パッケージＡと外部回路基板Ｂとの熱膨張
係数差はパッケージＡの中心からの距離に伴い大きくな
るため、アレイ上に並んだ多数の導体層１０のうち、パ
ッケージＡの中心から最も遠い導体層１０ａにおいて最
も高い熱応力が生じやすい。半導体素子４の作動・停止
により熱応力が繰り返し印加されると、パッケージＡの
中心から最も遠い導体層１０ａは疲労した後に破断し、
電気的な接続を保つことができなくなる。Since the difference between the thermal expansion coefficients of the package A and the external circuit board B increases with the distance from the center of the package A, the farthest from the center of the package A among the many conductor layers 10 arranged on the array. The highest thermal stress is likely to occur in the conductor layer 10a. When the thermal stress is repeatedly applied by the operation / stop of the semiconductor element 4, the conductor layer 10a farthest from the center of the package A is broken after being fatigued,
The electrical connection cannot be maintained.

【００３２】これに対してパッケージＡにおける絶縁基
板１のヤング率が１５０ＧＰａ以下であると、導体層１
０ａに生じる熱応力をパッケージＡと外部回路基板Ｂと
が同じ方向に歪む（反る）ことで低減することができ
る。しかし、パッケージＡのヤング率が１５０ＧＰａを
超えて高い場合には、パッケージＡと外部回路基板Ｂと
が同じ方向に歪む（反る）ことができないため、導体層
１０には高い熱応力が生じてしまう。したがって、パッ
ケージＡの絶縁基板１のヤング率が小さいほど熱応力を
低減できる。しかし、絶縁基板１のヤング率が５０ＧＰ
ａよりも小さいと、ポッティング材８や蓋体９の影響を
受けやすくなり逆に熱応力が高くなる。On the other hand, if the Young's modulus of the insulating substrate 1 in the package A is 150 GPa or less,
The thermal stress generated in Oa can be reduced by distorting (warping) the package A and the external circuit board B in the same direction. However, when the Young's modulus of the package A is higher than 150 GPa, the package A and the external circuit board B cannot be distorted (warped) in the same direction. I will. Therefore, as the Young's modulus of the insulating substrate 1 of the package A is smaller, the thermal stress can be reduced. However, the Young's modulus of the insulating substrate 1 is 50 GP.
If it is smaller than a, it tends to be affected by the potting material 8 and the lid 9, and the thermal stress increases.

【００３３】また、熱応力を低減する方法として、パッ
ケージＡの絶縁基板１と外部回路基板Ｂの絶縁体１１と
の熱膨張係数差を小さくする方法もある。具体的には、
一般に外部回路基板の熱膨張係数が１０ｐｐｍ／℃以上
であることから、パッケージＡの絶縁基板の熱膨張係数
を８ｐｐｍ／℃以上とし、絶縁基板１と絶縁体１１との
熱膨張係数差を１０ｐｐｍ／℃以下とすることにより、
導体層１０の厚みＹが小さくても熱応力は小さくでき
る。As a method of reducing the thermal stress, there is a method of reducing the difference in thermal expansion coefficient between the insulating substrate 1 of the package A and the insulator 11 of the external circuit board B. In particular,
Generally, since the thermal expansion coefficient of the external circuit board is 10 ppm / ° C. or more, the thermal expansion coefficient of the insulating substrate of the package A is set to 8 ppm / ° C. or more, and the thermal expansion coefficient difference between the insulating substrate 1 and the insulator 11 is 10 ppm / ° C. ℃ or less,
Even if the thickness Y of the conductor layer 10 is small, the thermal stress can be reduced.

【００３４】しかしながら、パッケージＡには、熱膨張
係数が約２〜３ｐｐｍ／℃の半導体素子４が搭載されて
いるために、パッケージＡの絶縁基板１の熱膨張係数が
１８ｐｐｍ／℃を超える、あるいは半導体素子４との熱
膨張係数差が１２ｐｐｍ／℃よりも大きくなると、半導
体素子４と絶縁基板１との熱膨張係数差に起因する熱応
力が導体層１０に発生してしまい、その結果接続信頼性
が低下してしまう。However, since the semiconductor element 4 having a thermal expansion coefficient of about 2 to 3 ppm / ° C. is mounted on the package A, the thermal expansion coefficient of the insulating substrate 1 of the package A exceeds 18 ppm / ° C., or If the difference in thermal expansion coefficient between the semiconductor element 4 and the semiconductor element 4 is greater than 12 ppm / ° C., thermal stress due to the difference in thermal expansion coefficient between the semiconductor element 4 and the insulating substrate 1 is generated in the conductor layer 10, and as a result, connection reliability is reduced. Performance is reduced.

【００３５】かかる観点から、パッケージＡの絶縁基板
１としては、−４０〜１２５℃における熱膨張係数が８
〜１８ｐｐｍ／℃、特に１０〜１５ｐｐｍ／℃、半導体
素子４との熱膨張係数差が１２ｐｐｍ／℃以下、特に１
０ｐｐｍ／℃以下、ヤング率が５０〜１５０ＧＰａ、特
に６０〜１１０ＧＰａであることが重要となるのであ
る。その結果、本発明の半導体素子収納用パッケージＡ
においては、前記メタライズランド部の間隔を０．８ｍ
ｍ以下、特に０．５ｍｍ以下にまで高密度化することが
できる。From this viewpoint, the insulating substrate 1 of the package A has a coefficient of thermal expansion at -40 to 125 ° C. of 8
-18 ppm / ° C, particularly 10-15 ppm / ° C, and a difference in thermal expansion coefficient from the semiconductor element 4 of 12 ppm / ° C or less, particularly 1
It is important that it is 0 ppm / ° C. or less and the Young's modulus is 50 to 150 GPa, particularly 60 to 110 GPa. As a result, the semiconductor device housing package A of the present invention
In the above, the distance between the metallized land portions is 0.8 m
m, especially 0.5 mm or less.

【００３６】また、半導体素子収納用パッケージの実装
構造においては、パッケージＡの絶縁基板１としては、
−４０〜１２５℃における熱膨張係数が８〜１８ｐｐｍ
／℃、特に１０〜１５ｐｐｍ／℃、半導体素子４との熱
膨張係数差が１２ｐｐｍ／℃以下、特に１０ｐｐｍ／℃
以下、ヤング率が５０〜１５０ＧＰａ、特に６０〜１１
０ＧＰａとすることに加え、且つ前記パッケージの絶縁
基板と前記外部回路基板の絶縁体との熱膨張係数差が１
０ｐｐｍ／℃以下、特に５ｐｐｍ／℃以下とすることに
より、前記メタライズランド部の間隔が０．８ｍｍ以
下、特に０．５ｍｍ以下、前記パッケージ側のランド部
と外部回路基板側のランド部との間に介在する導体層の
厚みを０．３ｍｍ以下、特に０．２ｍｍ以下まで薄くし
ても優れた接続信頼性が得られる。In the mounting structure of the package for housing a semiconductor element, the insulating substrate 1 of the package A
The thermal expansion coefficient at -40 to 125 ° C is 8 to 18 ppm
/ ° C, particularly 10 to 15 ppm / ° C, and a difference in thermal expansion coefficient from the semiconductor element 4 of 12 ppm / ° C or less, particularly 10 ppm / ° C.
Hereinafter, the Young's modulus is 50 to 150 GPa, particularly 60 to 11
0 GPa, and the thermal expansion coefficient difference between the insulating substrate of the package and the insulator of the external circuit board is 1
By setting the concentration to 0 ppm / ° C. or less, particularly 5 ppm / ° C. or less, the distance between the metallized land portions is 0.8 mm or less, especially 0.5 mm or less, and the distance between the package side land portion and the external circuit board side land portion is reduced. Excellent connection reliability can be obtained even if the thickness of the conductor layer interposed therebetween is reduced to 0.3 mm or less, particularly 0.2 mm or less.

【００３７】さらには、パッケージの絶縁基板と半導体
素子との熱膨張差よりもパッケージの絶縁基板と外部回
路基板の絶縁体との熱膨張差が小さい方が望ましい。Further, it is desirable that the difference in thermal expansion between the insulating substrate of the package and the insulator of the external circuit board be smaller than the difference in thermal expansion between the insulating substrate of the package and the semiconductor element.

【００３８】また、前記半導体素子の実装面積がパッケ
ージ面積に対して大きくなるに従い、半導体素子４によ
る影響が大きくなるが、本発明では、半導体素子の実装
面積がパッケージ面積の５０％以上である、いわゆるチ
ップサイズパッケージ（ＣＳＰ）である場合においても
優れた接続信頼性を発揮することができる。Further, as the mounting area of the semiconductor element increases with respect to the package area, the influence of the semiconductor element 4 increases. According to the present invention, the mounting area of the semiconductor element is 50% or more of the package area. Even in the case of a so-called chip size package (CSP), excellent connection reliability can be exhibited.

【００３９】このようなパッケージＡにおける絶縁基板
材料としては、例えばリチウム珪酸ガラス、ＰｂＯ系ガ
ラス、ＺｎＯ系ガラス、ＢａＯ系ガラス等のガラス成分
に対して、エンステタイト、フォルステライト、ＳｉＯ
2 系フィラー、ＭｇＯ、ＺｒＯ2 、ペタライト等の各種
セラミックスフィラーを混合し、ついで焼成して、上記
特性を満足する焼結体によって作製することができる。As an insulating substrate material in such a package A, for example, enstatite, forsterite, SiO2 is used for glass components such as lithium silicate glass, PbO-based glass, ZnO-based glass, and BaO-based glass.
Various ceramic fillers such as a 2 type filler, MgO, ZrO 2 , petalite and the like can be mixed and then fired to produce a sintered body satisfying the above characteristics.

【００４０】例えば、上記ガラス２０〜９０体積％、上
記フィラー８０〜１０体積％の混合物に、適時有機バイ
ンダーを添加してスラリーを調製し、そのスラリーをシ
ート状に成形した後、そのシート状成形体の表面に、Ｃ
ｕ、Ａｕ、Ａｇなどの低抵抗金属を含む導体ペーストを
印刷塗布する。また、所望によりシート状成形体の所定
箇所にマイクロドリルやレーザー等によりスルーホール
を形成して、ホール内に前記導体ペーストを充填する。
そして、そのシート状成形体を複数積層圧着して積層体
を作製した後、これを窒素雰囲気、あるいは水蒸気を含
む窒素雰囲気中で脱脂後、８００〜１０００℃の温度で
焼成することにより作製する。For example, a slurry is prepared by appropriately adding an organic binder to a mixture of 20 to 90% by volume of the glass and 80 to 10% by volume of the filler, and the slurry is formed into a sheet. C on the body surface
A conductive paste containing a low-resistance metal such as u, Au, or Ag is applied by printing. Further, if necessary, a through hole is formed at a predetermined position of the sheet-like molded body by a micro drill, a laser, or the like, and the hole is filled with the conductive paste.
Then, after laminating and pressing a plurality of the sheet-shaped molded bodies to produce a laminated body, the laminated body is degreased in a nitrogen atmosphere or a nitrogen atmosphere containing water vapor, and then fired at a temperature of 800 to 1000 ° C.

【００４１】[0041]

【実施例】表１に示す種々の特性を有するガラスセラミ
ックスについて、５×４×４０ｍｍの焼結体を作製した
後、各焼結体についてヤング率、および−４０〜１２５
℃における熱膨張係数を測定し表１に示した。EXAMPLES For glass ceramics having various characteristics shown in Table 1, sintered bodies of 5 × 4 × 40 mm were prepared, and the Young's modulus and -40 to 125 of each sintered body were obtained.
The thermal expansion coefficient at ℃ was measured and shown in Table 1.

【００４２】[0042]

【表１】 [Table 1]

【００４３】また、表１に示す各種セラミックスを絶縁
基板として用いて、その表面に半導体素子と接続される
メタライズ配線層、内部配線層及びビアホール導体、底
面に導体層を取りつけるための２５６個のランド部を銅
ペーストの印刷、あるいは充填により周知の方法に従い
９００℃の温度で同時焼成して、縦１５×横１５×厚さ
０．６ｍｍのパッケージ基板を作製した。Also, using various ceramics shown in Table 1 as an insulating substrate, a metallized wiring layer, an internal wiring layer and a via hole conductor connected to a semiconductor element on its surface, and 256 lands for attaching a conductor layer to the bottom surface. The part was simultaneously baked at a temperature of 900 ° C. according to a well-known method by printing or filling a copper paste to prepare a package substrate having a length of 15 × 15 × 0.6 mm.

【００４４】そして、パッケージ基板の上面に熱膨張係
数が３ｐｐｍ／℃の１１×１１×３ｍｍの半導体素子を
フリップチップ実装し、その一次実装部にビスフェノー
ル型エポキシ樹脂５０体積％と平均粒径５μｍの球状ア
ルミナ粉末５０体積％からなるアンダーフィル材を充填
して１５０℃で２時間保持して硬化させ、チップサイズ
パッケージを作製した。Then, a semiconductor element of 11 × 11 × 3 mm having a thermal expansion coefficient of 3 ppm / ° C. is flip-chip mounted on the upper surface of the package substrate, and 50 vol% of a bisphenol type epoxy resin and an average particle diameter of 5 μm are mounted on the primary mounting portion. An underfill material composed of 50% by volume of spherical alumina powder was filled and kept at 150 ° C. for 2 hours for curing to produce a chip size package.

【００４５】そして上記パッケージ基板の裏面のランド
部表面に半田（Ｓｎ６３重量％−Ｐｂ３７重量％）ペー
ストをスクリーン印刷により塗布し、加熱溶融して半田
からなる１００μｍの厚さの導体層を形成させた。な
お、ランド部は表２、３に示す間隔で下面全体に形成し
た。Then, a solder (Sn 63% by weight-Pb 37% by weight) paste was applied to the surface of the land on the back surface of the package substrate by screen printing, and was heated and melted to form a 100 μm thick conductor layer made of solder. . The lands were formed on the entire lower surface at intervals shown in Tables 2 and 3.

【００４６】また、比較のために絶縁材料として表１に
示すようなアルミナセラミックスやソーダ石灰ガラスを
用いて導体材料としてタングステンまたは銅を用いて１
５５０℃，１０００℃で同時焼成して、上記と全く同じ
大きさのパッケージ基板を作製し、同様な方法で半導体
素子を実装した。For comparison, alumina ceramic or soda-lime glass as shown in Table 1 was used as an insulating material, and tungsten or copper was used as a conductor material.
Simultaneous firing was performed at 550 ° C. and 1000 ° C. to produce a package substrate having the same size as above, and a semiconductor element was mounted in the same manner.

【００４７】一方、プリント基板として、ガラス−エポ
キシ基板からなる−４０〜１２５℃における熱膨張係数
が１５ｐｐｍ／℃、または２４ｐｐｍ／℃の絶縁体
の表面に銅箔からなるランド部が形成されたプリント基
板を準備した。On the other hand, a printed circuit board having a land portion made of copper foil formed on the surface of an insulator made of a glass-epoxy substrate and having a thermal expansion coefficient of 15 ppm / ° C. or 24 ppm / ° C. at −40 to 125 ° C. A substrate was prepared.

【００４８】そして、上記プリント基板のランド部に半
田（Ｓｎ６３重量％−Ｐｂ３７重量％）ペーストをスク
リーン印刷により塗布した後、上記のパッケージのラン
ド部と上記プリント基板のランド部とを位置合わせし、
２３０℃で加熱溶融させてパッケージをプリント基板表
面に実装した。試料Ｎo.１〜５４はのプリント基板、
試料Ｎo.５５〜６０はのプリント基板に実装した。Then, after solder (Sn 63% by weight-Pb 37% by weight) paste is applied to the land of the printed board by screen printing, the land of the package is aligned with the land of the printed board.
The package was mounted on the surface of the printed circuit board by heating and melting at 230 ° C. Sample Nos. 1 to 54 are printed circuit boards,
Sample Nos. 55 to 60 were mounted on a printed circuit board.

【００４９】なお、半田による導体層の厚みが０．１ｍ
ｍのパッケージの実装構造を作製する際は、パッケージ
側には半田ペーストの印刷は行わず、プリント基板側の
み半田ペーストの印刷を行った。The thickness of the conductor layer made of solder is 0.1 m.
When fabricating the package mounting structure of m, solder paste was not printed on the package side, but solder paste was printed only on the printed circuit board side.

【００５０】次に、上記のようにしてパッケージ基板を
プリント基板表面に実装したものを大気の雰囲気にて−
４０〜１２５℃の各温度に制御した恒温槽に試験サンプ
ルを１５分／１５分の保持を１サイクルとして最高２５
００サイクル繰り返した。Next, the package substrate mounted on the printed circuit board surface as described above was placed in an atmosphere of air.
The test sample is held in a thermostat controlled at each temperature of 40 to 125 ° C. for 15 minutes / 15 minutes as one cycle, and a maximum of 25
Repeated for 00 cycles.

【００５１】そして、１００サイクル毎にプリント基板
の配線導体とパッケージ用基板とのランド間の電気抵抗
を測定し、電気抵抗に変化が現れるまでのサイクル数を
表２、表３に示した。Then, the electric resistance between the lands between the wiring conductor of the printed circuit board and the package substrate was measured every 100 cycles, and Tables 2 and 3 show the number of cycles until the electric resistance changed.

【００５２】[0052]

【表２】 [Table 2]

【００５３】[0053]

【表３】 [Table 3]

【００５４】表２、表３より明らかなように、本発明に
基づき、パッケージの絶縁基板の熱膨張係数が８〜１８
ｐｐｍ／℃、半導体素子との熱膨張係数差Δα1 が１２
ｐｐｍ／℃以下、ヤング率が５０〜１５０ＧＰａであ
り、またパッケージの絶縁基板と前記外部回路基板の絶
縁体との熱膨張係数差Δα2 が１０ｐｐｍ／℃以下の半
導体素子収納用パッケージでは、前記メタライズランド
部の間隔が０．８ｍｍ以下であっても導体層同士が接触
することがなく、また前記ランド部間に介在する導体層
の厚みが０．３ｍｍ以下であっても、いずれも１０００
サイクルまで抵抗変化は全く認められず、極めて安定で
良好な電気的接続状態を維持できた。As is clear from Tables 2 and 3, according to the present invention, the thermal expansion coefficient of the insulating substrate of the package is from 8 to 18.
ppm / ° C, thermal expansion coefficient difference Δα 1 with semiconductor element is 12
ppm / ° C. or less, a Young's modulus of 50 to 150 GPa, and a semiconductor element housing package having a thermal expansion coefficient difference Δα 2 of 10 ppm / ° C. or less between the insulating substrate of the package and the insulator of the external circuit board. Even if the interval between the land portions is 0.8 mm or less, the conductor layers do not contact each other, and even if the thickness of the conductor layer interposed between the land portions is 0.3 mm or less, any
No change in resistance was observed at all until the cycle, and an extremely stable and good electrical connection state could be maintained.

【００５５】しかし、上記の特性から逸脱するパッケー
ジでは、１０００サイクル未満の早い段階から抵抗変化
が検出され、実装後の信頼性に欠けることがわかった。However, in a package deviating from the above characteristics, a change in resistance was detected at an early stage of less than 1000 cycles, and it was found that reliability after mounting was lacking.

【００５６】[0056]

【発明の効果】以上詳述したように、本発明の半導体素
子収納用パッケージは、ランド部を高密度に配置するこ
とが可能であるとともに、熱膨張係数の大きいプリント
基板などの外部回路基板に実装した場合にも、パッケー
ジと外部回路基板、あるいはパッケージと半導体素子と
の熱膨張係数の差に起因して発生する熱応力をパッケー
ジが歪む（反る）ことで熱応力を緩和できることから、
導体層の厚みが薄くても長期間にわたり安定に、かつ強
固に電気的接続させることが可能となる。As described in detail above, the semiconductor device housing package of the present invention can arrange lands at high density and can be mounted on an external circuit board such as a printed board having a large thermal expansion coefficient. Even when the package is mounted, the thermal stress generated due to the difference in the coefficient of thermal expansion between the package and the external circuit board or between the package and the semiconductor element can be relieved because the package is distorted (warped).
Even if the thickness of the conductor layer is thin, it is possible to make a stable and strong electrical connection for a long time.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明における半導体素子収納用パッケージの
実装構造を説明するための概略断面図である。FIG. 1 is a schematic cross-sectional view for explaining a mounting structure of a package for housing a semiconductor element according to the present invention.

【図２】本発明における半導体素子収納用パッケージの
他の実装構造を説明するための概略断面図である。FIG. 2 is a schematic cross-sectional view for explaining another mounting structure of the package for housing a semiconductor element according to the present invention.

【図３】本発明における半導体素子収納用パッケージの
さらに他の実装構造を説明するための概略断面図であ
る。FIG. 3 is a schematic cross-sectional view for explaining still another mounting structure of the semiconductor element housing package according to the present invention.

【図４】本発明の半導体素子収納用パッケージにおける
接続端子の要部拡大断面図である。FIG. 4 is an enlarged cross-sectional view of a main part of a connection terminal in the package for housing a semiconductor element of the present invention.

【符号の説明】[Explanation of symbols]

１ セラミック絶縁基板 ２ メタライズ配線層 ３ メタライズランド部 ４ 半導体素子 ５ 導体層 ６ アンダーフィル ７ ボンディングワイヤ ８ 封止樹脂（ポッティング材） ９ 蓋体 １０ 導体層 １１ 絶縁体 １２ ランド部 DESCRIPTION OF SYMBOLS 1 Ceramic insulating substrate 2 Metallized wiring layer 3 Metallized land part 4 Semiconductor element 5 Conductor layer 6 Underfill 7 Bonding wire 8 Sealing resin (potting material) 9 Lid 10 Conductor layer 11 Insulator 12 Land part

───────────────────────────────────────────────────── フロントページの続き (72)発明者 東 昌彦 鹿児島県国分市山下町１番４号 京セラ株 式会社総合研究所内 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masahiko Higashi 1-4, Yamashita-cho, Kokubu-shi, Kagoshima Inside the Kyocera Research Institute

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】セラミック絶縁基板と、該絶縁基板の表面
に被着形成され、該絶縁基板表面に搭載される半導体素
子と電気的に接続されるメタライズ配線層と、前記絶縁
基板の他表面に被着形成され、且つ外部回路基板と導体
を介して接続される複数のメタライズランド部とを具備
する半導体素子収納用パッケージであって、前記絶縁基
板の−４０〜１２５℃における熱膨張係数が８〜１８ｐ
ｐｍ／℃、前記半導体素子との熱膨張係数差が１２ｐｐ
ｍ／℃以下、ヤング率が５０〜１５０ＧＰａであり、且
つ前記メタライズランド部の隣接するランド間の中心間
距離が０．８ｍｍ以下であることを特徴とする半導体素
子収納用パッケージ。A ceramic insulating substrate, a metallized wiring layer adhered to the surface of the insulating substrate and electrically connected to a semiconductor element mounted on the surface of the insulating substrate; What is claimed is: 1. A semiconductor device housing package comprising: a plurality of metallized lands that are formed and connected to an external circuit board via a conductor, wherein the thermal expansion coefficient of the insulating substrate at -40 to 125 [deg.] C. is 8; ~ 18p
pm / ° C., and the thermal expansion coefficient difference with the semiconductor element is 12 pp.
m / ° C. or less, a Young's modulus of 50 to 150 GPa, and a center-to-center distance between adjacent lands of the metallized land is 0.8 mm or less. 【請求項２】前記絶縁基板が、ガラスセラミックスから
なることを特徴とする請求項１記載の半導体素子収納用
パッケージ。2. The package according to claim 1, wherein said insulating substrate is made of glass ceramic. 【請求項３】前記半導体素子の実装面積がパッケージ面
積の５０％以上である請求項１記載の半導体素子収納用
パッケージ。3. The package according to claim 1, wherein a mounting area of the semiconductor element is 50% or more of a package area. 【請求項４】セラミック絶縁基板と、該絶縁基板の表面
に被着形成され、該絶縁基板表面に搭載される半導体素
子と電気的に接続されるメタライズ配線層と、前記絶縁
基板の他表面に被着形成された複数のメタライズランド
部とを具備する半導体素子収納用パッケージを、−４０
〜１２５℃における熱膨張係数が１０ｐｐｍ／℃以上の
有機樹脂を含む絶縁体の表面にランド部が被着形成され
た外部回路基板上に載置し、前記パッケージにおける前
記ランド部と前記外部回路基板の前記ランド部とを導体
層によって電気的に接続固定してなるパッケージの実装
構造であって、 前記パッケージにおける絶縁基板の−４０〜１２５℃に
おける熱膨張係数が８〜１８ｐｐｍ／℃、前記半導体素
子との熱膨張係数差が１２ｐｐｍ／℃以下、ヤング率が
５０〜１５０ＧＰａ、前記前記メタライズランド部の隣
接するランド間の中心間距離が０．８ｍｍ以下であり、
且つ前記パッケージの絶縁基板と前記外部回路基板の絶
縁体との熱膨張係数差が１０ｐｐｍ／℃以下であり、前
記パッケージ側のランド部と外部回路基板側のランド部
との間に介在する前記導体層の厚みが０．３ｍｍ以下で
あることを特徴とする半導体素子収納用パッケージの実
装構造。4. A ceramic insulating substrate, a metallized wiring layer formed on the surface of the insulating substrate and electrically connected to a semiconductor element mounted on the surface of the insulating substrate, and a metallized wiring layer on the other surface of the insulating substrate. A semiconductor device housing package having a plurality of metallized lands formed thereon is
The semiconductor device is mounted on an external circuit board having a land portion formed on the surface of an insulator containing an organic resin having a thermal expansion coefficient of 10 ppm / ° C. or more at 125 ° C. and the land portion of the package and the external circuit board. Wherein the land portion is electrically connected and fixed by a conductor layer, wherein the thermal expansion coefficient of the insulating substrate in the package at −40 to 125 ° C. is 8 to 18 ppm / ° C., and the semiconductor element A difference in thermal expansion coefficient of 12 ppm / ° C. or less, a Young's modulus of 50 to 150 GPa, a center-to-center distance between adjacent lands of the metallized land portion is 0.8 mm or less,
A thermal expansion coefficient difference between the insulating substrate of the package and the insulator of the external circuit board is 10 ppm / ° C. or less, and the conductor interposed between the land on the package and the land on the external circuit board; A mounting structure of a package for housing a semiconductor element, wherein the thickness of the layer is 0.3 mm or less. 【請求項５】前記絶縁基板が、ガラスセラミックス焼結
体からなることを特徴とする請求項４記載の半導体素子
収納用パッケージの実装構造。5. The mounting structure according to claim 4, wherein said insulating substrate is made of a glass ceramic sintered body. 【請求項６】前記半導体素子の実装面積がパッケージ面
積の５０％以上である請求項４記載の半導体素子収納用
パッケージの実装構造。6. The mounting structure of a package for housing a semiconductor element according to claim 4, wherein a mounting area of the semiconductor element is 50% or more of a package area.
JP24534499A 1999-08-31 1999-08-31 Semiconductor element housing package and mounting structure therefor Pending JP2001077224A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24534499A JP2001077224A (en) 1999-08-31 1999-08-31 Semiconductor element housing package and mounting structure therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24534499A JP2001077224A (en) 1999-08-31 1999-08-31 Semiconductor element housing package and mounting structure therefor

Publications (1)

Publication Number Publication Date
JP2001077224A true JP2001077224A (en) 2001-03-23

Family

ID=17132286

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24534499A Pending JP2001077224A (en) 1999-08-31 1999-08-31 Semiconductor element housing package and mounting structure therefor

Country Status (1)

Country Link
JP (1) JP2001077224A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7279787B1 (en) 2001-12-31 2007-10-09 Richard S. Norman Microelectronic complex having clustered conductive members

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7279787B1 (en) 2001-12-31 2007-10-09 Richard S. Norman Microelectronic complex having clustered conductive members

Similar Documents

Publication Publication Date Title
JP3336240B2 (en) Semiconductor element mounting board
JP3631638B2 (en) Mounting structure of semiconductor device package
JP2001338999A (en) Semiconductor element storing package
JP2002076193A (en) Semiconductor element storing package and package mounting board
JPH10189815A (en) Mounting structure for semiconductor element mounting substrate
JP4013339B2 (en) Manufacturing method of electronic component having bump
JP2001077224A (en) Semiconductor element housing package and mounting structure therefor
JP2000252392A (en) Wiring board for mounting semiconductor device and its mounting structure
JP3426827B2 (en) Semiconductor device
JP3297567B2 (en) Package for housing semiconductor element and its mounting structure
JP3872236B2 (en) Wiring board and its mounting structure
JP3347583B2 (en) Wiring board mounting structure
JP2001244390A (en) Package for semiconductor device and mounting structure
JP2001102492A (en) Wiring board and mounting structure thereof
JP3740225B2 (en) Wiring board mounting structure
JP3610239B2 (en) Wiring board for mounting semiconductor device and mounting structure thereof
JP3692215B2 (en) Wiring board mounting structure
JP3502759B2 (en) Semiconductor element mounting structure and wiring board mounting structure
JP2000114424A (en) Semiconductor device mounting board
JP3420447B2 (en) Wiring board mounting structure
JP2000022017A (en) Ceramic wiring substrate and package structure thereof
JP2001044327A (en) Wiring board and mounting structure of the same
JP3784221B2 (en) Wiring board and manufacturing method thereof
JPH11340347A (en) Package for containing semiconductor element
JP3677468B2 (en) Package and its mounting structure