JP2000332048A - Bump structure in semiconductor chip, forming method therefor and mounting structure of flip chip - Google Patents

Bump structure in semiconductor chip, forming method therefor and mounting structure of flip chip

Info

Publication number
JP2000332048A
JP2000332048A JP11145187A JP14518799A JP2000332048A JP 2000332048 A JP2000332048 A JP 2000332048A JP 11145187 A JP11145187 A JP 11145187A JP 14518799 A JP14518799 A JP 14518799A JP 2000332048 A JP2000332048 A JP 2000332048A
Authority
JP
Japan
Prior art keywords
bump
semiconductor chip
metal
gold
metal ball
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11145187A
Other languages
Japanese (ja)
Inventor
Keisuke Matsunami
敬祐 松波
Yasuharu Nakamura
康春 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP11145187A priority Critical patent/JP2000332048A/en
Publication of JP2000332048A publication Critical patent/JP2000332048A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H01L2224/1184—Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a bump structure in a semiconductor chip, for which bump structure has an area equivalent to the case of a bump formed by a plating method, when a bump is formed by using a wire bonding method. SOLUTION: A metal ball is formed on the tip of a metal wire. After the metal ball is bonded to a semiconductor chip, the metal wire is cut while leaving the metal ball, and a metal bump is formed on the semiconductor chip, thus forming a bump structure. In this case, a flattened bump (a gold ball) 1 with the cut part side of the metal ball 12a flattened is formed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体チップにお
けるバンプ構造およびその形成方法およびフリップチッ
プの実装構造に関し、特に、接続媒体として導電粒子を
用いた接続用バンプを半導体チップに形成し、絶縁基板
の基板パッドに電気的接続を行う、半導体チップにおけ
るバンプ構造およびその形成方法およびフリップチップ
の実装構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bump structure in a semiconductor chip, a method for forming the same, and a mounting structure for a flip chip. The present invention relates to a bump structure in a semiconductor chip, a method of forming the same, and a flip chip mounting structure for making electrical connection to a substrate pad of the present invention.

【０００２】[0002]

【従来の技術】電子機器のデジタル化及び信号の高速化
といったシステムの変化に伴い、近年ではノイズの減少
や機器の小型化の要請により、半導体チップの実装方法
としてフリップチップ実装等のベアチップ実装方法が用
いられている。2. Description of the Related Art Along with system changes such as digitization of electronic devices and high-speed signals, recent demands for reduction of noise and miniaturization of devices have resulted in bare chip mounting methods such as flip chip mounting as semiconductor chip mounting methods. Is used.

【０００３】図９は、導電粒子を接続媒体としたフリッ
プチップ実装構造の断面図である。ここで、符号１０１
は絶縁基板、符号１０２は基板パッド、符号１１１は半
導体チップ（ベアチップ）、符号１１２は金（Ａｕ）バ
ンプ、符号１２１はバインダ（接着剤）、符号１２２は
バインダ中に含まれる導電粒子である。FIG. 9 is a sectional view of a flip chip mounting structure using conductive particles as a connection medium. Here, reference numeral 101
Is an insulating substrate, 102 is a substrate pad, 111 is a semiconductor chip (bare chip), 112 is a gold (Au) bump, 121 is a binder (adhesive), and 122 is conductive particles contained in the binder.

【０００４】導電粒子１２２を接続媒体とするフリップ
チップ実装工法には、異方性導電フィルム（ＡＣＦ）方
式と異方性導電樹脂（ＡＣＰ）方式の２種類がある。双
方共にバインダ１２１内に導電粒子１２２が分散してい
る点では共通しており、バインダ１２１の供給形態が、
固体か液体かによって方式が分かれる。There are two types of flip-chip mounting methods using the conductive particles 122 as a connection medium: an anisotropic conductive film (ACF) method and an anisotropic conductive resin (ACP) method. Both are common in that the conductive particles 122 are dispersed in the binder 121, and the supply form of the binder 121 is
The method is divided depending on whether it is solid or liquid.

【０００５】図１０に異方性導電フィルム方式のフリッ
プチップ実装プロセスを示し、図１１に異方性導電樹脂
方式のフリップチップ実装プロセスを示す。図１０に示
すように、異方性導電フィルム方式のフリップチップ実
装プロセスは、基板パッド１０２を備えた絶縁基板１０
１に、セパレータ１３１を備えた異方性導電フィルム
（ＡＣＦ）１３０を貼り付ける。次いで、セパレータ１
３１を剥離すると、導電粒子１２２を含んだバインダ１
２１が絶縁基板１０１に接着された状態となる。一方、
予めベアチップ１１１に金バンプ１１２を形成してお
き、金バンプ１１２を下面側にしてベアチップ１１１
を、前述のセパレータ１３１を剥離したＡＣＦ上に搭載
し、熱圧着により接続する。FIG. 10 shows a flip chip mounting process of an anisotropic conductive film system, and FIG. 11 shows a flip chip mounting process of an anisotropic conductive resin system. As shown in FIG. 10, the flip-chip mounting process of the anisotropic conductive film method uses an insulating substrate 10 having a substrate pad 102.
1, an anisotropic conductive film (ACF) 130 having a separator 131 is attached. Then, separator 1
31 is removed, the binder 1 containing the conductive particles 122 is removed.
21 is bonded to the insulating substrate 101. on the other hand,
The gold bump 112 is formed on the bare chip 111 in advance, and the bare chip 111 is
Is mounted on the ACF from which the separator 131 has been peeled off, and connected by thermocompression bonding.

【０００６】また、異方性導電樹脂方式の場合は、図１
１に示すように、基板パッド１０２を備えた絶縁基板１
０１に、異方性導電樹脂（ＡＣＰ）１３５を塗布する。
予め用意したベアチップ１１１に金バンプ１１２を形成
したものを、金バンプ１１２を下面側にしてＡＣＰ１３
５上に搭載し、熱圧着により接続する。In the case of the anisotropic conductive resin system, FIG.
As shown in FIG. 1, an insulating substrate 1 having substrate pads 102
01, an anisotropic conductive resin (ACP) 135 is applied.
A bare chip 111 having a gold bump 112 formed on a previously prepared bare chip 111 and an ACP 13
5 and connected by thermocompression bonding.

【０００７】ところで、このような導電粒子１２２を用
いたフリップチップ実装では金バンプ１１２と基板パッ
ド１０２との間に挟まれる導電粒子１２２（図１０、図
１１において符号Ａにより指示する）の数により電気的
接続の信頼性に影響し、こうした導電粒子１２２の数が
多ければ多いほど電気的接続は安定する。従って、金バ
ンプ１１２の面積が大きいほど挟み込む導電粒子数１２
２が多くなるので、金バンプ１１２の面積は可能な限り
大きい方が望ましく、一般的には金メッキ法と呼ばれる
工法にて形成された金バンプを用いて、配線基板上に実
装される。なお、バンプの形成方法としては金メッキ法
以外に、ワイヤボンディング法がある。In flip-chip mounting using such conductive particles 122, the number of conductive particles 122 (indicated by the symbol A in FIGS. 10 and 11) sandwiched between the gold bump 112 and the substrate pad 102 depends on the number. This affects the reliability of the electrical connection, and the greater the number of such conductive particles 122, the more stable the electrical connection. Therefore, the larger the area of the gold bump 112 is, the more conductive particles 12
Therefore, it is desirable that the area of the gold bump 112 be as large as possible. Generally, the gold bump 112 is mounted on a wiring board by using a gold bump formed by a method called a gold plating method. As a method for forming the bump, there is a wire bonding method other than the gold plating method.

【０００８】[0008]

【発明が解決しようとする課題】しかしながら、金メッ
キ法によるバンプ形成は、通常の半導体製造工程に加
え、密着及び拡散防止の金属層の形成やメッキの為のレ
ジスト形成など、多くの工程を必要とし、使用される設
備も非常に高価である為、パンプ形成コストが高くなる
という欠点がある。また、この金メッキ法では、ウェー
ハの状態でのみバンプ形成が可能なので、ウェーハの状
態で入手不可能な半導体に対しては適用不可能という欠
点もある。However, the bump formation by the gold plating method requires many steps such as formation of a metal layer for adhesion and diffusion prevention and formation of a resist for plating in addition to a normal semiconductor manufacturing step. Since the equipment used is very expensive, there is a drawback that the pump forming cost is high. In addition, since the gold plating method can form bumps only in the state of a wafer, there is a disadvantage that the method cannot be applied to a semiconductor that cannot be obtained in the state of a wafer.

【０００９】一方、ワイヤボンデイング法によるバンプ
形成は、工程も非常に少なく、ウェーハ及び個片に分割
された半導体のどちらにもバンプ形成が可能であるが、
金メッキ法によって形成されたバンプよりバンプ面積が
小さくなってしまい、フリップチップ実装時に電気的接
続が不安定になるという欠点がある。即ち、従来の金メ
ッキ法およびワイヤボンディング法には、バンプ形成の
面から見るとそれぞれ欠点がある。On the other hand, the bump formation by the wire bonding method has very few steps, and can form bumps on both a wafer and a semiconductor divided into individual pieces.
There is a disadvantage that the bump area is smaller than the bump formed by the gold plating method, and the electrical connection becomes unstable during flip chip mounting. That is, the conventional gold plating method and the conventional wire bonding method have drawbacks from the viewpoint of bump formation.

【００１０】本発明は、上記事情を考慮したもので、ワ
イヤボンデイング法にてバンプを形成するが、メッキ法
によるバンプの場合と同等な面積を持つ半導体チップに
おけるバンプ構造およびその形成方法およびフリップチ
ップの実装構造を提供することを目的とする。The present invention has been made in view of the above circumstances, and forms a bump by a wire bonding method. The bump structure in a semiconductor chip having the same area as a bump formed by a plating method, a method of forming the bump, and a flip chip It is an object of the present invention to provide a mounting structure.

【００１１】[0011]

【課題を解決するための手段】前記課題を解決するため
に請求項１記載の発明は、金属ワイヤの先端に金属ボー
ルを形成し、該金属ボールを半導体チップにボンディン
グ後、前記金属ボールを残して金属ワイヤを切断し、前
記半導体チップに金属バンプを形成してなる半導体チッ
プにおけるバンプ構造において、前記バンプ構造は、前
記金属ボールの切断部側を平坦化した平坦化バンプを備
えてなることを特徴とする。According to a first aspect of the present invention, a metal ball is formed at a tip of a metal wire, and after bonding the metal ball to a semiconductor chip, the metal ball is left. In a semiconductor chip formed by cutting a metal wire and forming a metal bump on the semiconductor chip, the bump structure includes a flattened bump obtained by flattening a cut portion side of the metal ball. Features.

【００１２】また、請求項２記載の発明は、金属ワイヤ
の先端に金属ボールを形成し、該金属ボールを半導体チ
ップにボンディング後、前記金属ボールを残して金属ワ
イヤを切断し、前記半導体チップに金属バンプを形成す
る半導体チップにおけるバンプの形成方法において、前
記金属ボールを残して金属ワイヤを切断した後、該金属
ボールの切断部を押圧して平坦化し、平坦化バンプを形
成することを特徴とする。According to a second aspect of the present invention, a metal ball is formed at the tip of a metal wire, and after bonding the metal ball to a semiconductor chip, the metal wire is cut while leaving the metal ball. A method of forming a bump in a semiconductor chip for forming a metal bump, comprising cutting a metal wire while leaving the metal ball, flattening the cut portion of the metal ball by pressing, and forming a flattened bump. I do.

【００１３】また、請求項３記載の発明は、前記金属ワ
イヤの太さと前記切断して半導体チップに残した金属ボ
ールの量と前記押圧力の大きさをパラメータとして、前
記平坦化バンプを形成することを特徴とする。According to a third aspect of the present invention, the flattening bump is formed by using the thickness of the metal wire, the amount of the metal ball cut and left on the semiconductor chip, and the magnitude of the pressing force as parameters. It is characterized by the following.

【００１４】このようにすれば、所望のサイズの金属バ
ンプを形成することができる。In this way, a metal bump having a desired size can be formed.

【００１５】また、請求項４記載の発明は、前記請求項
１記載の平坦化バンプをフェイスダウンし、予め絶縁基
板に形成した基板パッドに熱圧着して構成することを特
徴とする。According to a fourth aspect of the present invention, the flattening bump according to the first aspect is face-down, and is formed by thermocompression bonding to a substrate pad formed in advance on an insulating substrate.

【００１６】このようにすれば、前記平坦化バンプを備
えたフリップチップの実装構造を実現でき、例えば金バ
ンプと基板パッドとの間に多数の導電粒子を挟み込むこ
とができる。従って、電気的接続の信頼性を高めること
ができる。In this manner, a flip chip mounting structure having the flattening bumps can be realized, and for example, a large number of conductive particles can be sandwiched between the gold bumps and the substrate pads. Therefore, the reliability of the electrical connection can be improved.

【００１７】[0017]

【発明の実施の形態】以下、本発明を図示の実施の形態
に基づいて説明する。なお、既に説明した部分には同一
符号を付し、重複記載を省略する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the illustrated embodiments. Note that the same reference numerals are given to the already described portions, and redundant description is omitted.

【００１８】（１）第１の実施の形態 本実施の形態は、「１段バンプ（平坦化バンプ）」の構
造と、「１段バンプ」の形成方法の場合である。図１は
本実施の形態の側断面図、図２（Ａ），（Ｂ）は本実施
の形態の写真で示す斜視図および写真で示す平面図であ
る。(1) First Embodiment This embodiment relates to a structure of a “single-step bump (flattened bump)” and a method of forming a “single-step bump”. FIG. 1 is a side sectional view of the present embodiment, and FIGS. 2A and 2B are a perspective view shown by a photograph of the present embodiment and a plan view shown by a photograph.

【００１９】図１及び図２（Ａ），（Ｂ）に示すよう
に、本実施の形態のバンプ構造は、断面形状が略楕円形
の金バンプ１により構成され、半導体チップ１１１の入
出力パッド３の上に、前記金バンプ１が接続されてな
る。符号２は、パッシベーション（保護膜）である。As shown in FIGS. 1 and 2A and 2B, the bump structure according to the present embodiment is constituted by a gold bump 1 having a substantially elliptical cross section. 3, the gold bump 1 is connected. Reference numeral 2 denotes a passivation (protective film).

【００２０】次に、本実施の形態のバンプ構造を形成す
る方法を、図３を参照しつつ説明する。図３に示すよう
に、キャピラリ１１に金線１２を挿通し、トーチ１３に
よりスパークさせ（ステップ）、金線１２の先端部に
金ボール１２ａを形成する（ステップ）。次いで、予
め用意した半導体チップ１１１に入出力パッド３を形成
した形成体の該入出力パッド３の上に、前記金ボール１
２ａをボンディングする（ステップ）。ボンディング
後、キャピラリ１１を上昇させて金線１２を引き千切
り、金ボール１２ａのみを入出力パッド３上に残し（ス
テップ）、ステップ〜ステップを繰り返して、所
定数の金ボール１２ａを半導体チップ１１１上に接続す
る（ステップ）。Next, a method for forming the bump structure according to the present embodiment will be described with reference to FIG. As shown in FIG. 3, the gold wire 12 is inserted into the capillary 11 and sparked by the torch 13 (step), and a gold ball 12a is formed at the tip of the gold wire 12 (step). Next, the gold ball 1 is placed on the input / output pad 3 of the formed body in which the input / output pad 3 is formed on the semiconductor chip 111 prepared in advance.
2a is bonded (step). After bonding, the capillary 11 is lifted to cut the gold wire 12 apart, leaving only the gold ball 12a on the input / output pad 3 (step), and repeating the steps 1 to 2 so that a predetermined number of gold balls 12a are placed on the semiconductor chip 111. Connect to (step).

【００２１】次いで、予め用意しておいたレベリングプ
レート（平坦化プレート）１４により、所定の圧力で金
ボール１２ａを押圧し、バンプレベリング（平坦化）を
行うと（ステップ）、金バンプ１が完成する（ステッ
プ）。この金バンプ１の拡大断面図が前記図１であ
り、拡大斜視写真が前記図２（Ａ）、拡大平面写真が前
記図２（Ｂ）である。Next, the gold ball 12a is pressed with a predetermined pressure by a previously prepared leveling plate (flattening plate) 14 to perform bump leveling (flattening) (step), whereby the gold bump 1 is completed. (Step). FIG. 1 is an enlarged sectional view of the gold bump 1, FIG. 2A is an enlarged perspective photograph, and FIG. 2B is an enlarged plan photograph.

【００２２】以上のようにすれば、金線として非常に細
いもの（例えば、直径１８μｍ）を使用し、形成時の
「金ワイヤの量＝金ボールの大きさ」、「レベリング
圧」をパラメータとして適宜に選択することにより、バ
ンプ構造の直径を所望のサイズ（任意のサイズ）にする
ことが可能となる。従って、上記手段によれば、ワイヤ
ボンデイング法によって形成された金バンプが、メッキ
法によって形成された金バンプと同等径以上のサイズを
有することが可能になる。According to the above, a very thin gold wire (for example, a diameter of 18 μm) is used, and “the amount of the gold wire = the size of the gold ball” and the “leveling pressure” at the time of formation are used as parameters. By appropriately selecting, the diameter of the bump structure can be set to a desired size (arbitrary size). Therefore, according to the above means, it is possible for the gold bump formed by the wire bonding method to have a size equal to or larger than the diameter of the gold bump formed by the plating method.

【００２３】＜参考＞図４および図５（Ａ），（Ｂ）は
従来のワイヤボンデイング法によって形成された２段バ
ンプ（段差バンプ）形状の金バンプ１１２を示す図およ
び拡大写真であって、図４は２段バンプの側断面図、図
５（Ａ），（Ｂ）は２段バンプの拡大斜視写真、拡大平
面写真である。 これら図４、図５（Ａ），（Ｂ）と、
前掲の本実施例の図１および図２（Ａ），（Ｂ）とを比
較すると、本実施例の１段バンプと従来例の２段バンプ
との形状の差異が判然とする。 また、図６は従来例の
金メッキ法により形成したバンプ構造の側断面図であ
る。符号１１３はバリアメタル、符号１１４は入出力パ
ッド、符号１１５はパッシベーション（保護膜）、符号
１１６は入出力パッドである。<Reference> FIGS. 4 and 5A and 5B are diagrams and enlarged photographs showing a two-stage bump (step bump) -shaped gold bump 112 formed by a conventional wire bonding method. FIG. 4 is a side sectional view of the two-stage bump, and FIGS. 5A and 5B are an enlarged perspective photograph and an enlarged plan photograph of the two-stage bump. These FIGS. 4 and 5 (A), (B),
By comparing FIG. 1 and FIGS. 2A and 2B of the above-described embodiment, the difference in shape between the one-stage bump of the embodiment and the two-stage bump of the conventional example becomes apparent. FIG. 6 is a side sectional view of a conventional bump structure formed by gold plating. Reference numeral 113 denotes a barrier metal, reference numeral 114 denotes an input / output pad, reference numeral 115 denotes a passivation (protective film), and reference numeral 116 denotes an input / output pad.

【００２４】（２）第２の実施の形態 本実施の形態は、前記第１の実施の形態を用いて形成し
たバンプ構造の金バンプを備えた半導体チップを使用
し、フリップチップ実装構造を実現する場合である。(2) Second Embodiment In this embodiment, a flip-chip mounting structure is realized by using a semiconductor chip provided with gold bumps having a bump structure formed by using the first embodiment. This is the case.

【００２５】図７は本実施の形態のフリップチップ実装
構造の拡大側断面図、図８（Ａ）は本実施の形態におけ
る「小さな基板パッド」の場合の拡大側断面写真、図８
（Ｂ）は「大きな基板パッド」の場合の拡大側断面写真
である。先ず、本実施の形態のフリップチップ実装構造
の形成方法について、異方性導電フィルム（ＡＣＦ）方
式の場合を説明する。本実施の形態で使用する異方性導
電フィルム（ＡＣＦ）方式は、基本的には前記図１０で
説明した場合と同一であり、相違点は金バンプとして前
記第１の実施の形態で説明した１段バンプ（平坦化バン
プ）（図１の金バンプ１を参照）を使用した点である。FIG. 7 is an enlarged side sectional view of the flip chip mounting structure of the present embodiment, and FIG. 8A is an enlarged sectional photograph of a “small substrate pad” of the present embodiment, FIG.
(B) is an enlarged side cross-sectional photograph in the case of “large substrate pad”. First, a method of forming a flip-chip mounting structure according to the present embodiment will be described in the case of an anisotropic conductive film (ACF) method. The anisotropic conductive film (ACF) method used in the present embodiment is basically the same as the case described in FIG. 10 except for the gold bump described in the first embodiment. The point is that a one-step bump (flattening bump) (see the gold bump 1 in FIG. 1) is used.

【００２６】図７に示すように、金バンプ１と基板パッ
ド１０２との間に多数の導電粒子１２２が挟みこまれ
る。この導電粒子１２２の挟み込まれる数が１０個以上
あれば、電気的接続が安定し、信頼性が向上することが
実験により確認されている。As shown in FIG. 7, many conductive particles 122 are sandwiched between the gold bump 1 and the substrate pad 102. It has been confirmed by experiments that if the number of the conductive particles 122 sandwiched is 10 or more, the electrical connection is stable and the reliability is improved.

【００２７】その為には、できる限り大きなバンプが必
要になるが、元々電極パッド（入出力パッド）が大きい
ものについては、或る一定以上の大きさがあれば問題な
く導電粒子の個数を確保できる（図８（Ｂ）参照）。ま
た、非常に小さな電極パッド（基板パッド）では、その
電極以上の大きさのバンプ径が必要になる（図８（Ａ）
参照）。For this purpose, bumps as large as possible are required. However, if the size of the electrode pad (input / output pad) is larger than a certain value, the number of conductive particles can be secured without any problem. (See FIG. 8B). Also, a very small electrode pad (substrate pad) requires a bump diameter larger than the electrode (FIG. 8A).
reference).

【００２８】前記第１の実施の形態で説明した如く、本
発明によれば金バンプの面積を所望の大きさに形成でき
る。従って、ベアチップの金バンプの直径サイズ（大き
さ）とプリント基板（絶縁基板）のパターン幅とを同じ
サイズにする必要がないので、プリント基板設計時の制
約を排除することができる。As described in the first embodiment, according to the present invention, the area of the gold bump can be formed to a desired size. Therefore, it is not necessary to make the diameter size (size) of the gold bump of the bare chip equal to the pattern width of the printed board (insulating board), so that the restrictions at the time of designing the printed board can be eliminated.

【００２９】なお、前記実施の形態では金属ボールとし
て金ボールの場合を説明したが、他に例えばアルミニュ
ーム製のボールにしてもよい。In the above embodiment, the case where the metal ball is a gold ball has been described. Alternatively, for example, a ball made of aluminum may be used.

【００３０】[0030]

【発明の効果】以上説明したように本発明によれば、安
価なワイヤボンデイング法によって金属バンプを形成す
るが、平坦化して金属バンプの面積を大きくできるの
で、フリップチップ実装時に金属バンプと絶縁基板の基
板パッドとの間に多数の導電粒子を挟み込むことが可能
になり、電気的接続を安定させ、電気的接続の信頼性を
向上させることができる。As described above, according to the present invention, a metal bump is formed by an inexpensive wire bonding method. However, since the metal bump can be flattened and the area of the metal bump can be increased, the metal bump and the insulating substrate can be formed at the time of flip chip mounting. A large number of conductive particles can be sandwiched between the substrate and the substrate pad, thereby stabilizing the electrical connection and improving the reliability of the electrical connection.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１の実施の形態の側断面図である。FIG. 1 is a side sectional view of a first embodiment of the present invention.

【図２】同第１の実施の形態の拡大写真であって、
（Ａ）は斜視写真、（Ｂ）は平面写真である。FIG. 2 is an enlarged photograph of the first embodiment,
(A) is a perspective photograph and (B) is a plan photograph.

【図３】同第１の実施の形態の金バンプを形成する過程
を説明する図である。FIG. 3 is a diagram illustrating a process of forming a gold bump according to the first embodiment.

【図４】同第１の実施の形態の１段バンプと比較するた
めの、従来例の２段バンプの側断面図である。FIG. 4 is a side sectional view of a conventional two-stage bump for comparison with the single-stage bump of the first embodiment.

【図５】同従来例の２段バンプの拡大写真であって、
（Ａ）は斜視写真、（Ｂ）は平面写真である。FIG. 5 is an enlarged photograph of a two-stage bump of the conventional example,
(A) is a perspective photograph and (B) is a plan photograph.

【図６】同第１の実施の形態の１段バンプと比較するた
めの、従来例の金メッキ法による金バンプの側断面図で
ある。FIG. 6 is a side sectional view of a gold bump formed by a conventional gold plating method for comparison with the single-stage bump of the first embodiment.

【図７】本発明の第２の実施の形態の側断面図である。FIG. 7 is a side sectional view of a second embodiment of the present invention.

【図８】同第２の実施の形態の拡大写真であって、
（Ａ）は基板パッドが小さい場合の側断面写真、（Ｂ）
は基板パッドが大きい場合の側断面写真である。FIG. 8 is an enlarged photograph of the second embodiment,
(A) is a side sectional photograph when the substrate pad is small, (B)
Is a cross-sectional photograph when the substrate pad is large.

【図９】従来の異方性導電フィルム（ＡＣＦ）方式によ
るフリップチップ実装構造の側断面図である。FIG. 9 is a side sectional view of a conventional flip chip mounting structure using an anisotropic conductive film (ACF) method.

【図１０】従来の異方性導電フィルム（ＡＣＦ）方式に
よるフリップチップ実装構造を形成する過程を説明する
図である。FIG. 10 is a diagram illustrating a process of forming a flip-chip mounting structure using a conventional anisotropic conductive film (ACF) method.

【図１１】従来の異方性導電樹脂（ＡＣＰ）方式による
フリップチップ実装構造を形成する過程を説明する図で
ある。FIG. 11 is a diagram illustrating a process of forming a flip-chip mounting structure using a conventional anisotropic conductive resin (ACP) method.

【符号の説明】[Explanation of symbols]

１，１１２…金バンプ、２…パッシベーション、３，１
１４，１１６…入出力パッド、１１…キャピラリ、１２
…金線、１２ａ…金ボール、１３…トーチ、１０１…絶
縁基板、１０２…基板パッド、１１１…半導体チップ
（ベアチップ）、１１３…バリヤメタル、１２１…バイ
ンダ、１２２…導電粒子、１３０…異方性導電フィルム
（ＡＣＦ）、１３１…セパレータ、１３５…異方性導電
樹脂（ＡＣＰ）。1,112: gold bump, 2: passivation, 3, 1
14, 116: input / output pad, 11: capillary, 12
... gold wire, 12a ... gold ball, 13 ... torch, 101 ... insulating substrate, 102 ... substrate pad, 111 ... semiconductor chip (bare chip), 113 ... barrier metal, 121 ... binder, 122 ... conductive particles, 130 ... anisotropic conductive Film (ACF), 131 ... separator, 135 ... anisotropic conductive resin (ACP).

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 金属ワイヤの先端に金属ボールを形成
し、該金属ボールを半導体チップにボンディング後、前
記金属ボールを残して金属ワイヤを切断し、前記半導体
チップに金属バンプを形成してなる半導体チップにおけ
るバンプ構造において、 前記バンプ構造は、前記金属ボールの切断部側を平坦化
した平坦化バンプを備えてなることを特徴とする半導体
チップにおけるバンプ構造。1. A semiconductor comprising: forming a metal ball at a tip of a metal wire; bonding the metal ball to a semiconductor chip; cutting the metal wire while leaving the metal ball; and forming a metal bump on the semiconductor chip. A bump structure in a semiconductor chip, wherein the bump structure includes a flattened bump in which a cut portion side of the metal ball is flattened. 【請求項２】 金属ワイヤの先端に金属ボールを形成
し、該金属ボールを半導体チップにボンディング後、前
記金属ボールを残して金属ワイヤを切断し、前記半導体
チップに金属バンプを形成する半導体チップにおけるバ
ンプの形成方法において、 前記金属ボールを残して金属ワイヤを切断後、該金属ボ
ールの切断部を押圧して平坦化し、平坦化バンプを形成
することを特徴とする半導体チップにおけるバンプの形
成方法。2. A semiconductor chip in which a metal ball is formed at the tip of a metal wire, and after bonding the metal ball to a semiconductor chip, the metal wire is cut while leaving the metal ball, and a metal bump is formed on the semiconductor chip. In the method of forming a bump, a method of forming a bump in a semiconductor chip is characterized in that after cutting a metal wire while leaving the metal ball, a cut portion of the metal ball is pressed and flattened to form a flattened bump. 【請求項３】 前記金属ワイヤの太さと前記切断して半
導体チップに残した金属ボールの量と前記押圧力の大き
さをパラメータとして、前記平坦化バンプを形成するこ
とを特徴とする請求項２記載のバンプ形成方法。3. The flattening bump is formed by using the thickness of the metal wire, the amount of the metal ball cut and left on the semiconductor chip and the magnitude of the pressing force as parameters. The bump forming method according to the above. 【請求項４】 請求項１記載の平坦化バンプをフェイス
ダウンし、予め絶縁基板に形成した基板パッドに熱圧着
して構成することを特徴とするフリップチップの実装構
造。4. A flip-chip mounting structure, wherein the flattening bump according to claim 1 is face-down, and is thermocompression-bonded to a substrate pad formed on an insulating substrate in advance.
JP11145187A 1999-05-25 1999-05-25 Bump structure in semiconductor chip, forming method therefor and mounting structure of flip chip Pending JP2000332048A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11145187A JP2000332048A (en) 1999-05-25 1999-05-25 Bump structure in semiconductor chip, forming method therefor and mounting structure of flip chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11145187A JP2000332048A (en) 1999-05-25 1999-05-25 Bump structure in semiconductor chip, forming method therefor and mounting structure of flip chip

Publications (1)

Publication Number Publication Date
JP2000332048A true JP2000332048A (en) 2000-11-30

Family

ID=15379449

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009296115A (en) * 2008-06-03 2009-12-17 Daishinku Corp Tuning fork type piezoelectric vibration piece, tuning fork type piezoelectric vibration device, and manufacturing method of tuning fork piezoelectric vibration piece
DE102013211405A1 (en) * 2013-06-18 2014-12-18 Infineon Technologies Ag METHOD FOR PRODUCING A SEMICONDUCTOR MODULE

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009296115A (en) * 2008-06-03 2009-12-17 Daishinku Corp Tuning fork type piezoelectric vibration piece, tuning fork type piezoelectric vibration device, and manufacturing method of tuning fork piezoelectric vibration piece
DE102013211405A1 (en) * 2013-06-18 2014-12-18 Infineon Technologies Ag METHOD FOR PRODUCING A SEMICONDUCTOR MODULE
DE102013211405B4 (en) 2013-06-18 2020-06-04 Infineon Technologies Ag METHOD FOR PRODUCING A SEMICONDUCTOR MODULE

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