JP3397045B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP3397045B2 JP3397045B2 JP18422596A JP18422596A JP3397045B2 JP 3397045 B2 JP3397045 B2 JP 3397045B2 JP 18422596 A JP18422596 A JP 18422596A JP 18422596 A JP18422596 A JP 18422596A JP 3397045 B2 JP3397045 B2 JP 3397045B2
- Authority
- JP
- Japan
- Prior art keywords
- gold
- circuit board
- bumps
- height
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は半導体装置に関
し、特に、半導体チップを回路基板上に金−金拡散接合
により搭載してなる半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a semiconductor chip mounted on a circuit board by gold-gold diffusion bonding.
【０００２】[0002]
【従来の技術】例えばＣＳＰ(chip size package)と呼
ばれるＬＳＩ等からなる半導体チップの実装技術では、
半導体チップを回路基板（メイン回路基板）上に直接実
装するのではなく、サブ回路基板を介して実装してい
る。この場合、サブ回路基板の平面サイズは半導体チッ
プの平面サイズとほぼ同じとなっている。2. Description of the Related Art For example, in the mounting technology of a semiconductor chip composed of an LSI called CSP (chip size package),
The semiconductor chip is not directly mounted on the circuit board (main circuit board) but is mounted via the sub circuit board. In this case, the plane size of the sub-circuit board is almost the same as the plane size of the semiconductor chip.
【０００３】図２は従来のこのような半導体装置の一例
を示したものである。サブ回路基板１は複数枚（例えば
３枚）のセラミック基板１ａを積層したものからなって
いる。このサブ回路基板１の上面周辺部には、導電性ペ
ースト（例えば銀とパラジウムの混合ペースト、以下同
じ）を焼成硬化してなる複数個の第１の接続パッド２が
配列形成されている。サブ回路基板１の下面全体には、
導電性ペーストを焼成硬化してなる複数個の第２の接続
パッド３が格子状に配列形成されている。第１の接続パ
ッド２と第２の接続パッド３の相対応するもの同士は、
それぞれ、サブ回路基板１内に形成された、導電性ペー
ストを焼成硬化してなる内部導通部４を介して接続され
ている。第１の接続パッド２の上面にはニッケルメッキ
層５及び金メッキ層６がこの順で形成されている。第２
の接続パッド３の下面にはニッケルメッキ層７、金メッ
キ層８及びハンダバンプ９がこの順で形成されている。FIG. 2 shows an example of such a conventional semiconductor device. The sub-circuit board 1 is formed by laminating a plurality of (for example, three) ceramic boards 1a. A plurality of first connection pads 2 formed by baking and hardening a conductive paste (for example, a mixed paste of silver and palladium, the same applies hereinafter) are arrayed on the peripheral portion of the upper surface of the sub-circuit board 1. On the entire lower surface of the sub circuit board 1,
A plurality of second connection pads 3 formed by baking and hardening the conductive paste are arranged in a grid pattern. The corresponding ones of the first connection pad 2 and the second connection pad 3 are
Each of them is connected via an internal conducting portion 4 formed in the sub-circuit board 1 by baking and curing a conductive paste. A nickel plating layer 5 and a gold plating layer 6 are formed in this order on the upper surface of the first connection pad 2. Second
A nickel plating layer 7, a gold plating layer 8 and a solder bump 9 are formed in this order on the lower surface of the connection pad 3.
【０００４】半導体チップ１１は、チップ本体１２の下
面周辺部に複数個の接続パッド１３が配列形成され、接
続パッド１３の中央部を除くチップ本体１２の下面全体
に保護膜（パッシベーション膜）１４が形成され、接続
パッド１３の露出面下に下地金属層１５を介して金メッ
キからなる金バンプ１６が形成された構造となってい
る。そして、半導体チップ１１は、その金バンプ１６を
サブ回路基板１の第１の接続パッド２上の金メッキ層６
に金属拡散接合されていることにより、サブ回路基板１
上に搭載されている。この場合、半導体チップ１１とサ
ブ回路基板１との間にはエポキシ樹脂等からなる樹脂封
止材１７が設けられている。In the semiconductor chip 11, a plurality of connection pads 13 are formed in an array on the periphery of the lower surface of the chip body 12, and a protective film (passivation film) 14 is formed on the entire lower surface of the chip body 12 except the central portion of the connection pad 13. A gold bump 16 made of gold plating is formed under the exposed surface of the connection pad 13 with the underlying metal layer 15 interposed therebetween. Then, in the semiconductor chip 11, the gold bumps 16 are formed on the first connection pads 2 of the sub circuit board 1 by the gold plating layer 6 on the first connection pads 2.
Sub-circuit board 1 due to metal diffusion bonding to
Mounted on. In this case, a resin sealing material 17 made of epoxy resin or the like is provided between the semiconductor chip 11 and the sub circuit board 1.
【０００５】メイン回路基板２１は複数枚（例えば３
枚）のガラスエポキシ基板２１ａを積層したものからな
っている。このメイン回路基板２１の上面の所定の個所
には銅箔をエッチングしてなる複数個の接続パッド２２
が格子状に配列形成されている。メイン回路基板２１の
下面には銅箔をエッチングしてなる所定の配線パターン
２３が形成されている。接続パッド２２と配線パターン
２３とは、メイン回路基板２１内に形成されたメッキ等
からなる内部導通部２４を介して接続されている。そし
て、サブ回路基板１は、そのハンダバンプ９をメイン回
路基板２１の接続パッド２２に接合されていることによ
り、メイン回路基板２１上に搭載されている。これによ
り、半導体チップ１１はサブ回路基板１を介してメイン
回路基板２１上に実装されている。A plurality of main circuit boards 21 (for example, 3
It is composed of a stack of glass epoxy substrates 21a. A plurality of connection pads 22 formed by etching a copper foil are provided at predetermined places on the upper surface of the main circuit board 21.
Are arranged in a grid pattern. A predetermined wiring pattern 23 formed by etching a copper foil is formed on the lower surface of the main circuit board 21. The connection pad 22 and the wiring pattern 23 are connected to each other via an internal conducting portion 24 formed in the main circuit board 21 and made of plating or the like. The sub circuit board 1 is mounted on the main circuit board 21 by joining the solder bumps 9 to the connection pads 22 of the main circuit board 21. As a result, the semiconductor chip 11 is mounted on the main circuit board 21 via the sub circuit board 1.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、従来の
このような半導体装置では、半導体チップ１１の金メッ
キからなる金バンプ１６をサブ回路基板１の第１の接続
パッド２上の金メッキ層６に金属拡散接合している関係
から、次のような問題があった。１つは、半導体チップ
１１の金バンプ１６の高さは、サブ回路基板１の反り等
を吸収するために、例えば７０μｍ程度となるべく高い
方が望ましいが、金バンプ１６の高さが高くなると、金
バンプ１６を電解メッキによって形成するのに時間がか
かるという問題があった。もう１つは、電解メッキによ
り形成した金バンプ１６及び無電解メッキにより形成し
た金メッキ層６の硬度は比較的高いので、金−金拡散接
合のために熱圧着するとき比較的大きな圧力を加えるこ
ととなり、この結果金バンプ１６上の保護膜１４（窒化
シリコン等の脆い材料からなる場合が多い。）や接続パ
ッド１３にクラックが発生することがあるという問題が
あった。この発明の課題は、半導体チップの金メッキか
らなる金バンプの高さを低くしても実質的な金バンプの
高さを高くすることができ、また金−金拡散接合のため
の熱圧着を比較的小さい圧力で行うことができるように
することである。However, in such a conventional semiconductor device, the gold bumps 16 made of gold plating of the semiconductor chip 11 are metal-diffused into the gold plating layer 6 on the first connection pads 2 of the sub circuit board 1. Due to the connection, there were the following problems. First, the height of the gold bumps 16 of the semiconductor chip 11 is preferably as high as about 70 μm, for example, in order to absorb the warp of the sub-circuit board 1, but when the height of the gold bumps 16 becomes high, There is a problem that it takes time to form the gold bumps 16 by electrolytic plating. Second, since the hardness of the gold bumps 16 formed by electrolytic plating and the gold plating layer 6 formed by electroless plating is relatively high, a relatively large pressure should be applied when thermocompression bonding for gold-gold diffusion bonding. As a result, there is a problem that cracks may occur in the protective film 14 (often made of a brittle material such as silicon nitride) on the gold bump 16 and the connection pad 13. An object of the present invention is to make it possible to increase the height of a substantial gold bump even if the height of a gold bump made of gold plating of a semiconductor chip is lowered, and to compare thermocompression bonding for gold-gold diffusion bonding. It is to be able to do it with a relatively small pressure.
【０００７】[0007]
【課題を解決するための手段】この発明は、金ワイヤに
より回路基板の接続パッド上に金ワイヤバンプを形成
し、該金バンプに半導体チップの接続パッド上に形成さ
れた金メッキからなる金バンプを金属拡散接合するよう
にしたものである。SUMMARY OF THE INVENTION The present invention, a gold wire bump formed on the connection pads of the circuit board with gold wire, is formed on the connection pads of the semiconductor chip on the gold bumps
The gold bumps made of gold plating are joined by metal diffusion bonding.
【０００８】この発明によれば、両金バンプの合計高さ
が実質的な金バンプの高さとなるので、半導体チップの
金メッキからなる金バンプの高さを低くしても実質的な
金バンプの高さを高くすることができる。例えば、回路
基板の金バンプの高さを３５〜４５μｍ程度とすると、
半導体チップの金バンプの高さを２５〜３５μｍ程度と
低くしても、両金バンプの合計高さを７０μｍ程度以上
とすることができる。また、金ワイヤにより回路基板の
接続パッド上に形成された金バンプの硬度は比較的低い
ので、接合のための熱圧着を比較的小さい圧力で行うこ
とができる。According to the present invention, the total height of both gold bumps is substantially the same as the height of the gold bumps. The height can be increased. For example, if the height of the gold bumps on the circuit board is about 35 to 45 μm,
Even if the height of the gold bumps of the semiconductor chip is lowered to about 25 to 35 μm, the total height of both gold bumps can be set to about 70 μm or more. Further, since the hardness of the gold bump formed on the connection pad of the circuit board by the gold wire is relatively low, thermocompression bonding for bonding can be performed with a relatively small pressure.
【０００９】[0009]
【発明の実施の形態】図１はこの発明の一実施形態にお
ける半導体装置を示したものである。この図において、
図２と同一名称部分には同一の符号を付し、その説明を
適宜省略する。この実施形態では、サブ回路基板１の第
１の接続パッド２の上面にニッケルメッキ層５、金メッ
キ層６及び金バンプ１０がこの順で形成されている。こ
の場合、ニッケルメッキ層５は無電解メッキにより形成
され、その膜厚は２〜３μｍ程度となっている。金メッ
キ層６も無電解メッキにより形成され、その膜厚は０．
２〜１μｍ程度となっている。金バンプ１０は、後で説
明するように、金ワイヤを用いたワイヤボンディング技
術を利用して形成され、その高さは３５〜４５μｍ程度
となっている。一方、半導体チップ１１の金バンプ１６
は電解メッキにより形成され、その高さは２５〜３５μ
ｍ程度となっている。そして、半導体チップ１１は、そ
の金バンプ１６をサブ回路基板１の金バンプ１０に金属
拡散接合されていることにより、サブ回路基板１上に搭
載されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a semiconductor device according to an embodiment of the present invention. In this figure,
The same names as those in FIG. 2 are designated by the same reference numerals, and the description thereof will be appropriately omitted. In this embodiment, a nickel plating layer 5, a gold plating layer 6 and a gold bump 10 are formed in this order on the upper surface of the first connection pad 2 of the sub circuit board 1. In this case, the nickel plating layer 5 is formed by electroless plating and has a film thickness of about 2 to 3 μm. The gold plating layer 6 is also formed by electroless plating and has a film thickness of 0.
It is about 2 to 1 μm. As will be described later, the gold bump 10 is formed by using a wire bonding technique using a gold wire and has a height of about 35 to 45 μm. On the other hand, the gold bumps 16 of the semiconductor chip 11
Is formed by electroplating and its height is 25-35μ
It is about m. The semiconductor chip 11 is mounted on the sub circuit board 1 by metal diffusion bonding the gold bumps 16 to the gold bumps 10 of the sub circuit board 1.
【００１０】ここで、サブ回路基板１の金バンプ１０の
形成方法について説明する。ワイヤボンディング装置を
用いて金バンプ１０を形成する方法は周知であり、いく
つかの方法がある。例えば、図示していないが、キャピ
ラリの孔に金ワイヤを通し、この金ワイヤの先端に放電
等により熱エネルギーを与えることにより、金ワイヤの
先端に金ボールを形成し、次いでキャピラリを下降させ
て金ボールをサブ回路基板１の金メッキ層６に押し付け
て固着させ、この後キャピラリを上昇させまたは横方向
に移動させあるいは上昇させるとともに横方向に移動さ
せることにより、金ワイヤを切断し、かくして金バンプ
１０を形成する方法がある。また、金ワイヤを切断する
前に、金ワイヤを一度形成した金バンプに再度押し付け
ることにより、鏡餠のような２段構造の金バンプ１０を
形成する方法もある。金ワイヤの切断は、ガス炎やカッ
タ等によって行うようにしてもよい。このようにして形
成された金バンプ１０の高さは、金ワイヤの直径が２５
μｍ程度であると、３５〜４５μｍ程度とすることがで
きる。Here, a method for forming the gold bumps 10 on the sub circuit board 1 will be described. The method of forming the gold bump 10 using the wire bonding apparatus is well known, and there are several methods. For example, although not shown, a gold wire is passed through the hole of the capillary, and heat energy is applied to the tip of the gold wire by electric discharge or the like to form a gold ball at the tip of the gold wire, and then the capillary is lowered. The gold ball is pressed against the gold plating layer 6 of the sub-circuit board 1 to be fixed, and then the capillary is raised or moved laterally or moved up and moved laterally to cut the gold wire and thus the gold bump. There is a method of forming 10. In addition, before cutting the gold wire, there is also a method of forming the gold bump 10 having a two-step structure such as a mirror bowl by pressing the gold wire once against the gold bump once formed. The gold wire may be cut with a gas flame or a cutter. The height of the gold bump 10 thus formed is 25 mm when the diameter of the gold wire is 25 mm.
If it is about μm, it can be about 35 to 45 μm.
【００１１】このように、金ワイヤによりサブ回路基板
１の第１の接続パッド２上に金バンプ１０を形成してい
るので、この金バンプ１０に半導体チップ１１の金バン
プ１６を金属拡散接合すると、実質的な金バンプの高さ
は両金バンプ１０、１６の合計高さとなる。この場合、
サブ回路基板１の金バンプ１０の高さを３５〜４５μｍ
程度とし、半導体チップ１１の金バンプ１６の高さを２
５〜３５μｍ程度としているので、両金バンプ１０、１
６の合計高さを７０μｍ程度以上とすることができる。
すなわち、半導体チップ１１の金メッキからなる金バン
プ１６の高さを２５〜３５μｍ程度と低くしても、実質
的な金バンプの高さを７０μｍ程度以上と高くすること
ができる。この結果、半導体チップ１１の金バンプ１６
を電解メッキによって形成する時間を短縮することがで
きる。また、金ワイヤによりサブ回路基板１の第１の接
続パッド２上に形成された金バンプ１０の硬度は比較的
低いので、金−金拡散接合のための熱圧着を比較的小さ
い圧力で行うことができる。この結果、金バンプ１６上
の保護膜１４や接続パッド１３にクラックが発生しにく
いようにすることができ、接合信頼性の向上を図ること
ができる。As described above, since the gold bumps 10 are formed on the first connection pads 2 of the sub-circuit board 1 by the gold wires, when the gold bumps 16 of the semiconductor chip 11 are bonded to the gold bumps 10 by metal diffusion bonding. The substantial height of the gold bumps is the total height of both gold bumps 10 and 16. in this case,
The height of the gold bumps 10 of the sub circuit board 1 is 35 to 45 μm.
And the height of the gold bumps 16 of the semiconductor chip 11 is set to 2
Since the thickness is about 5 to 35 μm, both gold bumps 10, 1
The total height of 6 can be about 70 μm or more.
That is, even if the height of the gold bump 16 made of gold plating on the semiconductor chip 11 is reduced to about 25 to 35 μm, the substantial height of the gold bump can be increased to about 70 μm or more. As a result, the gold bumps 16 of the semiconductor chip 11
It is possible to reduce the time required to form the film by electrolytic plating. In addition, since the hardness of the gold bump 10 formed on the first connection pad 2 of the sub circuit board 1 by the gold wire is relatively low, thermocompression bonding for gold-gold diffusion bonding should be performed with a relatively small pressure. You can As a result, the protective film 14 on the gold bumps 16 and the connection pads 13 can be made less likely to crack, and the bonding reliability can be improved.
【００１２】なお、サブ回路基板１は、セラミック基板
に限らず、ガラスエポキシ基板等を用いてもよく、また
ポリイミド基板等のフレキシブル基板を用いてもよい。
また、半導体チップ１１とサブ回路基板１との組合わせ
は、ＣＳＰに限らず、ＢＧＡ(ball grid array)やＬＧ
Ａ(land grid array)等としてもよい。The sub-circuit board 1 is not limited to a ceramic board, but a glass epoxy board or the like may be used, or a flexible board such as a polyimide board may be used.
The combination of the semiconductor chip 11 and the sub-circuit board 1 is not limited to CSP, but may be BGA (ball grid array) or LG.
It may be A (land grid array) or the like.
【００１３】[0013]
【発明の効果】以上説明したように、この発明によれ
ば、半導体チップの接続パッド上に形成された金メッキ
からなる金バンプの高さを低くしても、実質的な金バン
プの高さを高くすることができるので、半導体チップの
金バンプを電解メッキによって形成する時間を短縮する
ことができる。また、金ワイヤにより回路基板の接続パ
ッド上に形成された金バンプの硬度は比較的低いので、
金属拡散接合のための熱圧着を比較的小さい圧力で行う
ことができ、この結果金バンプ上の保護膜や接続パッド
にクラックが発生しにくいようにすることができ、接合
信頼性の向上を図ることができる。As described above, according to the present invention, even if the height of the gold bump formed of gold plating formed on the connection pad of the semiconductor chip is lowered, the substantial height of the gold bump can be reduced. Since the height can be increased, the time for forming the gold bumps of the semiconductor chip by electrolytic plating can be shortened. Further, the hardness of the gold bump formed on the connection pad of the circuit board by the gold wire is relatively low,
Thermocompression bonding for metal diffusion bonding can be performed with a relatively small pressure, and as a result, cracks can be made less likely to occur in the protective film on the gold bumps and the connection pads, and bonding reliability is improved. be able to.
【図１】この発明の一実施形態における半導体装置の断
面図。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.
【図２】従来の半導体装置の一例の断面図。FIG. 2 is a sectional view of an example of a conventional semiconductor device.
１ サブ回路基板 ２ 第１の接続パッド ３ 第２の接続パッド ９ ハンダバンプ １０ 金バンプ １１ 半導体チップ １６ 金バンプ ２１ メイン回路基板２１ ２２ 接続パッド 1 sub circuit board 2 First connection pad 3 Second connection pad 9 solder bumps 10 gold bumps 11 semiconductor chips 16 gold bumps 21 main circuit board 21 22 Connection pad
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平７−226455（ＪＰ，Ａ) 特開 平９−213753（ＪＰ，Ａ) 特開 平９−181119（ＪＰ，Ａ) 実開 平５−4475（ＪＰ，Ｕ) 国際公開96／9647（ＷＯ，Ａ１) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-7-226455 (JP, A) JP-A-9-213753 (JP, A) JP-A-9-181119 (JP, A) 4475 (JP, U) International Publication 96/9647 (WO, A1) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 21/60
Claims (8)
た金メッキからなる金バンプと、金ワイヤにより回路基
板の接続パッド上に前記金バンプの高さより高く形成さ
れた金ワイヤバンプと、を備え、前記金バンプと前記金
ワイヤバンプとを金属拡散接合したことを特徴とする半
導体装置。1. Formed on a connection pad of a semiconductor chip
With gold bumps made of gold-plated, and gold wire bump formed higher than the height of the gold bumps on the connection pads of the circuit board with gold wire, and the gold and the gold bumps
A semiconductor device characterized by being metal-diffusion bonded to a wire bump .
イン回路基板上に実装してなる半導体装置において、前
記半導体チップの接続パッド上に形成された金メッキか
らなる金バンプと、金ワイヤにより前記サブ回路基板の
接続パッド上に前記金バンプの高さより高く形成された
金ワイヤバンプと、を備え、前記金バンプと前記金ワイ
ヤバンプとを金属拡散接合したことを特徴とする半導体
装置。2. A semiconductor device in which a semiconductor chip is mounted on a main circuit board via a sub circuit board, wherein a gold bump formed of gold plating on a connection pad of the semiconductor chip and a gold wire for the sub board. with a gold wire bump formed higher than the height of the gold bumps on the connection pads of the circuit board, wherein the gold wire and the gold bumps
A semiconductor device characterized by metal diffusion bonding with a bump .
回路基板の平面サイズは前記半導体チップの平面サイズ
とほぼ同じであることを特徴とする半導体装置。3. The semiconductor device according to claim 2, wherein the plane size of the sub-circuit board is substantially the same as the plane size of the semiconductor chip.
おいて、前記半導体チップの金バンプの高さは２５〜３
５μｍ程度であり、前記回路基板の金バンプの高さは３
５〜４５μｍ程度であって、両金バンプの合計高さが７
０μｍ程度以上であることを特徴とする半導体装置。4. The invention according to claim 1, wherein the height of the gold bump of the semiconductor chip is 25 to 3.
It is about 5 μm, and the height of the gold bumps on the circuit board is 3
It is about 5 to 45 μm, and the total height of both gold bumps is 7
A semiconductor device having a thickness of about 0 μm or more.
に金ワイヤバンプを形成し、該金ワイヤバンプに半導体
チップの接続パッド上に形成された金メッキからなる金
バンプを金属拡散接合することを特徴とする半導体装置
の製造方法。5. gold wire gold wire bump formed on the connection pads of the circuit board by, characterized in that the gold bumps made of gold plating formed on the connection pads of the semiconductor chip to the gold wire bump metal diffusion bonding And a method for manufacturing a semiconductor device.
イン回路基板上に実装するに際し、金ワイヤにより前記
サブ回路基板の接続パッド上に金ワイヤバンプを形成
し、該金ワイヤバンプに前記半導体チップの接続パッド
上に形成された金メッキからなる金バンプを金属拡散接
合することにより、前記半導体チップを前記サブ回路基
板上に搭載し、次いで前記サブ回路基板を前記メイン回
路基板上に搭載することを特徴とする半導体装置の製造
方法。6. A semiconductor chip upon mounted on the main circuit board via a sub-circuit board, the gold wire bump formed on the connection pads of the sub-circuit board with gold wire, the semiconductor chip to the gold wire bumps Connection pad
The semiconductor chip is mounted on the sub-circuit board, and then the sub-circuit board is mounted on the main circuit board by metal- bonding gold bumps made of gold plating formed on the top. A method of manufacturing a semiconductor device, comprising:
回路基板の平面サイズは前記半導体チップの平面サイズ
とほぼ同じであることを特徴とする半導体装置の製造方
法。7. The method of manufacturing a semiconductor device according to claim 6, wherein the plane size of the sub-circuit board is substantially the same as the plane size of the semiconductor chip.
おいて、前記半導体チップの金バンプの高さは２５〜３
５μｍ程度であり、前記回路基板の金バンプの高さは３
５〜４５μｍ程度であって、両金バンプの合計高さが７
０μｍ程度以上であることを特徴とする半導体装置の製
造方法。8. The invention according to claim 5, wherein the height of the gold bump of the semiconductor chip is 25 to 3.
It is about 5 μm, and the height of the gold bumps on the circuit board is 3
It is about 5 to 45 μm, and the total height of both gold bumps is 7
A method of manufacturing a semiconductor device, which is about 0 μm or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18422596A JP3397045B2 (en) | 1996-06-26 | 1996-06-26 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18422596A JP3397045B2 (en) | 1996-06-26 | 1996-06-26 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1012668A JPH1012668A (en) | 1998-01-16 |
| JP3397045B2 true JP3397045B2 (en) | 2003-04-14 |
Family
ID=16149567
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18422596A Expired - Fee Related JP3397045B2 (en) | 1996-06-26 | 1996-06-26 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3397045B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1639853A (en) * | 2002-03-11 | 2005-07-13 | 东洋钢板株式会社 | Electronic circuit device and porduction method therefor |
| JP5211801B2 (en) | 2008-03-28 | 2013-06-12 | Ｔｄｋ株式会社 | Electronic components |
-
1996
- 1996-06-26 JP JP18422596A patent/JP3397045B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH1012668A (en) | 1998-01-16 |
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