JPH10233417A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH10233417A JPH10233417A JP9049583A JP4958397A JPH10233417A JP H10233417 A JPH10233417 A JP H10233417A JP 9049583 A JP9049583 A JP 9049583A JP 4958397 A JP4958397 A JP 4958397A JP H10233417 A JPH10233417 A JP H10233417A
- Authority
- JP
- Japan
- Prior art keywords
- gold
- gold bump
- semiconductor chip
- bump
- concave portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は半導体装置及びそ
の製造方法に関する。The present invention relates to a semiconductor device and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】例えばＣＳＰ(chip size package)と呼
ばれるＬＳＩ等からなる半導体チップの実装技術では、
半導体チップを回路基板（メイン回路基板）上に直接実
装するのではなく、サブ回路基板を介して実装してい
る。この場合、サブ回路基板の平面サイズは半導体チッ
プの平面サイズとほぼ同じとなっている。2. Description of the Related Art For example, in a mounting technology of a semiconductor chip such as an LSI called a CSP (chip size package),
Semiconductor chips are not mounted directly on a circuit board (main circuit board), but are mounted via a sub-circuit board. In this case, the plane size of the sub-circuit board is substantially the same as the plane size of the semiconductor chip.
【０００３】図６は従来のこのような半導体装置の一例
を示したものである。サブ回路基板１は複数枚（例えば
３枚）のセラミック基板１ａを積層したものからなって
いる。このサブ回路基板１の上面周辺部には、導電性ペ
ースト（例えば銀とパラジウムの混合ペースト、以下同
じ。）を焼成硬化してなる複数個の第１の接続パッド２
が配列形成されている。サブ回路基板１の下面全体に
は、導電性ペーストを焼成硬化してなる複数個の第２の
接続パッド３が格子状に配列形成されている。第１の接
続パッド２と第２の接続パッド３の相対応するもの同士
は、それぞれ、サブ回路基板１内に形成された、導電性
ペーストを焼成硬化してなる内部導通部４を介して接続
されている。第１の接続パッド２の上面には無電解メッ
キによりニッケルメッキ層５及び金メッキ層６がこの順
で形成されている。第２の接続パッド３の下面にはニッ
ケルメッキ層７、金メッキ層８及びハンダバンプ９がこ
の順で形成されている。FIG. 6 shows an example of such a conventional semiconductor device. The sub-circuit board 1 is formed by laminating a plurality of (for example, three) ceramic substrates 1a. A plurality of first connection pads 2 formed by baking and hardening a conductive paste (for example, a mixed paste of silver and palladium, the same applies hereinafter) are provided on a peripheral portion of the upper surface of the sub-circuit board 1.
Are formed in an array. On the entire lower surface of the sub-circuit board 1, a plurality of second connection pads 3 formed by firing and hardening a conductive paste are arranged in a grid pattern. Corresponding ones of the first connection pads 2 and the second connection pads 3 are connected to each other via internal conductive portions 4 formed in the sub-circuit board 1 and formed by firing and curing a conductive paste. Have been. On the upper surface of the first connection pad 2, a nickel plating layer 5 and a gold plating layer 6 are formed in this order by electroless plating. On the lower surface of the second connection pad 3, a nickel plating layer 7, a gold plating layer 8, and a solder bump 9 are formed in this order.
【０００４】半導体チップ１１は、チップ本体１２の下
面周辺部に複数個の接続パッド１３が配列形成され、接
続パッド１３の中央部を除くチップ本体１２の下面全体
に保護膜（パッシベーション膜）１４が形成され、接続
パッド１３の露出面下に下地金属層１５を介して電解メ
ッキにより金バンプ１６が形成された構造となってい
る。そして、半導体チップ１１の金バンプ１６がサブ回
路基板１の第１の接続パッド２上の金メッキ層６に金−
金での金属拡散接合されていることにより、半導体チッ
プ１１はサブ回路基板１上に搭載されている。この場
合、半導体チップ１１とサブ回路基板１との間にはエポ
キシ樹脂等からなる樹脂封止材１７が設けられている。In the semiconductor chip 11, a plurality of connection pads 13 are arrayed and formed around the lower surface of the chip body 12, and a protective film (passivation film) 14 is formed on the entire lower surface of the chip body 12 except for the center of the connection pads 13. It has a structure in which a gold bump 16 is formed by electroplating under an exposed surface of the connection pad 13 via a base metal layer 15. Then, the gold bumps 16 of the semiconductor chip 11 are applied to the gold plating layer 6 on the first connection pads 2 of the sub-circuit board 1.
The semiconductor chip 11 is mounted on the sub-circuit board 1 by the metal diffusion bonding with gold. In this case, a resin sealing material 17 made of epoxy resin or the like is provided between the semiconductor chip 11 and the sub-circuit board 1.
【０００５】メイン回路基板２１は複数枚（例えば３
枚）のガラスエポキシ基板２１ａを積層したものからな
っている。このメイン回路基板２１の上面の所定の箇所
には銅箔をエッチングしてなる複数個の接続パッド２２
が格子状に配列形成されている。メイン回路基板２１の
下面には銅箔をエッチングしてなる所定の配線パターン
２３が形成されている。接続パッド２２と配線パターン
２３とは、メイン回路基板２１内に形成されたメッキ等
からなる内部導通部２４を介して接続されている。そし
て、サブ回路基板１のハンダバンプ９がメイン回路基板
２１の接続パッド２２に接合されていることにより、サ
ブ回路基板１はメイン回路基板２１上に搭載されてい
る。これにより、半導体チップ１１はサブ回路基板１を
介してメイン回路基板２１上に実装されている。A plurality of main circuit boards 21 (for example, three
) Of glass epoxy substrates 21a. A plurality of connection pads 22 formed by etching copper foil are provided at predetermined positions on the upper surface of the main circuit board 21.
Are arranged in a grid pattern. On the lower surface of the main circuit board 21, a predetermined wiring pattern 23 formed by etching a copper foil is formed. The connection pad 22 and the wiring pattern 23 are connected via an internal conduction portion 24 formed in the main circuit board 21 and made of plating or the like. The sub circuit board 1 is mounted on the main circuit board 21 because the solder bumps 9 of the sub circuit board 1 are joined to the connection pads 22 of the main circuit board 21. Thus, the semiconductor chip 11 is mounted on the main circuit board 21 via the sub circuit board 1.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、従来の
このような半導体装置では、半導体チップ１１の電解メ
ッキによる金バンプ１６をサブ回路基板１の第１の接続
パッド２上の無電解メッキによる金メッキ層６に金−金
での金属拡散接合している関係から、次のような問題が
あった。即ち、電解メッキにより形成した金バンプ１６
及び無電解メッキにより形成した金メッキ層６の硬度は
比較的高いので、金−金での金属拡散接合のために熱圧
着するとき比較的大きな圧力を加える必要があり、この
結果金バンプ１６上の保護膜１４（窒化シリコン等の脆
い材料からなる場合が多い。）や接続パッド１３にクラ
ックが発生することがあるという問題があった。この発
明の課題は、半導体チップを回路基板上に搭載する際の
熱圧着を比較的小さい圧力で行うことができるようにす
ることである。However, in such a conventional semiconductor device, the gold bumps 16 of the semiconductor chip 11 formed by electroplating are formed on the first connection pads 2 of the sub-circuit board 1 by electroless plating. 6 had the following problem from the relation of metal-to-metal diffusion bonding. That is, the gold bumps 16 formed by electrolytic plating
Also, since the hardness of the gold plating layer 6 formed by electroless plating is relatively high, it is necessary to apply a relatively large pressure when performing thermocompression bonding for metal-diffusion bonding with gold and gold. There is a problem that cracks may occur in the protective film 14 (often made of a brittle material such as silicon nitride) and the connection pad 13. An object of the present invention is to make it possible to perform thermocompression bonding with a relatively small pressure when mounting a semiconductor chip on a circuit board.
【０００７】[0007]
【課題を解決するための手段】請求項１記載の発明に係
る半導体装置は、接続パッド上に金ワイヤにより金バン
プが形成された基板と、接続パッド上に金メッキにより
金バンプが形成された半導体チップとを具備し、前記基
板の金バンプの突出面に前記半導体チップの金バンプの
サイズよりも小さめの凹部が形成され、該凹部内に前記
半導体チップの金バンプが圧入されていることにより、
前記両金バンプが相互に接合されているものである。請
求項２記載の発明に係る半導体装置は、接続パッド上に
金ワイヤにより金バンプが形成された基板と、接続パッ
ド上に金メッキにより金バンプが形成された半導体チッ
プとを具備し、前記基板の金バンプの突出面に前記半導
体チップの金バンプのサイズよりも大きめの凹部が形成
され、該凹部内に導電性接合剤が設けられ、前記凹部内
に前記半導体チップの金バンプが挿入されていることに
より、前記両金バンプが前記導電性接合剤を介して相互
に接合されているものである。請求項３記載の発明に係
る半導体装置の製造方法は、半導体チップの接続パッド
上に金メッキにより金バンプを形成し、基板の接続パッ
ド上に金ワイヤにより金バンプを形成し、該金バンプの
突出面に前記半導体チップの金バンプのサイズよりも小
さめの凹部を形成し、該凹部内に前記半導体チップの金
バンプを圧入して前記両金バンプを相互に接合するよう
にしたものである。請求項４記載の発明に係る半導体装
置の製造方法は、半導体チップの接続パッド上に金メッ
キにより金バンプを形成し、基板の接続パッド上に金ワ
イヤにより金バンプを形成し、該金バンプの突出面に前
記半導体チップの金バンプのサイズよりも大きめの凹部
を形成し、該凹部内に導電性接合剤を設け、前記凹部内
に前記半導体チップの金バンプを挿入して前記両金バン
プを前記導電性接合剤を介して相互に接合するようにし
たものである。According to a first aspect of the present invention, there is provided a semiconductor device in which a gold bump is formed on a connection pad by a gold wire and a gold bump is formed on the connection pad by gold plating. A chip, and a recess smaller than the size of the gold bump of the semiconductor chip is formed on the projecting surface of the gold bump of the substrate, and the gold bump of the semiconductor chip is press-fitted in the recess,
The two gold bumps are joined to each other. A semiconductor device according to a second aspect of the present invention includes a substrate having gold bumps formed on connection pads by gold wires, and a semiconductor chip having gold bumps formed on connection pads by gold plating. A concave portion larger than the size of the gold bump of the semiconductor chip is formed on the protruding surface of the gold bump, a conductive bonding agent is provided in the concave portion, and the gold bump of the semiconductor chip is inserted in the concave portion. Thereby, the two gold bumps are bonded to each other via the conductive bonding agent. According to a third aspect of the present invention, in the method of manufacturing a semiconductor device, a gold bump is formed on a connection pad of a semiconductor chip by gold plating, a gold bump is formed on a connection pad of a substrate by a gold wire, and the gold bump is projected. A concave portion smaller than the size of the gold bump of the semiconductor chip is formed on the surface, and the gold bump of the semiconductor chip is pressed into the concave portion to join the two gold bumps to each other. According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device, a gold bump is formed on a connection pad of a semiconductor chip by gold plating, and a gold bump is formed on a connection pad of a substrate by a gold wire. A concave portion larger than the size of the gold bump of the semiconductor chip is formed on the surface, a conductive bonding agent is provided in the concave portion, the gold bump of the semiconductor chip is inserted into the concave portion, and the two gold bumps are formed. They are joined to each other via a conductive joining agent.
【０００８】この発明によれば、金純度の高い金ワイヤ
により形成された金バンプの硬度は比較的低いので、こ
の金バンプの突出面に凹部を容易に形成することができ
る。そして、請求項１または３記載の発明では、硬度が
比較的高い金メッキからなる金バンプを硬度が比較的低
い金ワイヤからなる金バンプの凹部内に圧入するとき、
比較的小さい圧力で圧入することができ、したがって熱
圧着を比較的小さい圧力で行うことができる。また、請
求項２または４記載の発明では、金メッキからなる金バ
ンプを金ワイヤからなる金バンプの凹部内に挿入すると
き、凹部内に予め流動性を有する導電性ペースト等から
なる導電性接合剤が設けられていても、比較的小さい圧
力で挿入することができ、したがってこれまた熱圧着を
比較的小さい圧力で行うことができる。According to the present invention, since the hardness of the gold bump formed by the gold wire having high gold purity is relatively low, the concave portion can be easily formed on the protruding surface of the gold bump. According to the first or third aspect of the invention, when a gold bump made of gold plating having relatively high hardness is press-fitted into a concave portion of a gold bump made of gold wire having relatively low hardness,
The press-fitting can be performed with a relatively small pressure, so that the thermocompression bonding can be performed with a relatively small pressure. According to the second or fourth aspect of the present invention, when a gold bump made of gold plating is inserted into a recess of a gold bump made of a gold wire, a conductive bonding agent made of a conductive paste or the like having fluidity in the recess in advance. Can be inserted with a relatively low pressure, so that the thermocompression bonding can also be performed with a relatively low pressure.
【０００９】[0009]
（第１実施形態）図１はこの発明の第１実施形態におけ
る半導体装置の要部を示したものである。この図におい
て、図６と同一名称部分には同一の符号を付し、その説
明を適宜省略する。この第１実施形態では、サブ回路基
板１の第１の接続パッド２の上面にニッケルメッキ層
５、金メッキ層６及び金バンプ３１がこの順で形成され
ている。この場合、ニッケルメッキ層５及び金メッキ層
６は無電解メッキにより形成されている。金バンプ３１
は、後で説明するように、金ワイヤを用いたワイヤボン
ディング技術を利用して形成され、その突出面中央部に
は凹部３２が形成されている。一方、半導体チップ１１
の接続パッド１３の下面には下地金属層１５及び金バン
プ１６がこの順で形成されている。この場合、金バンプ
１６は電解メッキにより形成されている。そして、半導
体チップ１１の金バンプ１６がサブ回路基板１の金バン
プ３１の凹部３２内に圧入されて金−金での金属拡散接
合されていることにより、半導体チップ１１はサブ回路
基板１上に搭載されている。(First Embodiment) FIG. 1 shows a main part of a semiconductor device according to a first embodiment of the present invention. In this figure, the same parts as those in FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. In the first embodiment, a nickel plating layer 5, a gold plating layer 6, and a gold bump 31 are formed in this order on the upper surface of the first connection pad 2 of the sub-circuit board 1. In this case, the nickel plating layer 5 and the gold plating layer 6 are formed by electroless plating. Gold bump 31
As will be described later, is formed using a wire bonding technique using a gold wire, and a recess 32 is formed at the center of the protruding surface. On the other hand, the semiconductor chip 11
A lower metal layer 15 and a gold bump 16 are formed on the lower surface of the connection pad 13 in this order. In this case, the gold bump 16 is formed by electrolytic plating. The gold bumps 16 of the semiconductor chip 11 are pressed into the recesses 32 of the gold bumps 31 of the sub-circuit board 1 and are bonded by gold-gold metal diffusion, so that the semiconductor chip 11 is placed on the sub-circuit board 1. It is installed.
【００１０】次に、金バンプ３１の形成方法について説
明する。ワイヤボンディング装置を用いて単なる金バン
プを形成する方法は周知であり、いくつかの方法があ
る。例えば、まず、図２（Ａ）に示すように、キャピラ
リ４１の孔４２に金ワイヤ４３を通し、この金ワイヤ４
３の先端部に放電等により熱エネルギーを与えることに
より、金ワイヤ４３の先端部に金ボール４４を形成す
る。次に、図２（Ｂ）に示すように、キャピラリ４１を
下降させて金ボール４４を金バンプ形成面４５（具体的
には、サブ回路基板１の金メッキ層６）に押し付けて固
着させる。次に、キャピラリ４１を上昇させる等の方法
により金ワイヤ４３を切断すると、図２（Ｃ）に示すよ
うに、金バンプ４６が形成される。このようにして形成
された金バンプ４６では、キャピラリ４１の孔４２の形
状等にもよるが、図２（Ｃ）に示す場合には、大径部４
６ａの上面中央部に中径部４６ｂが形成され、中径部４
６ｂの上面中央部に金ワイヤ切断残部からなる小径部４
６ｃが形成された構造となっている。そして、ここまで
の金バンプの形成方法は周知である。Next, a method of forming the gold bump 31 will be described. A method of simply forming a gold bump using a wire bonding apparatus is well known, and there are several methods. For example, first, as shown in FIG. 2A, a gold wire 43 is passed through a hole 42 of a capillary 41,
By applying heat energy to the tip of the gold wire 43 by electric discharge or the like, a gold ball 44 is formed at the tip of the gold wire 43. Next, as shown in FIG. 2B, the capillary 41 is lowered, and the gold ball 44 is pressed and fixed to the gold bump forming surface 45 (specifically, the gold plating layer 6 of the sub-circuit board 1). Next, when the gold wire 43 is cut by a method such as raising the capillary 41, a gold bump 46 is formed as shown in FIG. In the gold bump 46 thus formed, although it depends on the shape of the hole 42 of the capillary 41, etc., in the case shown in FIG.
A middle diameter portion 46b is formed at the center of the upper surface of 6a.
6b, a small-diameter portion 4 consisting of the remaining gold wire cut at the center of the upper surface
6c is formed. The method of forming the gold bumps so far is well known.
【００１１】この第１実施形態では、さらに、図２
（Ｄ）に示すように、表面平坦化用治具４７の下面を金
バンプ４６の突出面に押し付けてこの突出面を平坦化す
るとともに、表面平坦化用治具４７の下面の所定の箇所
に設けられた所定の形状の突起４８を金バンプ４６の突
出面中央部に押し込むことにより、金バンプ４６の突出
面中央部に凹部４６ｄを形成する。この場合、表面平坦
化用治具４７と金バンプ４６とのうち少なくとも一方を
加熱しておく。また、金純度の高い金ワイヤにより形成
された金バンプ４６の硬度は比較的低いので、金バンプ
４６の突出面の平坦化とその中央部への凹部４６ｄの形
成は容易に行うことができる。かくして、図１に示すよ
うに、サブ回路基板１の金メッキ層６の上面に、平坦な
突出面の中央部に凹部３２を有する金バンプ３１が形成
される。In the first embodiment, further, FIG.
As shown in (D), the lower surface of the surface flattening jig 47 is pressed against the protruding surface of the gold bump 46 to flatten the protruding surface, and the lower surface of the surface flattening jig 47 is placed at a predetermined position. By pressing the provided projection 48 having a predetermined shape into the center of the protruding surface of the gold bump 46, a recess 46 d is formed in the center of the protruding surface of the gold bump 46. In this case, at least one of the surface flattening jig 47 and the gold bump 46 is heated. In addition, since the hardness of the gold bump 46 formed by the gold wire with high gold purity is relatively low, the flattening of the protruding surface of the gold bump 46 and the formation of the concave portion 46d at the center thereof can be easily performed. Thus, as shown in FIG. 1, on the upper surface of the gold plating layer 6 of the sub-circuit board 1, the gold bump 31 having the concave portion 32 at the center of the flat protruding surface is formed.
【００１２】ここで、金バンプ３１の凹部３２の形状等
について説明する。一例として、図３に示すように、凹
部３２は、平面サイズが半導体チップ１１の金バンプ１
６の平面サイズよりもやや小さめの柱状部３３の開口部
にテーパー状のガイド部３４が設けられているととも
に、柱状部３３の内壁面に１または複数の空気逃げ溝３
５が設けられた構造となっている。したがって、この場
合には、熱圧着により、硬度が比較的高い金メッキから
なる金バンプ１６を硬度が比較的低い金ワイヤからなる
金バンプ３１の柱状部３３内にガイド部３４に沿って圧
入すると、この圧入される金バンプ１６によって柱状部
３３が押し広げられ、金−金での金属拡散接合が行われ
ることになる。この場合、凹部３２内の空気は空気逃げ
溝３５から放出される。また、硬度が比較的高い金バン
プ１６によって硬度が比較的低い金バンプ３１の凹部３
２を比較的小さい圧力で押し広げることができる。した
がって、熱圧着を比較的小さい圧力で行うことができ
る。この結果、金バンプ１６上の保護膜１４や接続パッ
ド１３にクラックが発生しにくいようにすることがで
き、接合信頼性の向上を図ることができる。Here, the shape and the like of the concave portion 32 of the gold bump 31 will be described. As an example, as shown in FIG. 3, the recess 32 has a planar size of the gold bump 1 of the semiconductor chip 11.
6, a tapered guide portion 34 is provided in the opening of the columnar portion 33 which is slightly smaller than the plane size of the columnar portion 6, and one or more air escape grooves 3 are provided on the inner wall surface of the columnar portion 33.
5 is provided. Therefore, in this case, when the gold bump 16 made of gold plating having relatively high hardness is pressed into the columnar portion 33 of the gold bump 31 made of gold wire having relatively low hardness along the guide portion 34 by thermocompression bonding, The columnar portion 33 is pushed out by the press-fitted gold bump 16, and metal diffusion bonding with gold-gold is performed. In this case, the air in the recess 32 is discharged from the air escape groove 35. Further, the concave portions 3 of the gold bumps 31 having relatively low hardness are formed by the gold bumps 16 having relatively high hardness.
2 can be spread with a relatively small pressure. Therefore, thermocompression bonding can be performed with a relatively small pressure. As a result, it is possible to make it difficult for cracks to occur in the protective film 14 and the connection pads 13 on the gold bumps 16, and to improve the bonding reliability.
【００１３】次に、金バンプ３１の凹部３２の形状等の
他の例について、図４を参照して説明する。この場合、
凹部３２は、開口面が半導体チップ１１の金バンプ１６
の平面サイズよりも大きくて底面が半導体チップ１１の
金バンプ１６の平面サイズよりも小さいテーパー状であ
って、その内壁面に１または複数の空気逃げ溝３５が設
けられた構造となっている。したがって、この場合に
は、熱圧着により、硬度が比較的高い金メッキからなる
金バンプ１６を硬度が比較的低い金ワイヤからなる金バ
ンプ３１の凹部３２内にそのテーパー状の内壁面に沿っ
て圧入すると、この圧入される金バンプ１６によって凹
部３２が押し広げられ、金−金での金属拡散接合が行わ
れることになる。この場合も、凹部３２内の空気は空気
逃げ溝３５から放出される。また、硬度が比較的高い金
バンプ１６によって硬度が比較的低い金バンプ３１の凹
部３２を比較的小さい圧力で押し広げることができる。Next, another example of the shape of the concave portion 32 of the gold bump 31 will be described with reference to FIG. in this case,
The concave portion 32 has an opening surface formed of the gold bump 16 of the semiconductor chip 11.
Has a tapered shape whose bottom surface is smaller than the plane size of the gold bump 16 of the semiconductor chip 11 and has one or a plurality of air escape grooves 35 on its inner wall surface. Therefore, in this case, the gold bump 16 made of gold plating having relatively high hardness is pressed into the recess 32 of the gold bump 31 made of gold wire having relatively low hardness along the tapered inner wall surface by thermocompression bonding. Then, the recess 32 is pushed and expanded by the press-fitted gold bump 16, and the metal diffusion bonding with gold-gold is performed. Also in this case, the air in the concave portion 32 is discharged from the air escape groove 35. Further, the concave portion 32 of the gold bump 31 having a relatively low hardness can be spread with a relatively small pressure by the gold bump 16 having a relatively high hardness.
【００１４】（第２実施形態）次に、図５はこの発明の
第２実施形態における半導体装置の要部を示したもので
ある。この図において、図１と同一名称部分には同一の
符号を付し、その説明を適宜省略する。この第２実施形
態では、金バンプ３１の凹部３２は、半導体チップ１１
の金バンプ１６の平面サイズよりもやや大きい柱状とな
っている。この凹部３２内には、当初流動性を有する上
述した導電性ペーストや導電性接着剤等からなる導電性
接合剤３６が塗布や転写等の方法により適量設けられて
いる。そして、熱圧着により、硬度が比較的高い金メッ
キからなる金バンプ１６を硬度が比較的低い金ワイヤか
らなる金バンプ３１の凹部３２内に挿入すると、この挿
入される金バンプ１６によって導電性接合剤３６が押し
退けられて凹部３２の内面と金バンプ１６の外面との間
に介在され、この介在された導電性接合剤３６を介して
両金バンプ１６、３１が相互に接合されることになる。
この場合、凹部３２内の流動性を有する導電性接合剤３
６を押し退ければよいので、上記第１実施形態の場合と
比較して、金バンプ１６を金バンプ３１の凹部３２内に
より一層小さい圧力で挿入することができる。したがっ
て、熱圧着をより一層小さい圧力で行うことができる。
この結果、金バンプ１６上の保護膜１４や接続パッド１
３にクラックがより一層発生しにくいようにすることが
でき、接合信頼性の向上をより一層図ることができる。Second Embodiment FIG. 5 shows a main part of a semiconductor device according to a second embodiment of the present invention. In this figure, the same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. In the second embodiment, the recess 32 of the gold bump 31 is
The gold bump 16 has a columnar shape slightly larger than the plane size. In the concave portion 32, an appropriate amount of a conductive bonding agent 36 made of the above-described conductive paste or conductive adhesive having fluidity is provided by a method such as coating or transfer. Then, when the gold bump 16 made of gold plating having relatively high hardness is inserted into the recess 32 of the gold bump 31 made of gold wire having relatively low hardness by thermocompression bonding, the inserted gold bump 16 causes the conductive bonding agent to be inserted. 36 is pushed away and interposed between the inner surface of the concave portion 32 and the outer surface of the gold bump 16, and the two gold bumps 16 and 31 are joined to each other via the interposed conductive bonding agent 36.
In this case, the conductive bonding agent 3 having fluidity in the concave portion 32
6 only needs to be pushed away, so that the gold bump 16 can be inserted into the recess 32 of the gold bump 31 with a smaller pressure than in the case of the first embodiment. Therefore, thermocompression bonding can be performed with a much smaller pressure.
As a result, the protection film 14 on the gold bump 16 and the connection pad 1
3 can be made more difficult to generate cracks, and the bonding reliability can be further improved.
【００１５】なお、上記第２実施形態における凹部３２
を、例えば図３または図４に示す場合と同様に、テーパ
ー部を有する構造としてもよい。このようにすると、熱
圧着時に両金バンプ１６、３１に多少の位置ずれがあっ
た場合、両金バンプ１６、３１の一部を金−金での金属
拡散接合とし、残部を導電性接合剤３６を介しての接合
とすることもできる。また、サブ回路基板１は、セラミ
ック基板に限らず、ガラスエポキシ基板等を用いてもよ
く、またポリイミド基板等のフレキシブル基板を用いて
もよい。さらに、半導体チップ１１とサブ回路基板１と
の組合わせは、ＣＳＰに限らず、ＢＧＡ(ball grid arr
ay)ＬＧＡ(land grid array)等としてもよい。Incidentally, the concave portion 32 in the second embodiment is described.
May be a structure having a tapered portion, for example, as in the case shown in FIG. 3 or FIG. In this way, if there is a slight displacement between the two gold bumps 16 and 31 during thermocompression bonding, a part of the two gold bumps 16 and 31 is subjected to metal-diffusion bonding with gold-gold, and the rest is a conductive bonding agent. Bonding via 36 is also possible. Further, the sub-circuit board 1 is not limited to the ceramic board, and may be a glass epoxy board or the like, or a flexible board such as a polyimide board. Further, the combination of the semiconductor chip 11 and the sub-circuit board 1 is not limited to the CSP, but may be a BGA (ball grid arr
ay) It may be an LGA (land grid array) or the like.
【００１６】[0016]
【発明の効果】以上説明したように、この発明によれ
ば、半導体チップの金メッキからなる金バンプを基板の
金ワイヤからなる金バンプの突出面に形成された凹部内
に圧入することにより、または挿入してその間に導電性
接合剤を介在させることにより、両金バンプを相互に接
合しているので、熱圧着を比較的小さい圧力で行うこと
ができ、この結果半導体チップの金バンプ上の保護膜や
接続パッドにクラックが発生しにくいようにすることが
でき、接合信頼性の向上を図ることができる。As described above, according to the present invention, a gold bump made of gold plating on a semiconductor chip is pressed into a recess formed on a projecting surface of a gold bump made of gold wire on a substrate, or By inserting a conductive bonding agent between them, the two gold bumps are bonded to each other, so that thermocompression bonding can be performed with a relatively small pressure, and as a result, protection of the semiconductor chip on the gold bumps can be achieved. Cracks are less likely to occur in the film and the connection pads, and the bonding reliability can be improved.
【図１】この発明の第１実施形態における半導体装置の
要部の断面図。FIG. 1 is a sectional view of a main part of a semiconductor device according to a first embodiment of the present invention.
【図２】（Ａ）〜（Ｄ）はそれぞれ金ワイヤによる金バ
ンプの形成方法の一例を説明するために示す断面図。FIGS. 2A to 2D are cross-sectional views illustrating an example of a method of forming a gold bump using a gold wire.
【図３】金バンプの凹部の一例を説明するために示す断
面図。FIG. 3 is a sectional view illustrating an example of a concave portion of a gold bump.
【図４】金バンプの凹部の他の例を説明するために示す
断面図。FIG. 4 is a sectional view for explaining another example of the concave portion of the gold bump.
【図５】この発明の第２実施形態における半導体装置の
要部の断面図。FIG. 5 is a sectional view of a main part of a semiconductor device according to a second embodiment of the present invention.
【図６】従来の半導体装置の一例の断面図。FIG. 6 is a cross-sectional view of an example of a conventional semiconductor device.
１ サブ回路基板 ２ 第１の接続パッド １１ 半導体チップ １３ 接続パッド １６ 金バンプ ３１ 金バンプ ３２ 凹部 ３６ 導電性接合剤 DESCRIPTION OF SYMBOLS 1 Sub-circuit board 2 1st connection pad 11 Semiconductor chip 13 Connection pad 16 Gold bump 31 Gold bump 32 Depression 36 Conductive bonding agent
Claims (4)
が形成された基板と、接続パッド上に金メッキにより金
バンプが形成された半導体チップとを具備し、前記基板
の金バンプの突出面に前記半導体チップの金バンプのサ
イズよりも小さめの凹部が形成され、該凹部内に前記半
導体チップの金バンプが圧入されていることにより、前
記両金バンプが相互に接合されていることを特徴とする
半導体装置。A substrate having gold bumps formed on the connection pads by gold wires; and a semiconductor chip having gold bumps formed on the connection pads by gold plating. A concave portion smaller than the size of the gold bump of the semiconductor chip is formed, and the gold bump of the semiconductor chip is press-fitted in the concave portion, so that the two gold bumps are joined to each other. Semiconductor device.
が形成された基板と、接続パッド上に金メッキにより金
バンプが形成された半導体チップとを具備し、前記基板
の金バンプの突出面に前記半導体チップの金バンプのサ
イズよりも大きめの凹部が形成され、該凹部内に導電性
接合剤が設けられ、前記凹部内に前記半導体チップの金
バンプが挿入されていることにより、前記両金バンプが
前記導電性接合剤を介して相互に接合されていることを
特徴とする半導体装置。2. A semiconductor device comprising: a substrate having gold bumps formed by gold wires on connection pads; and a semiconductor chip having gold bumps formed on the connection pads by gold plating. A concave portion larger than the size of the gold bump of the semiconductor chip is formed, a conductive bonding agent is provided in the concave portion, and the gold bump of the semiconductor chip is inserted in the concave portion. Are bonded to each other via the conductive bonding agent.
により金バンプを形成し、基板の接続パッド上に金ワイ
ヤにより金バンプを形成し、該金バンプの突出面に前記
半導体チップの金バンプのサイズよりも小さめの凹部を
形成し、該凹部内に前記半導体チップの金バンプを圧入
して前記両金バンプを相互に接合することを特徴とする
半導体装置の製造方法。3. A gold bump is formed on a connection pad of a semiconductor chip by gold plating, a gold bump is formed on a connection pad of a substrate by a gold wire, and a size of the gold bump of the semiconductor chip is formed on a protruding surface of the gold bump. A method of manufacturing a semiconductor device, comprising: forming a smaller recess than the above; and press-fitting the gold bump of the semiconductor chip into the recess to join the two gold bumps to each other.
により金バンプを形成し、基板の接続パッド上に金ワイ
ヤにより金バンプを形成し、該金バンプの突出面に前記
半導体チップの金バンプのサイズよりも大きめの凹部を
形成し、該凹部内に導電性接合剤を設け、前記凹部内に
前記半導体チップの金バンプを挿入して前記両金バンプ
を前記導電性接合剤を介して相互に接合することを特徴
とする半導体装置の製造方法。4. A gold bump is formed on a connection pad of a semiconductor chip by gold plating, a gold bump is formed on a connection pad of a substrate by a gold wire, and a size of the gold bump of the semiconductor chip is formed on a protruding surface of the gold bump. A larger concave portion is formed, a conductive bonding agent is provided in the concave portion, a gold bump of the semiconductor chip is inserted into the concave portion, and the two gold bumps are bonded to each other via the conductive bonding agent. A method of manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9049583A JPH10233417A (en) | 1997-02-19 | 1997-02-19 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9049583A JPH10233417A (en) | 1997-02-19 | 1997-02-19 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10233417A true JPH10233417A (en) | 1998-09-02 |
Family
ID=12835248
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9049583A Pending JPH10233417A (en) | 1997-02-19 | 1997-02-19 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10233417A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008135481A (en) * | 2006-11-27 | 2008-06-12 | Matsushita Electric Works Ltd | Electronic device and its manufacturing method |
| JP2010080638A (en) * | 2008-09-25 | 2010-04-08 | Brother Ind Ltd | Wiring board and manufacturing method of wiring board |
| US8209856B2 (en) | 2008-10-21 | 2012-07-03 | International Business Machines Corporation | Printed wiring board and method for manufacturing the same |
| CN105430901A (en) * | 2014-09-11 | 2016-03-23 | 迪睿合株式会社 | Electronic component and connecting method thereof, connector and manufacturing method thereof, and buffer material |
| JP2020149991A (en) * | 2019-03-11 | 2020-09-17 | 浜松ホトニクス株式会社 | Semiconductor device, substrate with bump, and method of manufacturing semiconductor device |
-
1997
- 1997-02-19 JP JP9049583A patent/JPH10233417A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008135481A (en) * | 2006-11-27 | 2008-06-12 | Matsushita Electric Works Ltd | Electronic device and its manufacturing method |
| JP2010080638A (en) * | 2008-09-25 | 2010-04-08 | Brother Ind Ltd | Wiring board and manufacturing method of wiring board |
| US8209856B2 (en) | 2008-10-21 | 2012-07-03 | International Business Machines Corporation | Printed wiring board and method for manufacturing the same |
| US8373276B2 (en) | 2008-10-21 | 2013-02-12 | International Business Machines Corporation | Printed wiring board and method for manufacturing the same |
| CN105430901A (en) * | 2014-09-11 | 2016-03-23 | 迪睿合株式会社 | Electronic component and connecting method thereof, connector and manufacturing method thereof, and buffer material |
| JP2020149991A (en) * | 2019-03-11 | 2020-09-17 | 浜松ホトニクス株式会社 | Semiconductor device, substrate with bump, and method of manufacturing semiconductor device |
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