JP2000260934A - Manufacture for semiconductor device - Google Patents

Manufacture for semiconductor device

Info

Publication number
JP2000260934A
JP2000260934A JP11058818A JP5881899A JP2000260934A JP 2000260934 A JP2000260934 A JP 2000260934A JP 11058818 A JP11058818 A JP 11058818A JP 5881899 A JP5881899 A JP 5881899A JP 2000260934 A JP2000260934 A JP 2000260934A
Authority
JP
Japan
Prior art keywords
chip
electrode
conductive material
chips
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11058818A
Other languages
Japanese (ja)
Other versions
JP3918350B2 (en
Inventor
Takeshi Yoda
剛 依田
Shuji Koeda
周史 小枝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP05881899A priority Critical patent/JP3918350B2/en
Publication of JP2000260934A publication Critical patent/JP2000260934A/en
Application granted granted Critical
Publication of JP3918350B2 publication Critical patent/JP3918350B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To effectively perform many laminations by forming thick lands at through holes of chips and at electrode parts on the front and rear surface of pad parts, next by laminating each chip and after that by contacting and junctioning conductive material on the front surface of the lower side chip and on the rear surface of the upper side chip by heat melting. SOLUTION: Lands in which conductive material is implanted are formed at through holes 13 of semiconductor chips 16, 17 and 18 at electrode 12 parts on the front and rear surfaces of pad parts. The conductive material by which the lands of electrode 12 parts are formed is made thicker than the height of the elements, and each semiconductor chip 16, 17 and 18 is laminated more than two layers. After that, each conductive material which forms the lands on the surface of the lower side chip and which forms the lands on the surface of the upper side chip is melted by heating and is contacted and junctioned. By the means many laminations can effectively be performed and a three dimensional module can be formed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置に係
り、特に複数の単体素子を階層構造に実装した半導体装
置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a plurality of single elements are mounted in a hierarchical structure.

【０００２】[0002]

【従来の技術】近年におけるＬＳＩの高密度化の要求に
より、複数個のＬＳＩチップを積層して一体化し、かつ
相互に電気接続を行った三次元ＬＳＩモジュールが提案
されている。従来、この種の三次元ＬＳＩモジュールと
しては図４に示す構造のものであった。図４の構成はプ
リント配線板４０にＬＳＩの第１チップ４１ａが搭載さ
れ、さらにその上に第２、第３のチップ４１ｂ、４１ｃ
が搭載される。そして４１ａ、４１ｂ、４１ｃそれぞれ
の電極取り出しパッド４２ａ、４２ｂ、４２ｃとプリン
ト配線板４０上の電極パッド４２ｄとが相互に金属ワイ
ヤ４３あるいはフィルムキャリア上に形成したリードに
より電気的に接続される。しかしながらこれらのモジュ
ールの構成ではモジュール化するする各ＬＳＩ間をワイ
ヤあるいはリードで接続しているため、ＬＳＩチップの
サイズに加えワイヤあるいはリードのための実装領域が
必要となり、実装密度を高め、かつモジュールの小型化
を図る上では有利ではないという問題がある。この問題
を解消するために、ワイヤあるいはリードを不要にした
ワイヤレス、リードレス構造が提案されている（特開平
５−６３１３７、特開平８−２６４７１２）。図５は上
記３次元ＬＳＩモジュールの一例である。図５において
ＬＳＩチップ５１ａ、５１ｂは積層されてプリント配線
板５０に搭載されており、各チップはそれぞれに設けら
れたチップ間の相互接続用電極が直接的に接続されてい
る。５７は内部回路であり、５８は絶縁膜である。その
構成はチップ間の相互接続用電極パッド５２ａと５２
ａ′および５２ｂと５２ｂ′の上下に貫通導電層５５お
よび５６が形成されている。モジュールを構成する各Ｌ
ＳＩチップ５１ａ、５１ｂおよびプリント配線板５０間
はそれぞれバンプ間の相互接続用電極パッド５２ａ′と
５２ｂ間および５２ｂ′と外部端子が接続する配線５４
の間に設けられた半田バンプ５３ａ、５３ｂにより接続
されている。2. Description of the Related Art In response to recent demands for high-density LSIs, three-dimensional LSI modules in which a plurality of LSI chips are stacked and integrated and electrically connected to each other have been proposed. Conventionally, this type of three-dimensional LSI module has a structure shown in FIG. In the configuration of FIG. 4, the first chip 41a of the LSI is mounted on the printed wiring board 40, and the second and third chips 41b and 41c are further mounted thereon.
Is mounted. Then, the electrode extraction pads 42a, 42b, 42c of the respective 41a, 41b, 41c and the electrode pads 42d on the printed wiring board 40 are electrically connected to each other by the metal wires 43 or the leads formed on the film carrier. However, in the configuration of these modules, since the LSIs to be modularized are connected by wires or leads, a mounting area for the wires or leads is required in addition to the size of the LSI chip. There is a problem that it is not advantageous in reducing the size of the device. In order to solve this problem, wireless and leadless structures that do not require wires or leads have been proposed (JP-A-5-63137, JP-A-8-264712). FIG. 5 shows an example of the three-dimensional LSI module. In FIG. 5, LSI chips 51a and 51b are stacked and mounted on a printed wiring board 50, and each chip is directly connected to an interconnect electrode provided between the chips. 57 is an internal circuit, and 58 is an insulating film. The configuration is such that interconnection electrode pads 52a and 52a between chips are provided.
Penetrating conductive layers 55 and 56 are formed above and below a 'and 52b and 52b'. Each L constituting the module
Between the SI chips 51a, 51b and the printed wiring board 50, wiring 54 between the electrode pads 52a 'and 52b for interconnection between bumps and between the electrode pads 52b' and 52b 'and external terminals.
They are connected by solder bumps 53a and 53b provided between them.

【０００３】[0003]

【発明が解決しようとする課題】図５の構造であれば前
述のワイヤまたはリードのための実装領域が不必要であ
るため必要最小限の３次元構造のＬＳＩモジュールが実
現可能になる。しかし、上記した従来技術にはモジュー
ルを構成する各ＬＳＩチップの表面と裏面の両方に互い
に電気的に導通した導電材料の形成と上部のチップ裏面
と下部のチップ表面とを接続する電極およびバンプを別
々に作製する必要があった。またバンプに使用する金属
によっては圧着する必要がるため少なくとも２つのチッ
プ同士ずつ積層して接続しなければならないという課題
があった。With the structure shown in FIG. 5, the above-mentioned mounting area for wires or leads is unnecessary, so that an LSI module having a minimum necessary three-dimensional structure can be realized. However, in the above-described prior art, a conductive material electrically connected to each other is formed on both the front and back surfaces of each LSI chip constituting the module, and electrodes and bumps for connecting the upper chip back surface and the lower chip surface are formed. It had to be made separately. In addition, there is another problem that at least two chips must be stacked and connected to each other because it is necessary to perform pressure bonding depending on the metal used for the bumps.

【０００４】そこで、本発明の目的とするところは、上
記の課題を解決し、より多数の積層化を効率よく行い集
積度の高い半導体装置の提供を目的とするところであ
る。Accordingly, it is an object of the present invention to solve the above-mentioned problems and to provide a highly integrated semiconductor device by efficiently stacking a larger number of devices.

【０００５】[0005]

【課題を解決するための手段】本発明は上記のような課
題を解決するためのもので、以下の手段からなる。SUMMARY OF THE INVENTION The present invention is to solve the above-mentioned problems, and comprises the following means.

【０００６】本発明の半導体装置の製造方法は複数の半
導体チップが高さ方向に所定の間隔をもって積層されて
なり、該チップの電極取り出しパッド部分の表面および
裏面に該チップを貫通するスルーホールを通じて接続す
る電極をもち、該電極によりチップ相互間の接続が行わ
れる構造を持つ半導体装置において、ａ）該チップの該
スルーホールおよび該パッド部分の表面および裏面にあ
る電極部分に導電性材料を埋め込んだランドを形成し、
さらに電極部分の導電性材料を素子高さよりも厚く形成
する、ｂ）該チップを少なくとも２層以上重ねた後、該
下側チップ表面の該導電性材料と該上側チップ裏面の該
導電性材料を加熱により溶融することで接着し接続する
ことを特徴とする。すなわちａ）の構造とすることでス
ルーホールに形成した導電性材料がそのままチップ上下
の接続用の電極として使用できる。さらに素子よりも厚
く形成することで確実に表面および裏面の導電性材料が
その上下のチップの導電性材料による電極と接触するこ
とが可能である。またｂ）の接続方法によれば加熱のみ
でチップ間を接続できるため特別な器具を必要としな
い。さらに該電極を形成する該導電性材料に半田あるい
は低融点金属を用い電解または無電解メッキ法により形
成することを特徴とする。すなわちをメッキ法を用いる
ことでスルーホール中の導電性材料の埋め込みと接続用
の電極が同時に形成できる。さらに電極がすでに形成さ
れた該チップを複数個それぞれ電極取り出しパッド部分
を位置決めした状態で積層し、かつこれらを同時に加熱
により溶融することで接着をし接続することを特徴とす
る。すなわち複数個のチップを同時に接続することが可
能であり、製造工程短縮が可能である。In the method of manufacturing a semiconductor device according to the present invention, a plurality of semiconductor chips are stacked at predetermined intervals in the height direction, and the through holes penetrating through the chip are formed on the front and back surfaces of electrode extraction pad portions of the chip. In a semiconductor device having electrodes to be connected and having a structure in which chips are connected to each other by the electrodes, a) a conductive material is buried in electrode portions on the front surface and the back surface of the through hole and the pad portion of the chip. Form a land
Further, the conductive material of the electrode portion is formed thicker than the element height. B) After at least two layers of the chips are stacked, the conductive material on the lower chip surface and the conductive material on the upper chip back surface are removed. It is characterized in that it is bonded and connected by melting by heating. That is, by adopting the structure of a), the conductive material formed in the through hole can be used as it is as the connection electrodes on the upper and lower portions of the chip. Further, by forming the conductive material to be thicker than the element, the conductive material on the front surface and the back surface can be surely brought into contact with the electrodes made of the conductive material on the upper and lower chips. According to the connection method b), the chips can be connected only by heating, so that no special device is required. Further, it is characterized in that the electrode is formed by electrolytic or electroless plating using solder or a low melting point metal as the conductive material. That is, by using the plating method, the embedding of the conductive material in the through hole and the electrode for connection can be simultaneously formed. Further, the present invention is characterized in that a plurality of the chips on which the electrodes have already been formed are laminated in a state where the electrode extraction pad portions are positioned, and these are simultaneously melted by heating to be bonded and connected. That is, a plurality of chips can be connected at the same time, and the manufacturing process can be shortened.

【０００７】本発明者らは、上記構造の半導体装置の製
造方法を発明し、より多数の積層化を効率よく行い集積
度の高い半導体装置の提供に成功した。The inventors of the present invention have invented a method of manufacturing a semiconductor device having the above structure, and have succeeded in providing a highly integrated semiconductor device by efficiently stacking a larger number of semiconductor devices.

【０００８】[0008]

【発明の実施の形態】以下、本発明に実施の形態につい
て図面に基づき実施例を挙げて説明する。Embodiments of the present invention will be described below with reference to the drawings.

【０００９】（実施例1）図２は本発明の実施例を説明
するための導電性材料のランドの作製工程である。まず
同図（ａ）に示すように２０は第１チップであり厚さ５
００μｍを用いている。２１は内部回路、２２はチップ
引回し電極である。チップの引回し電極パッド部はＡｌ
を使用し、厚さ１μｍ、幅１００μｍ、長さ１００μｍ
とした。設計するチップによりチップ厚さ、電極部大き
さは自由に変更できる。さらに同図（ｂ）に示すように
レーザー照射によりチップ引回し電極部にスルーホール
２３を形成する。異方性エッチングでスルーホールを形
成してもよい。少なくともチップ引回し電極２２よりも
小さい径のスルーホールを開口する。さらに同図（ｃ）
に示すように開口されたスルーホールの側壁には気相法
によりＳｉＯ２またはＳｉＯＮ膜等の絶縁膜２４を２０
００Å程度成長させる。さらに同図（ｄ）に示すように
感光性ドライフィルム２５をチップの表面と裏面に５μ
ｍの厚さにつけ露光および現像を行い、チップ引回し電
極部２６と裏面の電極部２７を露出させる。その後、セ
ンシタイジングおよびアクチベーション法によりＰｄ核
をチップ引回し電極２６、スルーホール内２８および裏
面の電極部２７に形成させる。その後ドライフィルム剥
離する。さらに同図（ｅ）に示すように無電解Ｐｄメッ
キ液（塩化パラジウム２ｇ／Ｌ、水酸化アンモニウム１
６０ｇ／Ｌ、塩化アンモニウム２６ｇ／Ｌ、ホスフィン
酸ナトリウム１０ｇ／Ｌ、溶液温度５０℃）に第１チッ
プ２０を浸漬し厚さ１μｍのＰｄ２９をメッキする。さ
らに同図（ｆ）に示すようにチップ２０を２００℃で溶
融した半田（Ｐｄ：Ｓｎ＝３８：６２％）中に浸漬し、
スルーホール２８内に半田を充填することで半田ランド
２９ａは形成された。以上の方法により請求項１および
請求項２に示したランドの形成が可能であった。(Embodiment 1) FIG. 2 shows a process of manufacturing a land of a conductive material for explaining an embodiment of the present invention. First, as shown in FIG. 1A, reference numeral 20 denotes a first chip having a thickness of 5 mm.
00 μm is used. 21 is an internal circuit, and 22 is a chip lead electrode. The lead electrode pad part of the chip is Al
Using, thickness 1μm, width 100μm, length 100μm
And The chip thickness and the size of the electrode portion can be freely changed depending on the chip to be designed. Further, as shown in FIG. 3B, a through hole 23 is formed in the chip lead electrode portion by laser irradiation. A through hole may be formed by anisotropic etching. At least a through hole having a diameter smaller than that of the chip routing electrode 22 is opened. Further, FIG.
An insulating film 24 such as a SiO 2 film or a SiON film is formed on the side wall of the opened through hole by a vapor phase method as shown in FIG.
Grow about 00Å. Further, as shown in FIG. 3D, a photosensitive dry film 25 is applied to the front and back surfaces of the chip by 5 μm.
Exposure and development are performed to a thickness of m to expose the chip routing electrode section 26 and the electrode section 27 on the back surface. Thereafter, a Pd nucleus is formed on the electrode 26, the inside 28 of the through hole, and the electrode portion 27 on the back surface by the sensitizing and activating methods. Thereafter, the dry film is peeled off. Further, as shown in FIG. 3E, an electroless Pd plating solution (palladium chloride 2 g / L, ammonium hydroxide 1
The first chip 20 is immersed in 60 g / L, ammonium chloride 26 g / L, sodium phosphinate 10 g / L, and the solution temperature is 50 ° C., and Pd29 having a thickness of 1 μm is plated. Further, as shown in FIG. 2F, the chip 20 is immersed in solder (Pd: Sn = 38: 62%) melted at 200 ° C.
The solder land 29a was formed by filling the through hole 28 with solder. According to the above method, the lands described in claims 1 and 2 can be formed.

【００１０】さらに図１は本発明の実施例を説明するた
めの３次元モジュールの作製過程である。まず同図
（ａ）に示すようには第１チップ１０、内部回路１１、
チップ引回しＡＬ電極１２、導電性材料を埋め込むため
のスルーホール１３、絶縁膜１４からなる。第１チップ
１０、内部回路１１、バンプ相互間接続用電極１２、ス
ルーホールの形成、絶縁膜の形成は図２の（ａ）、
（ｂ）および（ｃ）のプロセスを経て作製した。次に図
１（ｂ）に示すようにスルーホール１３内およびチップ
間接続のための導電性材料１５を同時に形成しランドを
形成する。導電性材料のランド形成は図２の（ｄ）、
（ｅ）および（ｆ）のプロセスを経て作製した。次に図
１（ｃ）に示すように導電材料のランドを形成した第１
チップ１６、同様のプロセスによりランドを形成した第
２チップ１７、第３チップ１８および電極部にあらかじ
め導電性材料をメッキで形成したプリント配線板１９を
電極部分を位置決めしランド部分を接触させた状態積層
する。次に同図（ｄ）に示すように位置決めした第１チ
ップ１６、第２チップ１７、第３チップ１８およびプリ
ント配線板１９導電性材料を２００℃で一括加熱により
溶融し接続した。実施例１では積層するチップを３層と
しているが、作製する形態によりそれ以上の複数のチッ
プの積層も同時に可能である。以上の方法により請求項
１および請求項３に示した三次元モジュールの形成が可
能であった。FIG. 1 shows a process of manufacturing a three-dimensional module for explaining an embodiment of the present invention. First, as shown in FIG. 1A, the first chip 10, the internal circuit 11,
It comprises a chip routing AL electrode 12, a through hole 13 for embedding a conductive material, and an insulating film 14. The first chip 10, the internal circuit 11, the electrodes 12 for interconnecting bumps, the formation of through holes, and the formation of an insulating film are shown in FIG.
It was manufactured through the processes of (b) and (c). Next, as shown in FIG. 1B, a conductive material 15 for connecting inside the through hole 13 and between chips is simultaneously formed to form a land. The land formation of the conductive material is shown in FIG.
It was manufactured through the processes of (e) and (f). Next, as shown in FIG. 1 (c), a first conductive material land is formed.
The chip 16, the second chip 17, the third chip 18 on which lands are formed by the same process, and the printed wiring board 19, which is formed by plating a conductive material in advance on the electrode, with the electrode portions positioned and the land portions in contact with each other Laminate. Next, the conductive materials of the first chip 16, the second chip 17, the third chip 18, and the printed wiring board 19 positioned as shown in FIG. In the first embodiment, three chips are stacked, but a plurality of chips can be stacked at the same time depending on the manufacturing mode. The three-dimensional module according to claim 1 and claim 3 can be formed by the above method.

【００１１】（実施例２）図３は本発明の実施例を説明
するための導電性材料のランドの作製工程である。まず
同図（ａ）に示すように３０は第１チップであり厚さ５
００μｍを用いている。３１は内部回路、３２はチップ
引回し電極でありＡｌを使用し、厚さ１μｍ、幅１００
μｍ、長さ１００μｍのものを使用している。設計する
チップによりチップ厚さ、電極部大きさは自由に変更で
きる。さらに同図（ｂ）に示すようにレーザー照射によ
りチップ引回し電極部にスルーホール３３を形成する。
異方性エッチングでスルーホールを形成してもよい。少
なくともチップ引回し電極３２よりも小さい径のスルー
ホールを開口する。さらに同図（ｃ）に示すように開口
されたスルーホールの側壁には気相法によりＳｉＯ２ま
たはＳｉＯＮ膜等の絶縁膜３４を２０００Å程度成長さ
せる。さらに同図（ｄ）に示すように気相法によりチッ
プ表面およびスルーホール内にＡｕ３５を２０００Å程
度成長させメッキ用の電極を形成する。裏面側のスルー
ホール内部および裏面の電極部分へＡｕ膜が十分つかな
いようであれば、チップ裏側からさらに気相法にてＡｕ
を析出させる。さらに同図（ｅ）に示すように感光性レ
ジスト３６を厚さ２μｍ塗布しプレベークした後、露光
および現像を行いチップ引回し電極３２、スルーホール
３３内および裏面の電極部３７を露出する。さらに半田
を電気メッキ（すず（Ｓｎ２＋）４０ｇ／Ｌ、鉛（Ｐ
ｂ）１５ｇ／Ｌ、遊離ほうふっ酸１００ｇ／Ｌ、ホルマ
リン（３７％）１０ｇ／Ｌ、分散剤４０ｇ／Ｌ：温度２
０℃、陰極電流密度３Ａ／ｄｍ２、陽極Ｓｎ７０−Ｐｂ
３０）によりチップ引回し電極３２、スルーホール３３
内および裏面の電極部３７に形成させる。さらに同図
（ｆ）に示すように感光性レジストを剥離しＡｕ電極を
エッチングすることで半田ランド３８は形成された。以
上の方法により請求項１および請求項２に示したランド
の形成が可能であった。(Embodiment 2) FIG. 3 shows a process of manufacturing a land of a conductive material for explaining an embodiment of the present invention. First, as shown in FIG. 1A, reference numeral 30 denotes a first chip having a thickness of 5 mm.
00 μm is used. 31 is an internal circuit, 32 is a chip lead-out electrode made of Al, having a thickness of 1 μm and a width of 100 μm.
μm and a length of 100 μm are used. The chip thickness and the size of the electrode portion can be freely changed depending on the chip to be designed. Further, as shown in FIG. 3B, a through hole 33 is formed in the chip lead electrode portion by laser irradiation.
A through hole may be formed by anisotropic etching. At least a through hole having a diameter smaller than that of the chip routing electrode 32 is opened. Further, an insulating film 34 such as a SiO 2 or SiON film is grown on the side wall of the through hole opened as shown in FIG. Further, as shown in FIG. 2D, Au35 is grown on the chip surface and in the through hole by about 2000.degree. By a vapor phase method to form an electrode for plating. If the Au film does not sufficiently adhere to the inside of the through hole on the back side and the electrode portion on the back side, Au is further applied from the back side of the chip by a vapor phase method.
Is precipitated. Further, as shown in FIG. 3E, a photosensitive resist 36 is applied to a thickness of 2 μm and prebaked, and then exposed and developed to expose the chip lead-out electrode 32, the through hole 33 and the electrode portion 37 on the back surface. Further, the solder is electroplated (tin (Sn 2+ ) 40 g / L, lead (P
b) 15 g / L, free boric acid 100 g / L, formalin (37%) 10 g / L, dispersant 40 g / L: temperature 2
0 ° C., cathode current density 3 A / dm 2 , anode Sn70-Pb
30) chip leading electrode 32, through hole 33
It is formed on the inner and back electrode portions 37. Further, as shown in FIG. 2F, the solder land 38 was formed by removing the photosensitive resist and etching the Au electrode. According to the above method, the lands described in claims 1 and 2 can be formed.

【００１２】さらに実施例１と同様に図１（ｃ）に示す
ように導電材料のランドを形成した第１チップ１６、同
様のプロセスによりランドを形成した第２チップ１７、
第３チップ１８および電極部にあらかじめ導電性材料を
メッキで形成したプリント配線板１９を電極部分を位置
決めしランド部分を接触させた状態積層する。次に同図
（ｄ）に示すように位置決めした第１チップ１６、第２
チップ１７、第３チップ１８およびプリント配線板１９
導電性材料を２００℃で一括加熱により溶融し接続し
た。実施例２においても積層するチップを３層としてい
るが、作製する形態によりそれ以上の複数のチップの積
層も同時に可能である。以上の方法により請求項１およ
び請求項３に示した三次元モジュールの形成が可能であ
った。Further, as shown in FIG. 1C, a first chip 16 on which a land of a conductive material is formed, a second chip 17 on which a land is formed by the same process as in FIG.
A printed wiring board 19 in which a conductive material is previously formed by plating on the third chip 18 and the electrode portion is laminated with the electrode portion positioned and the land portion in contact. Next, the first chip 16 and the second chip 16 positioned as shown in FIG.
Chip 17, third chip 18, and printed wiring board 19
The conductive material was melted at 200 ° C. by batch heating and connected. In the second embodiment as well, the chips to be stacked are three layers, but more chips can be stacked at the same time depending on the form of manufacture. The three-dimensional module according to claim 1 and claim 3 can be formed by the above method.

【００１３】[0013]

【発明の効果】以上のように、本発明により３次元モジ
ュールを構成する各ＬＳＩチップの表面と裏面の両方に
互いに電気的に導通した導電材料の形成と表面と裏面と
を接続する電極を同時に作製することが可能になった。
また複数のＬＳＩチップを同時に接続することが可能に
なった。これにより多数のＬＳＩチップの積層化を効率
よく行い集積度の高い半導体装置の提供が可能になっ
た。As described above, according to the present invention, a conductive material electrically connected to both the front and back surfaces of each of the LSI chips constituting the three-dimensional module is formed, and the electrodes for connecting the front and back surfaces are simultaneously formed. It has become possible to produce.
Also, it has become possible to connect a plurality of LSI chips simultaneously. As a result, a large number of LSI chips can be efficiently stacked and a highly integrated semiconductor device can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の製造方法を説明するための図FIG. 1 is a diagram for explaining a manufacturing method of the present invention.

【図２】本発明のランド製造方法を説明するための図FIG. 2 is a diagram for explaining a land manufacturing method of the present invention.

【図３】本発明のランド製造方法を説明するための図FIG. 3 is a view for explaining a land manufacturing method according to the present invention.

【図４】従来のＬＳＩモジュール製造装置構成を説明す
るための図FIG. 4 is a diagram for explaining a configuration of a conventional LSI module manufacturing apparatus.

【図５】従来のＬＳＩモジュール製造装置構成を説明す
るための図FIG. 5 is a diagram for explaining a configuration of a conventional LSI module manufacturing apparatus.

【符号の説明】[Explanation of symbols]

１０第１チップ １１内部回路 １２チップ引回し電極 １３スルーホール １４絶縁膜 １５導電性材料 １６第１チップ １７第２チップ １８第３チップ １９プリント配線板 ２０第１チップ ２１内部回路 ２２チップ引回し電極 ２３スルーホール ２４絶縁膜 ２５感光性ドライフィルム ２６チップ引回し電極 ２７裏面電極 ２８スルーホール ２９パラジウム ２９ａ半田ランド ３０第１チップ ３１内部回路 ３２チップ引回し電極 ３３スルーホール ３４絶縁膜 ３５金 ３６感光性レジスト ３７裏面電極 ３８半田ランド ４０プリント配線板 ４１ａ第１チップ ４１ｂ第２チップ ４１ｃ第３チップ ４２ａ電極取り出しパッド ４２ｂ電極取り出しパッド ４２ｃ電極取り出しパッド ４２ｄ電極取り出しパッド ４３金属ワイヤ ５０プリント配線板 ５１ａＬＳＩチップ ５１ｂＬＳＩチップ ５２ａチップ間相互接続用電極 ５２ａ′チップ間相互接続用電極 ５２ｂチップ間相互接続用電極 ５２ｂ′チップ間相互接続用電極 ５３ａ半田バンプ ５３ｂ半田バンプ ５４外部端子接続用配線 ５５貫通導電層 ５６貫通導電層 ５７内部回路 ５８絶縁膜 10 first chip 11 internal circuit 12 chip routing electrode 13 through hole 14 insulating film 15 conductive material 16 first chip 17 second chip 18 third chip 19 printed wiring board 20 first chip 21 internal circuit 22 chip routing electrode Reference Signs List 23 through hole 24 insulating film 25 photosensitive dry film 26 chip lead electrode 27 back electrode 28 through hole 29 palladium 29a solder land 30 first chip 31 internal circuit 32 chip lead electrode 33 through hole 34 insulating film 35 gold 36 photosensitive Resist 37 Back surface electrode 38 Solder land 40 Printed wiring board 41a First chip 41b Second chip 41c Third chip 42a Electrode extraction pad 42b Electrode extraction pad 42c Electrode extraction pad 42d Electrode extraction pad 43 Metal wire 50 Printed wiring board 51 aLSI chip 51b LSI chip 52a Inter-chip interconnection electrode 52a 'Inter-chip interconnection electrode 52b Inter-chip interconnection electrode 52b' Inter-chip interconnection electrode 53a Solder bump 53b Solder bump 54 External terminal connection wiring 55 Penetrating conductive layer 56 penetrating conductive layer 57 internal circuit 58 insulating film

フロントページの続き Ｆターム(参考） 5F033 HH07 HH08 HH13 MM30 PP27 PP28 QQ16 QQ37 QQ53 QQ73 QQ75 RR04 RR08 SS11 VV07 XX00 XX33 XX34 Continued on the front page F term (reference) 5F033 HH07 HH08 HH13 MM30 PP27 PP28 QQ16 QQ37 QQ53 QQ73 QQ75 RR04 RR08 SS11 VV07 XX00 XX33 XX34

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 複数の半導体チップが高さ方向に所定の
間隔をもって積層されてなり、該チップの電極取り出し
パッド部分の表面および裏面に該チップを貫通するスル
ーホールを通じて接続する電極をもち、該電極によりチ
ップ相互間の接続が行われる構造を持つ半導体装置にお
いて、 ａ）該チップの該スルーホールおよび該パッド部分の表
面および裏面にある電極部分に導電性材料を埋め込んだ
ランドを形成し、さらに電極部分の導電性材料を素子高
さよりも厚く形成する ｂ）該チップを少なくとも２層以上重ねた後、該下側チ
ップ表面の該導電性材料と該上側チップ裏面の該導電性
材料を加熱により溶融することで接着し接続することを
特徴とした半導体装置の製造方法。1. A semiconductor device comprising: a plurality of semiconductor chips stacked at predetermined intervals in a height direction; and electrodes connected to through-holes penetrating the chip on front and back surfaces of electrode extraction pad portions of the chip. A semiconductor device having a structure in which connection between chips is performed by electrodes, a) forming a land in which a conductive material is embedded in electrode portions on the front surface and the back surface of the through hole and the pad portion of the chip; B) forming at least two layers of the conductive material of the electrode portion thicker than the element height, and then heating the conductive material on the lower chip surface and the conductive material on the upper chip back surface by heating. A method for manufacturing a semiconductor device, characterized by bonding and connecting by melting. 【請求項２】 該電極を形成する該導電性材料に半田あ
るいは低融点金属を用い電解または無電解メッキ法によ
り形成することを特徴とする請求項１記載の半導体装置
製造法。2. The method of manufacturing a semiconductor device according to claim 1, wherein said conductive material for forming said electrode is formed by electrolytic or electroless plating using solder or a low melting point metal. 【請求項３】 電極がすでに形成された該チップを複数
個それぞれ電極取り出しパッド部分を位置決めした状態
で積層し、かつこれらを同時に加熱により溶融すること
で接着し接続することを特徴とする請求項１および請求
項２記載の半導体装置の製造方法。3. A plurality of chips on which electrodes have already been formed are stacked in a state where electrode extraction pad portions are positioned, and are bonded and connected by simultaneously melting them by heating. 3. A method for manufacturing a semiconductor device according to claim 1.
JP05881899A 1999-03-05 1999-03-05 Manufacturing method of semiconductor device Expired - Fee Related JP3918350B2 (en)

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