JPH01183195A - Manufacture of multilayer printed wiring board device - Google Patents
Manufacture of multilayer printed wiring board deviceInfo
- Publication number
- JPH01183195A JPH01183195A JP63007881A JP788188A JPH01183195A JP H01183195 A JPH01183195 A JP H01183195A JP 63007881 A JP63007881 A JP 63007881A JP 788188 A JP788188 A JP 788188A JP H01183195 A JPH01183195 A JP H01183195A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- conductors
- substrates
- printed wiring
- outer layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004020 conductor Substances 0.000 claims abstract description 64
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 230000000149 penetrating effect Effects 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 22
- 229920005989 resin Polymers 0.000 claims description 18
- 239000011347 resin Substances 0.000 claims description 18
- 238000007747 plating Methods 0.000 claims description 10
- 239000003990 capacitor Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 8
- 239000011889 copper foil Substances 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 52
- 238000004806 packaging method and process Methods 0.000 description 5
- 239000004593 Epoxy Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000004840 adhesive resin Substances 0.000 description 1
- 229920006223 adhesive resin Polymers 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
この発明は電子回路部品を多層配線により接続して成る
多層印刷配線板装置に係り、詳細には配線導体の導電性
の向上を図ると共に多層化工程を簡略に行うようにした
多層印刷配線板装置の製造方法に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a multilayer printed wiring board device in which electronic circuit components are connected by multilayer wiring. The present invention relates to a method for manufacturing a multilayer printed wiring board device, which is improved and also simplifies the multilayering process.
（従来の技術）
近年、メモリカード、ＩＣカードが発達し、メモリ容量
等の性能が高く、かつ小形化、薄形化されたより実装密
度の高い印刷配線技術が要求されている。(Prior Art) In recent years, with the development of memory cards and IC cards, there is a demand for printed wiring technology that has high performance such as memory capacity, is smaller and thinner, and has higher packaging density.
従来、実装密度が高くかつ薄形化が可能な印刷配線技術
として、樹脂製基板の上に配線導体と絶縁層とを順次重
ねて形成するものがある。第５図はこの技術によって構
成された従来の多層印刷配線板装置を示す断面図である
。同図において、５１は樹脂製基板（以下基体という）
、５２．５２・・・は電極パッド５２ａを有する半導
体素子、抵抗、コンデンサ等の電子回路部品く以下チッ
プ部品どする）、５３、５５は導体層、５６は絶縁層で
ある。基体５１には凹部５１ａが穿設され、各チップ部
品５２はその凹部５１ａ内に埋設されている。但し、電
極パッド５２ａを形成した面は凹部５１ａの外側となり
、かつ基体表面と一致するようにしである。また、導体
層５３゜５５は、ビアフィル導体５４を介して互いに接
続されている。BACKGROUND ART Conventionally, as a printed wiring technique that allows for high packaging density and thinning, there is a technique in which a wiring conductor and an insulating layer are sequentially formed on a resin substrate. FIG. 5 is a sectional view showing a conventional multilayer printed wiring board device constructed using this technique. In the same figure, 51 is a resin substrate (hereinafter referred to as the base)
, 52, 52, . . . are electronic circuit components such as semiconductor elements, resistors, capacitors, etc. having electrode pads 52a, 53 and 55 are conductive layers, and 56 is an insulating layer. A recess 51a is formed in the base 51, and each chip component 52 is embedded in the recess 51a. However, the surface on which the electrode pad 52a is formed is on the outside of the recess 51a and is aligned with the surface of the base. Further, the conductor layers 53 and 55 are connected to each other via a via fill conductor 54.
以上のような多層印刷配線板装置は、導電性樹脂ペース
トをスクリーン印刷により形成し、基体５１の表面及び
チップ部品５２の表面に導体層５３を形成して各チップ
部品５２の電極パッド５２ａ間を接続する。更に回路を
多層化するため絶縁層５６を形成する。絶縁層５６は感
光性ドライフィルムを熱圧着によって貼着して形成され
ている。この際、ビアフィル導体５４を形成するために
、露出、現像して開口を形成する。この開口に導電性樹
脂ペーストを充填してビアフィル導体５４を形成する。In the multilayer printed wiring board device as described above, a conductive resin paste is formed by screen printing, a conductive layer 53 is formed on the surface of the base 51 and the surface of the chip component 52, and the conductive layer 53 is formed between the electrode pads 52a of each chip component 52. Connecting. Furthermore, an insulating layer 56 is formed to make the circuit multilayered. The insulating layer 56 is formed by adhering a photosensitive dry film by thermocompression bonding. At this time, in order to form the via fill conductor 54, an opening is formed by exposing and developing. This opening is filled with a conductive resin paste to form a via fill conductor 54.
そして、更に外層導体として導体層５５を導電性樹脂ペ
ーストににって形成する。こうして従来の多層印刷配線
板装置は形成されるものである。Further, a conductor layer 55 as an outer layer conductor is formed using a conductive resin paste. A conventional multilayer printed wiring board device is thus formed.
このように従来の多層化技術は、導電性樹脂ペーストの
スクリーン印刷による配線導体の形成及び感光性フィル
ムによる絶縁層の形成を繰返して多層化を実現するため
、先ず第１に製造工程が煩雑であることである。In this way, conventional multilayering technology achieves multilayering by repeatedly forming wiring conductors by screen printing a conductive resin paste and forming an insulating layer with a photosensitive film, so first of all, the manufacturing process is complicated. It is a certain thing.
第２に、導電性樹脂ペーストによる配線導体は、機械的
、或は化学的に生成した銅箔導体より導電性が劣り、こ
れは実装密度向上のため導体幅を狭くすると特に顕著と
なる。このため、回路に要求される特性によっては使用
に制限をうける。Second, wiring conductors made of conductive resin paste have poorer conductivity than mechanically or chemically produced copper foil conductors, and this becomes particularly noticeable when the conductor width is narrowed to improve packaging density. Therefore, its use is limited depending on the characteristics required of the circuit.
第３に導体層間の絶縁層として感光性ドライフィルムを
用いるため、熱圧着のときに、チップ部品５２に機械的
、熱的応力が加わり、更には現像液の浸漬により、内部
構造が損傷する虞がある。Thirdly, since a photosensitive dry film is used as the insulating layer between the conductor layers, mechanical and thermal stress is applied to the chip component 52 during thermocompression bonding, and furthermore, there is a risk that the internal structure may be damaged due to immersion in the developer. There is.
第４に、２層以上に亘るビアフィル導体の形成は困難な
ため、例えば基体５１の両面にチップ部品５２を設ける
場合に、それら表裏部品間の接続ができないという問題
がある。Fourth, since it is difficult to form a via-fill conductor that spans two or more layers, there is a problem that, for example, when chip components 52 are provided on both sides of the base 51, connection between the front and back components cannot be made.
（発明が解決しようとする課題）
従来の多層印刷配線板装置は、多層化工程が複雑である
と共に、感光性ドライフィルムを用いる層間絶縁工程に
おいて、現像液がチップ部品に浸漬して内部を損傷する
虞がある。また、導電性樹脂ペーストによる導体は、銅
箔導体による配線導体より導電率が劣るため、導体幅を
狭めることができず、ＩＣカード、メモリカード等の小
形化。(Problems to be Solved by the Invention) In conventional multilayer printed wiring board devices, the multilayer process is complicated, and in the interlayer insulation process using a photosensitive dry film, the developer soaks into the chip components and damages the internal parts. There is a possibility that In addition, conductors made of conductive resin paste have lower conductivity than wiring conductors made of copper foil conductors, so the conductor width cannot be reduced, making IC cards, memory cards, etc. smaller.
薄形化を制限していた。This limited the ability to make it thinner.
この発明は上記問題点を除去したもので、製造工程が簡
素で、小形化、Ｎ形化を更に推進し、配線導体の導電性
を高め信頼性の向上を図るようにした多層印刷配線板装
置の提供を目的とする。This invention eliminates the above-mentioned problems, and has a multilayer printed wiring board device that has a simple manufacturing process, further promotes miniaturization and N-type wiring, and improves the conductivity of the wiring conductors and improves reliability. The purpose is to provide.
［発明の構成］
く課題を解決するだめの手段）
この発明は予め導体を形成した複数の基板同志を貼設し
て多層基板にし、
この多層基板に各層を貫通する連設孔と凹孔とを形成し
、これら８孔のいずれかに半導体素子。[Structure of the Invention] Means for Solving Problems] This invention provides a multilayer board by pasting together a plurality of boards on which conductors have been formed in advance, and a continuous hole and a recessed hole penetrating each layer in this multilayer board. A semiconductor element is formed in one of these eight holes.
抵抗、コンデンサ等の小型電子回路部品をそれらの電極
部が外層基板の外側表面とほぼ一致するように埋設して
固定し、
残った各連設孔にメッキ法によりスルーホール接続部を
形成すると同時に、前記外層基板と小型電子回路部品と
の一致面に外層導体を形成して所定の電極部間を接続す
るようにしたちのである。Small electronic circuit components such as resistors and capacitors are buried and fixed so that their electrodes are almost in line with the outer surface of the outer layer board, and through-hole connections are formed in each of the remaining continuous holes by plating. An outer layer conductor is formed on the matching surface of the outer layer substrate and the small electronic circuit component to connect predetermined electrode portions.
（作用）
この発明による樹脂製基板に予め形成された導体は多層
化したとぎ内層導体となる。そして、各内層導体を接続
するスルーホール接続部を形成する際に、外層基板の表
面にスルーホール接続部形成方法と同じメッキ法によっ
て外側導体を形成する。したがって、導体層の形成作業
は、従来のように導電性樹脂ペーストと絶縁性樹脂ペー
ストとを繰返し形成するような工程がなく簡単な作業で
済む。また、メッキ法による導体層は導電率が良く導電
性能が良好となり、多層印刷配線板装置の信頼性を向上
するものである。(Function) The conductor formed in advance on the resin substrate according to the present invention becomes a multilayered inner layer conductor. Then, when forming the through-hole connection portions for connecting the inner layer conductors, the outer conductors are formed on the surface of the outer layer substrate by the same plating method as the method for forming the through-hole connection portions. Therefore, the formation of the conductor layer is a simple operation without the need for the conventional process of repeatedly forming a conductive resin paste and an insulating resin paste. Further, the conductor layer formed by plating has good conductivity and conductive performance, which improves the reliability of the multilayer printed wiring board device.
（実施例） 以下、この発明を図示の実施例によって説明する。(Example) The present invention will be explained below with reference to illustrated embodiments.
第１図はこの発明に係る多層印刷配線板装置の製造方法
の一実施例を示す工程図である。同図中、第１図ａはこ
の発明により製造される多層基板１０を示し、第１図す
は上記多層基板１０に電子回路部品を取付けた状態を示
し、第１図Ｃはこの発明により製造された多層印刷配線
板装置の完成品２０を示している。尚、第２図は両面に
導体が予め形成された両面基板、第３図ａ、ｂはガラス
エポキシ等の樹脂基板である。但し、第１図においては
基板の断面を示す斜線は省略している。FIG. 1 is a process diagram showing an embodiment of a method for manufacturing a multilayer printed wiring board device according to the present invention. In the figure, FIG. 1A shows a multilayer board 10 manufactured according to the present invention, FIG. 1A shows a state in which electronic circuit components are attached to the multilayer board 10, and FIG. A completed product 20 of the multilayer printed wiring board device is shown. Incidentally, FIG. 2 shows a double-sided substrate on which conductors are preliminarily formed on both sides, and FIGS. 3a and 3b show resin substrates such as glass epoxy. However, in FIG. 1, diagonal lines indicating the cross section of the substrate are omitted.
先ず、この発明により作成される多層印刷配線板装置の
構成を第１図Ｃを参照して説明する。First, the structure of a multilayer printed wiring board device produced according to the present invention will be explained with reference to FIG. 1C.
第１図Ｃにおいて、１１は第２図に示した両面基板であ
り、該基板１１の各面にはそれぞれ内層（下層）導体２
１．２２が形成されている。In FIG. 1C, 11 is the double-sided board shown in FIG. 2, and each side of the board 11 has an inner layer (lower layer) conductor 2.
1.22 is formed.
１２、１３は中間となる前記基板１１の両側に貼設され
た外層基板であり、これら外層基板１２．１３は前記両
面基板１１を間に貼設して多層基板１０（第１図Ｃ参照
）を構成している。これら外層基板１２．１３には第３
図ａ、ｂに示すように、凹孔１６．１６・・・が予め形
成されており、これら凹孔１６．１６内に、電極部１４
ａ 、 １４ａ・・・を有するチップ部品１４が埋設さ
れ、かつそれらの隙間には絶縁性接着用樹脂１７が充填
されている。これによりチップ部品１４が固定される。Reference numerals 12 and 13 denote outer layer substrates attached to both sides of the intermediate substrate 11, and these outer layer substrates 12 and 13 are attached with the double-sided substrate 11 between them to form the multilayer substrate 10 (see FIG. 1C). It consists of These outer layer substrates 12 and 13 have a third
As shown in Figures a and b, recessed holes 16.16... are formed in advance, and the electrode portion 14 is placed inside these recessed holes 16.16.
Chip components 14 having a, 14a, . . . are buried therein, and the gaps therebetween are filled with insulating adhesive resin 17. This fixes the chip component 14.
尚、各チップ部品１４の電極部１４ａは外層基板１２．
１３の外側表面と一致している。Note that the electrode portion 14a of each chip component 14 is connected to the outer layer substrate 12.
13 coincides with the outer surface.
２５、２６はスルーホール接続部である。これらスルー
ボール接続部２５．２６は、各スルーホール用孔２３、
２８に導体２４．２９をメッキ法により形成して成るも
のであるが、スルーホール用孔２３は、３つの基板１１
．１２．１３を貫通し、スルーホール用孔２８は各外層
基板１２．１３だけに穿設された有底孔である。25 and 26 are through-hole connections. These through-ball connection parts 25 and 26 are connected to each through-hole hole 23,
The conductors 24 and 29 are formed on the three substrates 11 by plating.
．． The through-hole hole 28 is a hole with a bottom formed only in each outer layer substrate 12.13.
そして、チップ部品１４の電気的接続を行うため、上記
スルーホール接続部２５．２６の導体２４．２９とチッ
プ部品１４の電極部１４ａとを互いに接続する外層導体
１５が、外層基板１２．１３の各外側面に形成されてい
る。In order to electrically connect the chip component 14, the outer layer conductor 15 that connects the conductor 24.29 of the through-hole connection portion 25.26 and the electrode portion 14a of the chip component 14 is connected to the outer layer substrate 12.13. formed on each outer surface.
次に、上記構成より成る多層印刷配線板装置の製造方法
の一実施例を説明する。Next, an embodiment of a method for manufacturing a multilayer printed wiring board device having the above structure will be described.
本実施例による多層印刷配線板装置は、第２図及び第３
図ａ、ｂに示すような基板１１．１２．１３を用意する
。両面基板１１は上記のごとく両面印刷配線基板であり
、両面に予め形成される内層導体２１゜２２はＳ電性樹
脂ペーストを印刷、焼成、乾燥して形成した厚膜導体で
も良く、或は両面基板１１として例えばガラスエポキシ
等の予め銅箔導体が形成された銅張積層板を用いる場合
は、エツチングによって形成しても良い。また、本実施
例の場合、外層基板１２．１３にチップ部品１４を埋設
するための凹孔１６をドリル、プレス等の手段によって
予め形成しておく。この場合、凹孔１６は実施例のよう
に貫通孔である必要はなくプレスによって凹ませたもの
でも良い。The multilayer printed wiring board device according to this embodiment is shown in FIGS. 2 and 3.
Substrates 11, 12, and 13 as shown in Figures a and b are prepared. The double-sided board 11 is a double-sided printed wiring board as described above, and the inner layer conductors 21 and 22 formed in advance on both sides may be thick film conductors formed by printing, firing, and drying an S-conductive resin paste, or they may be double-sided printed wiring boards. If a copper-clad laminate made of glass epoxy or the like on which a copper foil conductor is previously formed is used as the substrate 11, the conductor may be formed by etching. Further, in the case of this embodiment, a recessed hole 16 for embedding the chip component 14 in the outer layer substrate 12, 13 is previously formed by means such as a drill or a press. In this case, the recessed hole 16 need not be a through hole as in the embodiment, but may be recessed by pressing.
次に、各基板１１．１２．１３は、接着剤で接着するか
、プリプレグシートを介して熱圧着する等の手段によっ
て貼設する。これによって得られる多層基板１０には、
第１図ａに示すように、上記貼設によってスルーホール
用孔２３となる連設孔２３′、及びスルーボール用孔２
８となる右底孔２８′ を形成する。こうして形成した
各凹孔１６には、第１図すに示すように、チップ部品１
４を挿入し、それらの隙間に樹脂１７を充填して各チッ
プ部品１４を固定する。Next, each of the substrates 11, 12, and 13 is attached by bonding with an adhesive or by thermocompression bonding via a prepreg sheet. The multilayer substrate 10 obtained by this includes:
As shown in FIG. 1a, the continuous hole 23' which becomes the through-hole hole 23 by the pasting, and the through-ball hole 2
A right bottom hole 28' is formed. As shown in FIG.
4 is inserted, and the gaps between them are filled with resin 17 to fix each chip component 14.
このとき、チップ部品１４の電極部１４ａが外層基板１
２、１３の外側表面と一致するように固定する。At this time, the electrode portion 14a of the chip component 14 is connected to the outer layer substrate 1.
Fix it so that it matches the outer surface of 2 and 13.
次に配線工程を行う。配線工程は、銅を使用したメッキ
法により、連設孔２３′及び右底孔２８′の内面を含む
全ての表面に、メッキによる金属（銅）層を析出させる
。その後、エツチングレジストを用いた通常のサブトラ
クティブ法でパターンニングすることで、連設孔２３′
、有底孔２８′ をスルーホール導体化する導体２４．
２９及びチップ部品１４間の相互接続及び回路パターン
を成す外層導体１５を同時に形成する（第１図Ｃ参照）
。尚、メッキ導体２４．２９の形成の際は、チップ部品
１４の電極部１４ａに金メッキ層を形成し、メッキ溶液
による損傷から保護する。Next, a wiring process is performed. In the wiring process, a metal (copper) layer is deposited by plating on all surfaces including the inner surfaces of the continuous hole 23' and the bottom right hole 28' by a plating method using copper. Thereafter, the continuous holes 23' are patterned by a normal subtractive method using an etching resist.
, a conductor 24 for making the bottomed hole 28' into a through-hole conductor.
29 and the chip component 14 and the outer layer conductor 15 forming the circuit pattern (see FIG. 1C).
. Note that when forming the plated conductors 24 and 29, a gold plating layer is formed on the electrode portion 14a of the chip component 14 to protect it from damage caused by the plating solution.
以上の製造方法より成る多層印刷配線板装置によれば、
従来のように、層間絶縁のための煩雑な繰返し工程が不
要である。即ち、この実施例に用いる両面基板１１は、
銅箔導体が予め形成されており、その両面に基板１２．
１３を貼設するだけで内層導体（２１，２２）が形成さ
れる。また、外層導体１５は、スルーホール接続部２５
．２６を形成刃るときに同時に形成する。これらの理由
によって、本多層印刷配線板は、多層化工程が極めて簡
略化されるものである。According to the multilayer printed wiring board device formed by the above manufacturing method,
Unlike the conventional method, there is no need for complicated repeated steps for interlayer insulation. That is, the double-sided substrate 11 used in this example is
A copper foil conductor is formed in advance, and a substrate 12 is formed on both sides of the copper foil conductor.
Inner layer conductors (21, 22) are formed by simply pasting 13. Further, the outer layer conductor 15 has a through-hole connection portion 25
．． 26 is formed at the same time. For these reasons, the present multilayer printed wiring board allows the multilayering process to be extremely simplified.
また、内層導体２１．２２．メッキ法による外層導体１
５及びスルーホール内導体２４．２９は、導電性樹脂ペ
ーストによる導体に比し導電性が良好であり、配線幅を
狭くしても、導電性能が問題となることはない。このた
め、回路パターンの信頼性が増大する。加えて、冬作・
内層導体１５．２１．２２間の間隔を従来の多層印刷配
線板より狭めることができ、導電性樹脂ペーストによる
多層印刷配線板に比し、実装密度を各段と高め、回路パ
ターンの複雑化による多層印刷配線板の層数増加を回避
し、厚みの増大を防ぐ。In addition, the inner layer conductors 21, 22. Outer layer conductor 1 by plating method
5 and through-hole conductors 24 and 29 have better conductivity than conductors made of conductive resin paste, and even if the wiring width is narrowed, conductive performance will not be a problem. This increases the reliability of the circuit pattern. In addition, winter crops
The spacing between the inner layer conductors 15, 21, and 22 can be narrower than that of conventional multilayer printed wiring boards, and compared to multilayer printed wiring boards made of conductive resin paste, the packaging density is significantly increased, and the circuit pattern becomes more complex. To avoid an increase in the number of layers of a multilayer printed wiring board and prevent an increase in thickness.
第４図は所定断面で切断したこの発明による多層印刷配
線板装置の概略斜視図であるが、外層導体１５は、幅が
小さいために、チップ部品１４の上に形成することが可
能で、内層導体２１．２２のみに回路パターンの負担を
かけることがない。したがって、内層導体にアースパタ
ーン等の共通電位パタ一ンを形成し、上層導体に信号パ
ターンを形成することができるので、より回路パターン
の信頼性に寄与するものである。FIG. 4 is a schematic perspective view of the multilayer printed wiring board device according to the present invention cut at a predetermined cross section. Since the outer layer conductor 15 has a small width, it can be formed on the chip component 14, and the inner layer The load of the circuit pattern is not placed only on the conductors 21 and 22. Therefore, a common potential pattern such as a ground pattern can be formed on the inner layer conductor, and a signal pattern can be formed on the upper layer conductor, which further contributes to the reliability of the circuit pattern.
尚、凹孔１６は、スルーホール用孔２３を穿設する工程
で同時に形成しても良いし、第２図、第３図の状態、即
ち多層基板１０とする前の段階で形成しても良い。また
、実施例では、凹孔１６に埋設する電子部品として小型
電子回路部品であるチップ部品を選んだが、他の電子部
品でも良い。Incidentally, the recessed hole 16 may be formed at the same time as the step of drilling the through-hole hole 23, or may be formed in the state shown in FIGS. 2 and 3, that is, at a stage before forming the multilayer substrate 10. good. Further, in the embodiment, a chip component, which is a small electronic circuit component, was selected as the electronic component to be buried in the recessed hole 16, but other electronic components may be used.
［発明の効果］
以上説明したようにこの発明によれば、高い実装密度と
薄形化を満足した上で、導体層の導電性を向上する効果
がある。[Effects of the Invention] As described above, the present invention has the effect of improving the conductivity of the conductor layer while satisfying high packaging density and thinning.
第１図はこの発明に係る多層印刷配線板装置の一実施例
を説明するだめの工程図、第２図及び第３図は第１図の
実施例における多層基板を説明するだめの断面図、第４
図はこの発明による多層印刷配線板装置の斜視図、第５
図は従来の多層印刷配線板を示す断面図である。
１１・・・両面基板、１２．１３・・・外層基板、１４
・・・小型電子回路部品、１４ａ・・・電極部、１５・
・・外層導体、１６・・・凹孔、１７・・・樹脂、２０
・・・完成品、２１．２２・・・内層導体、２３、２８
・・・スルーホール用孔、２４．２９・・・スルーホー
ル内導体、２５．２６・・・スルーホール接続部。
代理人 弁理士 伊 藤 進０ ．０
０ ρ1 is a process diagram illustrating an embodiment of a multilayer printed wiring board device according to the present invention; FIGS. 2 and 3 are sectional views illustrating a multilayer board in the embodiment of FIG. 1; Fourth
FIG. 5 is a perspective view of a multilayer printed wiring board device according to the present invention.
The figure is a sectional view showing a conventional multilayer printed wiring board. 11...Double-sided substrate, 12.13...Outer layer substrate, 14
...Small electronic circuit component, 14a...Electrode part, 15.
... Outer layer conductor, 16 ... Recessed hole, 17 ... Resin, 20
...Finished product, 21.22...Inner layer conductor, 23, 28
...Through hole hole, 24.29...Through hole internal conductor, 25.26...Through hole connection part. Agent Patent Attorney Susumu Ito0. 0 0 ρ
Claims (1)
基板を製作する基板貼合わせ工程と、前記多層基板に各
層を貫通する連設孔及び凹孔とを形成し、これら各孔の
いずれかに半導体素子，抵抗，コンデンサ等の小型電子
回路部品をそれらの電極部が外層基板の外側表面とほぼ
一致するように埋設し固定する工程と、 残った前記各連設孔にメッキ法によりスルーホール接続
部を形成すると同時に、前記外層基板と小型電子回路部
品との一致面に外層導体を形成して所定の端子部間を接
続する配線工程とを具備することを特徴とする多層印刷
配線板装置の製造方法。[Claims] A substrate bonding step of manufacturing a multilayer substrate by bonding a plurality of resin substrates on which conductors have been formed in advance, and forming continuous holes and recessed holes penetrating each layer in the multilayer substrate. , a step of embedding and fixing a small electronic circuit component such as a semiconductor element, resistor, or capacitor in one of these holes so that their electrode portions almost coincide with the outer surface of the outer layer substrate; It is characterized by comprising a wiring step of forming a through-hole connection part in the hole by a plating method, and at the same time forming an outer layer conductor on the matching surface of the outer layer board and the small electronic circuit component to connect predetermined terminal parts. A method for manufacturing a multilayer printed wiring board device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63007881A JPH01183195A (en) | 1988-01-18 | 1988-01-18 | Manufacture of multilayer printed wiring board device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63007881A JPH01183195A (en) | 1988-01-18 | 1988-01-18 | Manufacture of multilayer printed wiring board device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01183195A true JPH01183195A (en) | 1989-07-20 |
Family
ID=11677953
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63007881A Pending JPH01183195A (en) | 1988-01-18 | 1988-01-18 | Manufacture of multilayer printed wiring board device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01183195A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03117881U (en) * | 1990-03-15 | 1991-12-05 | ||
| JPH11126978A (en) * | 1997-10-24 | 1999-05-11 | Kyocera Corp | Multilayered wiring board |
| JP2014072279A (en) * | 2012-09-28 | 2014-04-21 | Dainippon Printing Co Ltd | Manufacturing method of wiring board with components incorporated therein |
| JP2018529231A (en) * | 2015-09-03 | 2018-10-04 | ルミレッズ ホールディング ベーフェー | Method for manufacturing an LED device |
-
1988
- 1988-01-18 JP JP63007881A patent/JPH01183195A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03117881U (en) * | 1990-03-15 | 1991-12-05 | ||
| JPH11126978A (en) * | 1997-10-24 | 1999-05-11 | Kyocera Corp | Multilayered wiring board |
| JP2014072279A (en) * | 2012-09-28 | 2014-04-21 | Dainippon Printing Co Ltd | Manufacturing method of wiring board with components incorporated therein |
| JP2018529231A (en) * | 2015-09-03 | 2018-10-04 | ルミレッズ ホールディング ベーフェー | Method for manufacturing an LED device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5530288A (en) | Passive interposer including at least one passive electronic component | |
| US7473988B2 (en) | Wiring board construction including embedded ceramic capacitors(s) | |
| US6333857B1 (en) | Printing wiring board, core substrate, and method for fabricating the core substrate | |
| US6930257B1 (en) | Integrated circuit substrate having laminated laser-embedded circuit layers | |
| US8381394B2 (en) | Circuit board with embedded component and method of manufacturing same | |
| EP0526133B1 (en) | Polyimide multilayer wiring substrate and method for manufacturing the same | |
| JP2001320171A (en) | Multilayer wiring board and semiconductor device | |
| JPH0697225A (en) | Semiconductor device | |
| JP2001111232A (en) | Electronic component mounting multilayer board and manufacturing method thereof | |
| JPS5819160B2 (en) | multilayer printed circuit board | |
| US8826531B1 (en) | Method for making an integrated circuit substrate having laminated laser-embedded circuit layers | |
| JPH05343855A (en) | Multilayer printed wiring board and manufacture thereof | |
| JP2007524254A (en) | Interconnect structure and method for connecting embedded signal lines to electrical devices | |
| US8546186B2 (en) | Planar interconnect structure for hybrid circuits | |
| KR100972431B1 (en) | Embedded printed circuit board and manufacturing method thereof | |
| JPH01256161A (en) | Printed wiring board device | |
| JP2529987B2 (en) | Method for manufacturing multilayer printed wiring board device | |
| JPH01183195A (en) | Manufacture of multilayer printed wiring board device | |
| JPH01175297A (en) | Multilayer printed circuit board device | |
| JPH01175296A (en) | Multilayer printed circuit board device | |
| JP3179572B2 (en) | Multilayer printed wiring board and method of manufacturing the same | |
| JP2787230B2 (en) | Substrate for mounting electronic components | |
| CA1311854C (en) | Apparatus and method for high density interconnection substrates using stacked modules | |
| US20020166697A1 (en) | Circuit board construction | |
| JP2500404B2 (en) | Circuit board mounting structure |