JPH09275176A - Plastic molded type semiconductor device - Google Patents

Plastic molded type semiconductor device

Info

Publication number
JPH09275176A
JPH09275176A JP8082200A JP8220096A JPH09275176A JP H09275176 A JPH09275176 A JP H09275176A JP 8082200 A JP8082200 A JP 8082200A JP 8220096 A JP8220096 A JP 8220096A JP H09275176 A JPH09275176 A JP H09275176A
Authority
JP
Japan
Prior art keywords
die pad
resin
semiconductor chip
semiconductor device
palladium layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8082200A
Other languages
Japanese (ja)
Inventor
Tadashi Ebihara
正 海老原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP8082200A priority Critical patent/JPH09275176A/en
Publication of JPH09275176A publication Critical patent/JPH09275176A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve resistance to crack of a package, by forming a palladium layer on the surface opposite to the surface of a die pad on which a semiconductor chip is mounded and fixed. SOLUTION: A palladium layer is formed on the surface opposite to the surface of a die pad on which a semiconductor chip is mounted and fixed. That is, as to a means for turning a rear surface 4a to the first palladium layer, a metal 6c is previously peeled from the rear surface 4a of a die pad 4 by using, e.g. aqua regia, in a process for forming the metal 6c on the first palladium layer, out of a process for forming a processing film 6 on a lead frame. Further, after the metal 6c is formed, a second palladium layer 7 is formed on the metal 6c formed on the rear surface 4a of the die pad 4. As a result, adhesion between the palladium layer on the surface opposite to the surface of the die pad on which the semiconductor chip is mounted and fixed and epoxy resin, e.g. used as sealing resin is improved, and stress applied to the surface opposite to the surface of the die pad on which the semiconductor chip is mounted and fixed can be dispersed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は樹脂封止型半導体装
置に関し、さらに詳しくは、パッケージの耐クラック性
を向上させる樹脂封止型半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated semiconductor device, and more particularly to a resin-encapsulated semiconductor device that improves the crack resistance of a package.

【０００２】[0002]

【従来の技術】近年、樹脂封止型半導体装置のパッケー
ジの小型化および薄型化が顕著である。しかしながら、
薄型パッケージの進展に伴い半導体チップおよびダイパ
ッドを樹脂封止したパッケージにクラックが生じ、樹脂
封止型半導体装置の耐久性や信頼性を損なう虞が大とな
っている。すなわち、樹脂封止型半導体装置の封止樹脂
に供されるエポキシ樹脂と、ダイパッドを含むリードフ
レームの銅材との熱膨張率は大きく異なるものとなって
いる。この為、樹脂封止型半導体装置を基板等に実装す
る際のリフローにより２５０℃前後の雰囲気に晒される
等、温度差の生じる熱履歴を受けると、半導体チップを
載置固定しているダイパッド周辺に応力集中が起こる。
特に、ダイパッドの半導体チップを載置固定する面の反
対面側のパッケージは薄厚であり、ダイパッド周辺に応
力集中が起こるとこの部分にクラックが生じ易い傾向に
ある。パッケージに生じたクラックは、外観的に好まし
くないばかりでなく、パッケージ本来の防湿機能や封止
機能を失わせ、樹脂封止型半導体装置の信頼性を著しく
低下させるものである。2. Description of the Related Art In recent years, miniaturization and thinning of packages of resin-sealed semiconductor devices have been remarkable. However,
With the progress of thin packages, cracks are generated in a package in which a semiconductor chip and a die pad are resin-sealed, and the durability and reliability of the resin-sealed semiconductor device are likely to be impaired. That is, the thermal expansion coefficient of the epoxy resin used as the sealing resin of the resin-sealed semiconductor device and the copper material of the lead frame including the die pad are greatly different. Therefore, when a thermal history that causes a temperature difference such as exposure to an atmosphere of about 250 ° C. due to reflow when mounting a resin-sealed semiconductor device on a substrate or the like, the periphery of the die pad on which the semiconductor chip is mounted and fixed is received. Stress concentration occurs in the.
In particular, the package on the side of the die pad opposite to the side on which the semiconductor chip is mounted and fixed is thin, and when stress concentration occurs around the die pad, cracks tend to occur in this portion. The cracks generated in the package are not only unfavorable in appearance, but also lose the moisture-proof function and the sealing function inherent to the package, and significantly reduce the reliability of the resin-sealed semiconductor device.

【０００３】図２（ａ）は、樹脂封止型半導体装置の概
略側面断面図であり、同図（ｂ）は同図（ａ）における
Ａ部の概略拡大図である。一般に樹脂封止型半導体装置
の概略構成は、半導体チップ１がダイパッド４上に銀ペ
ースト等の導電性接着剤により載置固定され、半導体チ
ップ１上に形成された電極とリード２とが金線等のワイ
ヤー５で電気的に接続され、更に半導体チップ１、ダイ
パッド４及びリード２の一部を樹脂封止したパッケージ
３が形成され、パッケージ３から突出しているリード２
はガルウイング形状に曲げ加工されたものとなってい
る。FIG. 2A is a schematic side sectional view of a resin-sealed semiconductor device, and FIG. 2B is a schematic enlarged view of a portion A in FIG. 2A. Generally, the general structure of a resin-sealed semiconductor device is that the semiconductor chip 1 is mounted and fixed on the die pad 4 with a conductive adhesive such as silver paste, and the electrodes formed on the semiconductor chip 1 and the leads 2 are gold wires. And the like, which are electrically connected by a wire 5 such as a semiconductor chip 1, a die pad 4, and a portion of the lead 2 are resin-sealed to form a package 3. The lead 2 protruding from the package 3 is formed.
Is bent into a gull wing shape.

【０００４】ところで、樹脂封止型半導体装置に供せら
れるリードフレームには表面処理により三層から成る処
理膜６が形成されている。この三層は、リードフレーム
の素材２ａ上にニッケル層６ａ、ニッケル層６ａ上に第
一のパラジウム層６ｂ、更に第一のパラジウム層６ｂ上
に金層６ｃから形成されている。この金層６ｃの厚さは
３０〜１００×１０-10 ｍであり、半導体チップ１との
接合強度の向上及びリード２部におけるハンダ接合性の
向上の為に施されている。しかしながら、この金層６ｃ
を施したリードフレームは、上述した半導体チップ１と
の接合強度の向上及びハンダ接合性を向上させる効果は
あるものの、エポキシ樹脂等の封止樹脂との密着性が小
であり、上述したようなパッケージ３の耐クラック性に
問題があった。図２（ａ）は、樹脂封止型半導体装置が
温度差の生じる熱履歴を受け、パッケージ３にクラック
８が生じた事例を示したものである。このような事例
は、特にパッケージが薄型化および薄型化するほど顕著
なものとなる傾向にある。By the way, a lead frame used for a resin-encapsulated semiconductor device is provided with a treatment film 6 consisting of three layers by surface treatment. The three layers are formed of a nickel layer 6a on the lead frame material 2a, a first palladium layer 6b on the nickel layer 6a, and a gold layer 6c on the first palladium layer 6b. The gold layer 6c has a thickness of 30 to 100 × 10 −10 m, and is applied to improve the bonding strength with the semiconductor chip 1 and the solder bondability in the lead 2 portion. However, this gold layer 6c
Although the lead frame having the effect of improving the bonding strength with the semiconductor chip 1 and the solder bonding property described above has low adhesion with the sealing resin such as epoxy resin, There was a problem in the crack resistance of the package 3. FIG. 2A shows an example in which the resin-sealed semiconductor device receives a thermal history of a temperature difference and a crack 8 is generated in the package 3. Such cases tend to become more remarkable as the package becomes thinner and thinner.

【０００５】[0005]

【発明が解決しようとする課題】本発明の課題は、パッ
ケージの耐クラック性を向上させ、信頼性を有する樹脂
封止型半導体装置を提供することである。SUMMARY OF THE INVENTION An object of the present invention is to provide a resin-encapsulated semiconductor device having improved package crack resistance and reliability.

【０００６】[0006]

【課題を解決するための手段】上記課題を解決するため
に、本発明の樹脂封止型半導体装置では、半導体チップ
を載置固定するダイパッドと、半導体チップおよびダイ
パッドを樹脂封止したパッケージと、パッケージから突
出するリードとを有する樹脂封止型半導体装置におい
て、ダイパッドの半導体チップを載置固定する面の反対
面に、パラジウム層が形成されているものであることを
特徴とする。In order to solve the above problems, in a resin-sealed semiconductor device of the present invention, a die pad for mounting and fixing a semiconductor chip, and a package in which the semiconductor chip and the die pad are resin-sealed, A resin-sealed semiconductor device having a lead protruding from a package is characterized in that a palladium layer is formed on a surface of a die pad opposite to a surface on which a semiconductor chip is mounted and fixed.

【０００７】上述した手段による作用としては、ダイパ
ッドの半導体チップを載置固定する面の反対面のパラジ
ウム層と、封止樹脂に供されるエポキシ樹脂等との密着
性が向上し、ダイパッドの半導体チップを載置固定する
面の反対面に作用する応力を分散させることができるこ
とである。The action of the above means is that the adhesiveness between the palladium layer on the surface of the die pad opposite to the surface on which the semiconductor chip is mounted and fixed and the epoxy resin or the like used as the sealing resin is improved, and the semiconductor of the die pad is improved. That is, it is possible to disperse the stress acting on the surface opposite to the surface on which the chip is mounted and fixed.

【０００８】[0008]

【発明の実施の形態】以下、本発明の実施の形態例につ
いて、図１（ａ）〜（ｂ）を参照して説明する。なお、
図中の構成要素で従来の技術と同様の構造を成している
ものについては同一の参照符号を付すものとする。ま
た、樹脂封止型半導体装置の概略構成については、従来
の技術で図２（ａ）を参照し説明した事例と同様である
にので省略する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIGS. In addition,
Constituent elements in the figure that have the same structure as that of the conventional technique are designated by the same reference numerals. The schematic configuration of the resin-encapsulated semiconductor device is the same as the case described with reference to FIG.

【０００９】図１（ａ）〜（ｂ）は、従来の技術におけ
る図２（ｂ）と同様、図２（ａ）におけるＡ部の概略拡
大図である。本発明は、従来の技術において図２を参照
して説明した事例と同様に、樹脂封止型半導体装置に供
されるリードフレームの素材２ａ上にニッケル層６ａ、
ニッケル層６ａ上に第一のパラジウム層６ｂ、更に第一
のパラジウム層６ｂ上に金層６ｃからなる処理膜６が形
成されているが、図１（ａ）に示したように、ダイパッ
ド４の裏面４ａの表面が金層６ｃでなく、第一のパラジ
ウム層６ｂとなっている点が異なるものである。1 (a) and 1 (b) are schematic enlarged views of a portion A in FIG. 2 (a), similar to FIG. 2 (b) in the prior art. The present invention is similar to the case described with reference to FIG. 2 in the prior art, in which the nickel layer 6a is formed on the material 2a of the lead frame used for the resin-sealed semiconductor device.
The treatment film 6 including the first palladium layer 6b on the nickel layer 6a and the gold layer 6c on the first palladium layer 6b is formed. As shown in FIG. The difference is that the surface of the back surface 4a is not the gold layer 6c but the first palladium layer 6b.

【００１０】裏面４ａの表面を第一のパラジウム層６ｂ
とする手段としては、リードフレームに処理膜６を形成
する工程の内、第一のパラジウム層６ｂ上に金層６ｃを
形成する工程において、予めダイパッド４の裏面４ａに
ポリイミド等の絶縁物を形成してマスキングする、また
は金層６ｃの形成後、ダイパッド４の裏面４ａを王水等
で金層６ｃを剥離する、さらにまた図１（ｂ）に示した
ように、金層６ｃの形成後、ダイパッド４の裏面４ａに
形成された金層６ｃ上に第二のパラジウム層７を形成す
る等がある。そして、これ等は何れも容易にダイパッド
４の裏面４ａにパラジウム層を形成することができる。The surface of the back surface 4a is covered with the first palladium layer 6b.
As a means for forming the treated film 6, in the step of forming the gold layer 6c on the first palladium layer 6b in the step of forming the treatment film 6 on the lead frame, an insulator such as polyimide is previously formed on the back surface 4a of the die pad 4. And masking, or after forming the gold layer 6c, the back surface 4a of the die pad 4 is peeled off the gold layer 6c with aqua regia, etc. Further, as shown in FIG. 1B, after forming the gold layer 6c, For example, the second palladium layer 7 is formed on the gold layer 6c formed on the back surface 4a of the die pad 4. Any of these can easily form a palladium layer on the back surface 4a of the die pad 4.

【００１１】ダイパッド４の裏面４ａ表面にある第一の
Ｐｄ層６ｂあるいは第二のＰｄ層７とパッケージ３に供
されるエポキシ樹脂等の合成樹脂とは密着性は、金層６
ｃとエポキシ樹脂等の合成樹脂との密着性よりも向上す
るので、半導体チップ１を載置固定しているダイパッド
４の裏面４ａに作用する応力集中を分散させることがで
きる。The adhesion between the first Pd layer 6b or the second Pd layer 7 on the back surface 4a of the die pad 4 and the synthetic resin such as the epoxy resin used for the package 3 is determined by the gold layer 6
Since the adhesion between c and the synthetic resin such as epoxy resin is improved, the stress concentration acting on the back surface 4a of the die pad 4 on which the semiconductor chip 1 is mounted and fixed can be dispersed.

【００１２】[0012]

【発明の効果】本発明の樹脂封止型半導体装置によれ
ば、特にパッケージが薄肉となるダイパッドの裏面に作
用する応力を分散させることができるので、パッケージ
の耐クラック性が向上する。従って、信頼性を有する樹
脂封止型半導体装置とすることができる。According to the resin-encapsulated semiconductor device of the present invention, the stress acting on the back surface of the die pad, in which the package is thin, can be dispersed, so that the crack resistance of the package is improved. Therefore, the resin-encapsulated semiconductor device having reliability can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図１】 本発明の実施の形態例を示し、（ａ）〜
（ｂ）は、図２（ａ）におけるＡ部の概略拡大図であ
る。FIG. 1 shows an embodiment of the present invention, in which (a)-
2B is a schematic enlarged view of a portion A in FIG.

【図２】 従来例を示し、（ａ）は、樹脂封止型半導体
装置の概略側面断面図であり、（ｂ）は（ａ）における
Ａ部の概略拡大図である。2A shows a conventional example, FIG. 2A is a schematic side sectional view of a resin-encapsulated semiconductor device, and FIG. 2B is a schematic enlarged view of a portion A in FIG.

【符号の説明】[Explanation of symbols]

１…半導体チップ、２…リード、２ａ…素材、３…パッ
ケージ、４…ダイパッド、４ａ…裏面、５…ワイヤー、
６…処理膜、６ａ…ニッケル層、６ｂ…第一のパラジウ
ム層、６ｃ…金層、７…第二のパラジウム層、８…クラ
ック1 ... Semiconductor chip, 2 ... Lead, 2a ... Material, 3 ... Package, 4 ... Die pad, 4a ... Back surface, 5 ... Wire,
6 ... Treatment film, 6a ... Nickel layer, 6b ... First palladium layer, 6c ... Gold layer, 7 ... Second palladium layer, 8 ... Crack

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップと、 前記半導体チップを載置固定するダイパッドと、 前記半導体チップおよび前記ダイパッドを樹脂封止した
パッケージと、 前記パッケージから突出するリードとを有する樹脂封止
型半導体装置において、 前記ダイパッドの前記半導体チップを載置固定する面の
反対面に、パラジウム層が形成されているものであるこ
とを特徴とする樹脂封止型半導体装置。1. A resin-sealed semiconductor device having a semiconductor chip, a die pad on which the semiconductor chip is mounted and fixed, a package in which the semiconductor chip and the die pad are resin-sealed, and leads protruding from the package. A resin-sealed semiconductor device, wherein a palladium layer is formed on a surface of the die pad opposite to a surface on which the semiconductor chip is mounted and fixed.
JP8082200A 1996-04-04 1996-04-04 Plastic molded type semiconductor device Pending JPH09275176A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8082200A JPH09275176A (en) 1996-04-04 1996-04-04 Plastic molded type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8082200A JPH09275176A (en) 1996-04-04 1996-04-04 Plastic molded type semiconductor device

Publications (1)

Publication Number Publication Date
JPH09275176A true JPH09275176A (en) 1997-10-21

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP8082200A Pending JPH09275176A (en) 1996-04-04 1996-04-04 Plastic molded type semiconductor device

Country Status (1)

Country Link
JP (1) JPH09275176A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000223634A (en) * 1999-01-28 2000-08-11 Hitachi Ltd Semiconductor device
JP2017168617A (en) * 2016-03-16 2017-09-21 Ｓｈマテリアル株式会社 Lead frame, semiconductor device, and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000223634A (en) * 1999-01-28 2000-08-11 Hitachi Ltd Semiconductor device
JP2017168617A (en) * 2016-03-16 2017-09-21 Ｓｈマテリアル株式会社 Lead frame, semiconductor device, and manufacturing method thereof

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