JPH06291223A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06291223A JPH06291223A JP8100293A JP8100293A JPH06291223A JP H06291223 A JPH06291223 A JP H06291223A JP 8100293 A JP8100293 A JP 8100293A JP 8100293 A JP8100293 A JP 8100293A JP H06291223 A JPH06291223 A JP H06291223A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- container
- semiconductor
- control
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Die Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、例えばバイポーラトラ
ンジスタの表面部にＭＯＳ構造を有し、電圧駆動のスイ
ッチング素子として用いられる絶縁ゲート型バイポーラ
トランジスタ(以下ＩＧＢＴと記す) 素子のように一主
面上に主電極と制御電極を有する半導体素体の１個ある
いは複数個を容器の中に収容した半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a main surface such as an insulated gate bipolar transistor (hereinafter referred to as IGBT) element having a MOS structure on the surface of a bipolar transistor and used as a voltage-driven switching element. The present invention relates to a semiconductor device in which one or more semiconductor elements having a main electrode and a control electrode are housed in a container.
【０００２】[0002]
【従来の技術】近年スイッチング素子として伝導度変調
を利用したＭＯＳＦＥＴ、いわゆるＩＧＢＴが注目され
ている。ＩＧＢＴはＭＯＳＦＥＴ同様に入力インピーダ
ンスが高く、またバイポーラトランジスタと同様にオン
抵抗が低くできる。図２は、ＩＧＢＴの基本構造を示
す。この構造においては、ｎ- 層11の表面層内にｐベー
ス領域12、さらにその表面層内にｎ+ エミッタ領域13と
がそれぞれ選択的に形成されている。ｐベース領域12の
ｎ- 層11とｎ+ エミッタ領域13ではさまれた表面部分は
チャネル領域14となる部分で、その上にゲート絶縁膜15
を介して、ゲート電極16が形成されている。ｎ+ エミッ
タ領域13の一部にはｐベース領域12と共通にエミッタ電
極17が接触している。エミッタ電極17はゲート電極16と
絶縁膜18で絶縁されている。ｎ- 層11の他側には高不純
物濃度のｎバッファ層19が設けられ、さらにｎ+ バッフ
ァ層19の下層ｐ+ コレクタ層20が形成されている。そし
て、ｐ + コレクタ層20にはコレクタ電極21が接触してい
る。2. Description of the Related Art In recent years, conductivity modulation as a switching element
Attention has been paid to MOSFETs using so-called IGBTs
ing. Like the MOSFET, the IGBT has an input impedance
High resistance, and on like a bipolar transistor
Resistance can be lowered. Figure 2 shows the basic structure of the IGBT.
You In this structure, n-In the surface layer of layer 11
Area 12 and n in its surface layer+With emitter region 13
Are selectively formed. p base region 12
n-Layers 11 and n+The surface part sandwiched by the emitter region 13 is
The gate insulating film 15 is formed on the portion to be the channel region 14.
The gate electrode 16 is formed via the. n+Emi
The emitter region 13 has a common emitter electrode in common with the p base region 12.
Pole 17 is touching. The emitter electrode 17 and the gate electrode 16
It is insulated by the insulating film 18. n-High impurity on the other side of layer 11
An n buffer layer 19 having a physical concentration is provided, and n+Buff
Lower layer p+A collector layer 20 is formed. That
, P +The collector electrode 21 is in contact with the collector layer 20.
It
【０００３】このようなＩＧＢＴでは、エミッタ電極17
を接地し、ゲート電極16に電圧を印加することにより、
ｎ+ エミッタ領域13からチャネル領域14を通ってｎ- 層
11に電子電流が注入される。ｎ- 層11に注入された電子
電流がｎ+ バッファ層19に達すると、ｎ+ バッファ層19
とｐ+ コレクタ層20によるｎ+ ／ｐ+ のビルトイン電圧
を電子を蓄積させることで回復するので、ｐ+ コレクタ
層20への電子の注入が起こり、それによってｐ+ コレク
タ層20からｎ+ バッファ層19およびｎ- 層11への正孔の
注入がおこり、その結果ｎ+ バッファ層19およびｎ- 層
11において伝導度変調がおこる。ｎ- 層11に注入された
正孔電流は、ｐベース領域12のｎ+ エミッタ領域13直下
を通りエミッタ電極17へ抜ける。エミッタ電極17はｐベ
ース領域12とｎ+ エミッタ領域13を短絡しているので、
ｐ+ コレクタ層20、ｎ+ バッファ層19およびｎ- 層11、
ｐベース領域12、ｎ+ エミッタ領域13からなるｐｎｐｎ
構造のサイリスタ動作を阻止し、ゲート・エミッタ間電
位をゼロにすることで素子をターンオフすることができ
る。In such an IGBT, the emitter electrode 17
By grounding and applying a voltage to the gate electrode 16,
from n + emitter region 13 through the channel region 14 n - layer
An electron current is injected into 11. n - the electron current injected into the layer 11 reaches the n + buffer layer 19, n + buffer layer 19
Since recovery be accumulated electrons of n + / p + built-in voltage of by the p + collector layer 20 and, occur electron injection into the p + collector layer 20, n + buffer whereby the p + collector layer 20 Holes are injected into the layer 19 and the n − layer 11, resulting in the n + buffer layer 19 and the n − layer.
Conductivity modulation occurs at 11. The hole current injected into the n − layer 11 passes under the n + emitter region 13 of the p base region 12 and escapes to the emitter electrode 17. Since the emitter electrode 17 short-circuits the p base region 12 and the n + emitter region 13,
p + collector layer 20, n + buffer layer 19 and n − layer 11,
pnpn consisting of p base region 12 and n + emitter region 13
The device can be turned off by blocking the thyristor operation of the structure and reducing the gate-emitter potential to zero.
【０００４】このようなＩＧＢＴの電流容量を増大させ
るには、図３に示すような基本構造を一つのシリコン素
体に複数個形成する。この場合、複数のエミッタ電極17
およびコレクタ電極20はそれぞれ連結されて一体とさ
れ、ゲート電極16はゲートリードを介して相互に接続さ
れる。あるいは一つの容器に複数個のＩＧＢＴシリコン
素体を収容し、並列接続する。In order to increase the current capacity of such an IGBT, a plurality of basic structures as shown in FIG. 3 are formed in one silicon body. In this case, multiple emitter electrodes 17
The collector electrode 20 and the collector electrode 20 are connected and integrated, and the gate electrode 16 is connected to each other through a gate lead. Alternatively, a plurality of IGBT silicon bodies are housed in one container and connected in parallel.
【０００５】[0005]
【発明が解決しようとする課題】一般の電力用素子でそ
うであるように、ＩＧＢＴでも導通時にシリコン素体内
で発生する熱を放散して素体温度を一定温度以下に抑え
ることが重要である。コレクタ電極21を支持板にろう付
けすれば、その支持板を介して容易に放熱できるが、エ
ミッタ電極17への通電をアルミニウム導線をボンディン
グして行う場合には、素体上面からの放熱は期待できな
い。また、アルミニウム導線の持つインダクタンスによ
って周波数の高い分野への適用が困難となってくる。As is the case with general power devices, it is important to dissipate the heat generated in the silicon body during conduction even in the IGBT to keep the body temperature below a certain temperature. . If the collector electrode 21 is brazed to the support plate, heat can be easily dissipated through the support plate.However, when the emitter electrode 17 is energized by bonding an aluminum conductor wire, heat dissipation from the upper surface of the element body is expected. Can not. In addition, the inductance of the aluminum conductor makes it difficult to apply it to a field having a high frequency.
【０００６】本発明の目的は、一主面上に主電極および
制御電極を有する半導体素体の上下両面から放熱するこ
とにより電流容量を増大でき、さらに内部インダクタン
スの小さい半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device which can increase the current capacity by radiating heat from the upper and lower surfaces of a semiconductor element body having a main electrode and a control electrode on one main surface and which has a small internal inductance. is there.
【０００７】[0007]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明は、一主面上に主電極および制御電極を有
する半導体素体の１個あるいは複数個が一つの容器に収
容され、複数の制御電極が共通の制御端子に接続される
半導体装置において、半導体素体の両主面にそれぞれ存
在する主電極に半導体材料に熱膨脹係数の近似した金属
材料よりなる電極体が接合され、電極体の反半導体素体
側の面が容器の端子板に対向するか、あるいは反半導体
素体側で容器外面に露出し、各制御電極が容器の絶縁性
側壁を貫通する制御端子に接続される共通配線と接続さ
れたものとする。そして、それぞれ冷却手段を備えた接
触体が容器両面の端子板あるいは露出する電極体に加圧
して使用されることが有効である。また、制御電極のう
ちの一部と共通配線との接続配線が中間で除去されたこ
と、制御電極が導線によって共通配線と接続されるか、
あるいは共通配線が２枚の絶縁板の間にはさまれ、一方
の絶縁板の一面に共通配線と接続される複数の突出電極
が露出し、その突出電極が各制御電極の一部分にそれぞ
れ接合されことが有効である。さらに、制御電極と半導
体素体の同一主面上に存在する主電極に接合された電極
体の断面積が制御電極と制御端子との間の接続導体より
半導体素体から遠い側において大きくされたこと、その
場合電極体の断面積が半導体素体主面上の制御電極と制
御端子との間の接続導体の上方を避けて大きくされたこ
と、制御端子の容器外にあって先端に近い部分が可撓性
であること、そのために制御端子の容器に近接した部分
が波状に形成されたこと、あるいは制御端子の先端がＵ
字状に分岐されたことが有効である。In order to achieve the above object, the present invention provides one container in which one or a plurality of semiconductor elements having a main electrode and a control electrode on one main surface are housed in one container. In a semiconductor device in which a plurality of control electrodes are connected to a common control terminal, an electrode body made of a metal material having a thermal expansion coefficient close to that of the semiconductor material is bonded to the main electrodes respectively present on both main surfaces of the semiconductor element body, The surface of the electrode body on the anti-semiconductor body side faces the terminal plate of the container, or is exposed on the outer surface of the container on the anti-semiconductor body side, and each control electrode is connected to the control terminal penetrating the insulating side wall of the container. It shall be connected to the wiring. Then, it is effective that the contact bodies each equipped with a cooling means are pressed against the terminal plates on both sides of the container or the exposed electrode bodies to be used. Also, the connection wiring between a part of the control electrode and the common wiring is removed in the middle, whether the control electrode is connected to the common wiring by a conductive wire,
Alternatively, the common wiring may be sandwiched between two insulating plates, a plurality of protruding electrodes connected to the common wiring may be exposed on one surface of one insulating plate, and the protruding electrodes may be bonded to a part of each control electrode. It is valid. Furthermore, the cross-sectional area of the electrode body joined to the main electrode existing on the same main surface of the control electrode and the semiconductor element body is made larger on the side farther from the semiconductor element body than the connecting conductor between the control electrode and the control terminal. In that case, the cross-sectional area of the electrode body was enlarged to avoid above the connecting conductor between the control electrode and the control terminal on the main surface of the semiconductor element body, and the portion outside the container of the control terminal near the tip. Is flexible, and therefore, the portion of the control terminal close to the container is formed in a wavy shape, or the tip of the control terminal is U-shaped.
It is effective to have a branched shape.
【０００８】[0008]
【作用】半導体素体の両面に接合された電極体を直接容
器外面に露出させるか、あるいは容器の端子板内面に対
向させることにより、接触体を容器外面に露出する電極
体あるいは端子板に対して加圧すれば、半導体素体に発
生する熱は、電極体から直接あるいは端子板を介して接
触体に伝搬され、半導体装置の電流容量を増大させるこ
とができる。そして、主電極の接続に導線のボンディン
グによる接続を用いないので、内部インダクタンスが小
さくなる。さらに、電極体の断面積を半導体素体から遠
い側で大きくすることにより、放熱を向上させることが
できる。また、制御電極の制御端子と接続する共通配線
を介しての接続を、導線のボンディングによって行うこ
ともできるが、内部に共通配線を有し各制御電極の一部
に接合する突出電極のみが露出する両面絶縁板の接触基
板を用いることにより、ボンディング導線のためのスペ
ースが節減され、容器の高さを低くすることができる。
さらに、不良ユニットあるいは素子のゲート配線をしゃ
断してリペアすることも容易であり、また容器外に引き
出される制御端子の先端部分を可撓性にすることによ
り、制御端子の外部接続の際に容器に近接した部分での
応力による支障が生ずることがない。The electrode body bonded to both sides of the semiconductor body is exposed directly to the outer surface of the container or is made to face the inner surface of the terminal plate of the container, so that the contact body is exposed to the outer surface of the container. By applying pressure, the heat generated in the semiconductor element body is propagated from the electrode body directly or through the terminal plate to the contact body, and the current capacity of the semiconductor device can be increased. Further, since the connection by the bonding of the conductive wire is not used for the connection of the main electrodes, the internal inductance becomes small. Further, heat dissipation can be improved by increasing the cross-sectional area of the electrode body on the side far from the semiconductor element body. Further, although the connection through the common wire connected to the control terminal of the control electrode can be performed by bonding the conductive wire, only the protruding electrode which has the common wire inside and is joined to a part of each control electrode is exposed. By using the contact substrate of the double-sided insulating plate, the space for the bonding wire can be saved and the height of the container can be reduced.
Furthermore, it is easy to cut off the gate wiring of the defective unit or element to repair it, and the tip of the control terminal that is pulled out of the container is made flexible so that the container can be connected when the control terminal is externally connected. There will be no trouble due to the stress in the part close to.
【０００９】[0009]
【実施例】図１(a) は本発明の一実施例のＩＧＢＴ素子
を示し、図１(b) はそのＩＧＢＴチップを示し、図３と
共通の部分には同一の符号が付されている。Siからなる
ＩＧＢＴチップ１の下面のコレクタ電極21には、Siとほ
ぼ熱膨脹係数の等しいモリブデンあるいはタングステン
からなるコレクタ電極体２が全面に高温はんだ等でろう
付けされるか、あるいは融着されている。また、エミッ
タ電極17にはチップ中心部でエミッタ電極体３が同様に
接合されている。このチップ１を底板４とアルミナセラ
ミックスの外枠５からなる容器に入れる。チップ１の下
面を熱伝導率の高いCuなどからなる底板４にはんだによ
りろう付けしてもよい。外枠５はＬ字形断面を有し、そ
の段部上に内部ゲートリード６が固定され、このリード
から外枠５を貫通するゲート端子７から引出されてい
る。そして、チップ１上のゲート電極に接続されたゲー
トパッド２２とゲートリード６をAl線８のボンディング
により接続する。このあと、不活性ガス中で蓋板９を外
枠５の上端面とろう付け、融着あるいは接着によって接
合し、密封する。なお、外枠には、アルミナの代わり
に、ムライトやステアタイトあるいは窒化アルミニウム
を用いることができる。また底板４、蓋板６との接合が
低温で行われる場合には、樹脂も用いることができる。
このほか、ＩＧＢＴチップ１の耐圧維持および保護の目
的により、素体１の周辺の容器内にシリコーン樹脂を充
填してもよい。このようにして34mm×34mm×８mmのコン
パクトな寸法のＩＧＢＴ素子が得られる。1 (a) shows an IGBT element according to an embodiment of the present invention, FIG. 1 (b) shows its IGBT chip, and the same parts as those in FIG. 3 are designated by the same reference numerals. . On the lower surface of the IGBT chip 1 made of Si, a collector electrode body 2 made of molybdenum or tungsten whose thermal expansion coefficient is almost the same as that of Si is brazed or fused by high temperature solder or the like. . Further, the emitter electrode body 3 is similarly joined to the emitter electrode 17 at the center of the chip. The chip 1 is placed in a container composed of a bottom plate 4 and an alumina ceramic outer frame 5. The lower surface of the chip 1 may be brazed to the bottom plate 4 made of Cu or the like having high thermal conductivity by soldering. The outer frame 5 has an L-shaped cross section, an internal gate lead 6 is fixed on the stepped portion, and is drawn out from the gate terminal 7 penetrating the outer frame 5 from this lead. Then, the gate pad 22 connected to the gate electrode on the chip 1 and the gate lead 6 are connected by the bonding of the Al wire 8. After that, the lid plate 9 is brazed to the upper end surface of the outer frame 5 in an inert gas, joined by fusion or adhesion, and sealed. Instead of alumina, mullite, steatite or aluminum nitride can be used for the outer frame. Further, when the joining with the bottom plate 4 and the lid plate 6 is performed at a low temperature, resin can also be used.
In addition, for the purpose of maintaining the pressure resistance and protecting the IGBT chip 1, a silicone resin may be filled in a container around the element body 1. In this way, an IGBT element having a compact size of 34 mm × 34 mm × 8 mm can be obtained.
【００１０】図３(a) 、(b) 、(c) および図４に示す本
発明の別の実施例のＩＧＢＴ素子では、チップ１が図３
(b) のＢ−Ｂ線断面図である図４に示すように８個のユ
ニットパターンに分割されており、各ユニットパターン
に存在するゲート電極16にはそれぞれボンディングパッ
ド22が存在する。そして周囲の外枠５の段部上のゲート
リード６とAl線８のボンディングにより接続される。ゲ
ートの接続後、底板４と外枠５からなる容器にゲル23、
樹脂24などの充填剤が封入され、エミッタ電極体３が樹
脂24の面より突出している。なお、図４に示すような複
数のＩＧＢＴユニットのうちに不良ユニットがある場
合、そのユニットに対するAl線８のボンディングをしな
いか、あるいは切断することによりリペアすることがで
きる。In the IGBT device of another embodiment of the present invention shown in FIGS. 3 (a), 3 (b), 3 (c) and FIG.
As shown in FIG. 4 which is a sectional view taken along the line BB of FIG. 4B, it is divided into eight unit patterns, and bonding pads 22 are present on the gate electrodes 16 existing in each unit pattern. Then, the gate lead 6 on the stepped portion of the surrounding outer frame 5 is connected to the Al wire 8 by bonding. After connecting the gate, put the gel 23 in the container consisting of the bottom plate 4 and the outer frame 5,
A filler such as resin 24 is enclosed, and the emitter electrode body 3 projects from the surface of the resin 24. If there is a defective unit among the plurality of IGBT units as shown in FIG. 4, it is possible to repair it by not bonding or cutting the Al wire 8 to the unit.
【００１１】図５は図１のＩＧＢＴ素子の複数個を用い
た半導体装置、すなわちＩＧＢＴモジュールを示す。図
において、複数個のＩＧＢＴ素子31が２個の接触体32、
33の間にはさまれ、絶縁ボルト34とナット35により、上
部接触体32が素子31の図１における蓋板９と、下部接触
体33が底板４に加圧接触し、素子31は接触体32、33の間
に固定される。そして、容器の中のエミッタ電極体４と
蓋板９との間、またコレクタ電極体２が底板４とろう付
けされないときにはそれらの間の低抵抗の接触が確保さ
れる。これにより、ＩＧＢＴチップ１に発生する熱は、
エミッタ電極体３、蓋板９、上部接触体32およびコレク
タ電極体２、底板４、下部接触体33の径路を経て伝達さ
れる。接触体32、33は風冷により表面から放熱するので
冷却体を兼ねているが、さらに放熱用フィンを備えた
り、水冷あるいはヒートポンプジャケットを備えること
により冷却効果を上げることも効果的で、これらの方策
により同一電流容量のＩＧＢＴモジュールを複数個のＩ
ＧＢＴチップを一つの容器に収容し、各チップのエミッ
タ電極との接続をボンディングした導線で行う場合に比
して約１／２の大きさにすることができ、低インダクタ
ンスになる。FIG. 5 shows a semiconductor device using a plurality of the IGBT elements shown in FIG. 1, that is, an IGBT module. In the figure, a plurality of IGBT elements 31 are provided with two contact bodies 32,
It is sandwiched between 33, and by the insulating bolt 34 and the nut 35, the upper contact body 32 makes pressure contact with the lid plate 9 of the element 31 in FIG. 1 and the lower contact body 33 with the bottom plate 4, and the element 31 makes contact body. It is fixed between 32 and 33. A low resistance contact is secured between the emitter electrode body 4 and the cover plate 9 in the container, and between the collector electrode body 2 and the bottom plate 4 when they are not brazed. As a result, the heat generated in the IGBT chip 1 is
It is transmitted through the paths of the emitter electrode body 3, the cover plate 9, the upper contact body 32 and the collector electrode body 2, the bottom plate 4, and the lower contact body 33. The contact bodies 32, 33 also serve as a cooling body because they radiate heat from the surface by air cooling, but it is also effective to increase the cooling effect by further providing heat radiation fins, water cooling or a heat pump jacket. Depending on the policy, IGBT modules with the same current capacity can
The GBT chip can be housed in a single container, and the size of the chip can be reduced to about 1/2 of that in the case where the connection with the emitter electrode of each chip is made by a bonded conductive wire, resulting in low inductance.
【００１２】また、図示のように隣接するＩＧＢＴ素子
31のゲート端子７をはんだづけ、圧着またはねじ止めに
より接続することができ、素子内のゲート配線を利用す
ることで、モジュール内部に配線をひき回す必要がなく
なり、一層のモジュールの寸法縮小ができる。図６(a)
、(b) 、(c) に示す本発明の実施例のＩＧＢＴ素子
は、樹脂モジュール型であり、絶縁性外枠６は用いな
い。すなわち、下面にコレクタ電極体２、上面にエミッ
タ電極体３を露出させて樹脂24により封止されている。
そして、ＩＧＢＴチップ１上のゲートパッド22への接続
にはゲート接触基板25が用いられている。ゲート接触気
団25は図７(a) 、(b) に示すように、ゲートリード６
は、それぞれ中央にエミッタ電極３のための貫通孔30を
有する上部絶縁板26と下部絶縁板27の間にはさまれてい
て外部から見えない。両絶縁板26、27にはセラミックあ
るいは高分子材料の板を用いる。そして、下面絶縁板27
からはんだバンプ28が突出している。このはんだバンプ
28がＩＧＢＴチップ１の各ユニットパターンに存在する
ボンディングパッド22と接合される。このようなゲート
接触基板25を用いることにより、素子の高さをAl線８に
よって接続する場合に比して１mm以上薄くすることがで
きた。なお、ゲートリード６から対向する位置でゲート
接触基板25外へゲート端子７が引き出されるが、その根
本部分には波状部分71が形状され、先端部が変形自在に
なっている。Also, as shown in the figure, adjacent IGBT elements
The 31 gate terminals 7 can be connected by soldering, crimping or screwing, and by using the gate wiring in the element, it is not necessary to lay the wiring inside the module, and the size of the module can be further reduced. Figure 6 (a)
, (B) and (c) of the embodiment of the present invention are of the resin module type, and the insulating outer frame 6 is not used. That is, the collector electrode body 2 is exposed on the lower surface and the emitter electrode body 3 is exposed on the upper surface and sealed with the resin 24.
A gate contact substrate 25 is used to connect to the gate pad 22 on the IGBT chip 1. As shown in FIGS. 7 (a) and 7 (b), the gate contact air mass 25 has a gate lead 6
Are sandwiched between an upper insulating plate 26 and a lower insulating plate 27, each of which has a through hole 30 for the emitter electrode 3 in the center and are not visible from the outside. Ceramic plates or polymer plates are used for both insulating plates 26 and 27. Then, the lower surface insulating plate 27
The solder bumps 28 project from the. This solder bump
28 is bonded to the bonding pad 22 existing in each unit pattern of the IGBT chip 1. By using such a gate contact substrate 25, the height of the device can be reduced by 1 mm or more as compared with the case of connecting by the Al wire 8. Although the gate terminal 7 is drawn out of the gate contact substrate 25 at a position facing the gate lead 6, a corrugated portion 71 is formed at the root portion of the gate terminal 7, and the tip portion thereof is deformable.
【００１３】図３に示すＩＧＢＴ素子では、エミッタ電
極体３は、チップ１上のゲート電極にボンディングされ
る導線８との接触をさけるため、長方形にしなければな
らず、コレクタ電極体３に比して面積が小さくなる。そ
のためエミッタ電極側からの放熱量はコレクタ電極側か
らに比してかなり少なかった。図８(a) 、(b) 、(c)に
示す実施例では、ゲート接触基板25を用いる構造でエミ
ッタ電極体３の横断面積がゲート接触基板25上部で大き
くしたものである。この場合、エミッタ電極体３の加工
とチップ１に対する位置合わせが難しくなる反面、エミ
ッタ電極体側への放熱量を増大させることができる。こ
の場合は、ゲート接触基板25を用いているため、エミッ
タ電極体３とボンディング導線との接触の問題はない
が、横断面積がゲート接触基板の上部に限られる。図９
(a) 、(b) 、(c) は、図３の素子のようにゲートボンデ
ィング導線８を用いる場合の実施例を示し、エミッタ電
極体５の横断面積を大きくした上部はゲートボンディン
グ導線８の上方を避けるスリット81を形成した。これに
よって図９(c) に示すようにエミッタ電極体３の面積を
拡大した上部が導線８と接触するおそれがなくなり、厚
さを厚くすることができ、熱抵抗の低減を大きくするこ
とができた。図10に示す実施例では、図９のスリット81
をつないでエミッタ電極体３の平面形状をＩ字状にし
た。図９の実施例にくらべて熱抵抗は増大するが、電極
体の加工は容易になる。In the IGBT element shown in FIG. 3, the emitter electrode body 3 has to be rectangular in order to avoid contact with the conducting wire 8 bonded to the gate electrode on the chip 1, which is smaller than that of the collector electrode body 3. Area becomes smaller. Therefore, the amount of heat radiation from the emitter electrode side was considerably smaller than that from the collector electrode side. In the embodiment shown in FIGS. 8A, 8B and 8C, the gate contact substrate 25 is used and the cross-sectional area of the emitter electrode body 3 is increased above the gate contact substrate 25. In this case, while it is difficult to process the emitter electrode body 3 and align it with the chip 1, it is possible to increase the amount of heat radiation to the emitter electrode body side. In this case, since the gate contact substrate 25 is used, there is no problem of contact between the emitter electrode body 3 and the bonding conductor, but the cross-sectional area is limited to the upper part of the gate contact substrate. Figure 9
3 (a), (b), and (c) show an embodiment in which the gate bonding conductor 8 is used as in the device of FIG. 3, and the upper part where the cross-sectional area of the emitter electrode body 5 is increased is the gate bonding conductor 8. A slit 81 was formed to avoid the upper side. As a result, as shown in FIG. 9 (c), there is no possibility that the upper part of the enlarged area of the emitter electrode body 3 will come into contact with the conductive wire 8, the thickness can be increased, and the reduction of thermal resistance can be increased. It was In the embodiment shown in FIG. 10, the slit 81 of FIG.
The emitter electrode body 3 was formed into an I-shaped plane by connecting. Although the thermal resistance is increased as compared with the embodiment of FIG. 9, the electrode body can be easily processed.
【００１４】図11、図12は、ゲート接触基板25の下部絶
縁板27を除いて示したゲートリード６のパターンの二つ
の例であり、ゲートリード６は各はんだバンプ28から離
れた位置でその外側あるいは内側に環状に形成されてい
る。図13(a) 、(b) 、(c) は、このようなゲート接触基
板を用いたＩＧＢＴ素子でチップに不良ユニットが存在
する場合のリペア方法を示す。図13(a) に示すＩＧＢＴ
チップ１で不良ユニット10が存在する場合、図13(b) 、
(c) に示すように上部絶縁板26から下部絶縁板27に達す
る貫通孔29を明け、その部分のはんだバンプ28を除去し
て、不良ユニット10のゲート電極がゲートリード６に接
続されないようにする。これにより、Al線８を用いてゲ
ートの接続を行う図１あるいは図３、図４の場合のよう
にリペアを行うことができた。11 and 12 are two examples of the pattern of the gate lead 6 shown by removing the lower insulating plate 27 of the gate contact substrate 25. The gate lead 6 is formed at a position apart from each solder bump 28. It is formed annularly on the outside or inside. FIGS. 13 (a), 13 (b) and 13 (c) show a repairing method when a defective unit exists in a chip in an IGBT device using such a gate contact substrate. The IGBT shown in Fig. 13 (a)
If there is a defective unit 10 in the chip 1, Fig. 13 (b),
As shown in (c), a through hole 29 reaching from the upper insulating plate 26 to the lower insulating plate 27 is opened, and the solder bump 28 in that portion is removed so that the gate electrode of the defective unit 10 is not connected to the gate lead 6. To do. As a result, the repair could be carried out as in the case of FIG. 1 or FIGS. 3 and 4 in which the gate is connected using the Al wire 8.
【００１５】以上の実施例では、一つのＩＧＢＴ素子の
ＩＧＢＴチップが１個の場合であるが、１個または複数
個のゲートを有するＩＧＢＴチップを複数個封入したマ
イクロスタックにおいても同様な両面冷却構造にするこ
とができ、不良チップの分離も同様にできる。図14は、
本発明によるＩＧＢＴ素子31の複数個からなるモジュー
ルの組立を示し、図５と共通の部分には同一の符号が付
されている。このとき、ゲート端子７がはんだ39で固定
される端子台37の高さが同じであれば問題はないが、端
子台37の加工誤差や、あるいはゲート接触基板25を用い
た素子の場合のゲート接触基板の傾きなどの理由からゲ
ート端子取り付け面の高さが違う場合、素子31が傾いて
しまったり図のように浮き上がってしまったりする場合
がある。しかし、図15に示すように、ゲート端子７の根
本に図６、図８に示したような波状部分71があれば、そ
のような取り付け面高さの差を吸収するため、図15(a)
のように素子31が最初傾いていても、各素子の両面を接
触体32、33に直接あるいはスペーサ36を介して間接に十
分な力で加圧接触させることができる。この波状部分71
がない場合には、ゲート端子７の根本部分に大きな応力
がかかり、破損の原因になるだけでなく、大きな加圧力
がかからないために接触熱抵抗が増大することがある。
上記のゲート端子構造によりこのような破損あるいは接
触熱抵抗の増大が避けられる。 図16(a) 、(b) は、図
５に示したようにモジュールの隣接素子31のゲート端子
７を直接接続した場合を示し、もしゲート端子７が剛性
が高く、同一高さにあれば、一方の素子31は浮き上がっ
てしまって上記と同様の不具合が生ずるか、先端部を可
撓性にすることにより、このような不具合が生じない。In the above embodiments, one IGBT element has one IGBT chip, but the same double-sided cooling structure can be applied to a microstack in which a plurality of IGBT chips each having one or a plurality of gates are enclosed. And defective chips can be similarly separated. Figure 14 shows
The assembly of a module composed of a plurality of IGBT elements 31 according to the present invention is shown, and the same parts as those in FIG. 5 are designated by the same reference numerals. At this time, if the height of the terminal block 37 to which the gate terminal 7 is fixed by the solder 39 is the same, there is no problem, but there is a processing error of the terminal block 37 or the gate in the case of an element using the gate contact substrate 25. When the height of the gate terminal mounting surface is different due to the inclination of the contact substrate, the element 31 may be inclined or lifted as shown in the figure. However, as shown in FIG. 15, if there is a wavy portion 71 at the base of the gate terminal 7 as shown in FIG. 6 and FIG. )
Even when the element 31 is initially inclined as described above, both surfaces of each element can be brought into pressure contact with the contact bodies 32 and 33 directly or indirectly through the spacer 36 with sufficient force. This wavy portion 71
In the case where there is not, not only a large stress is applied to the root portion of the gate terminal 7 to cause damage, but also a large pressing force is not applied, which may increase the contact thermal resistance.
The above gate terminal structure avoids such damage or increase in contact thermal resistance. 16 (a) and 16 (b) show the case where the gate terminal 7 of the adjacent element 31 of the module is directly connected as shown in FIG. 5, and if the gate terminal 7 has high rigidity and is at the same height, The one element 31 is lifted to cause the same problem as described above, or such a problem does not occur by making the tip end portion flexible.
【００１６】図17に示した本発明の実施例の素子では、
ゲート端子７の先端部72をＵ字状に分岐させた。この先
端部72は変形しやすいので、加工誤差などによるゲート
端子７とゲート端子台33との位置や高さにずれがあって
も、図18(a) 、(b) に示すようにねじ38を用いて端子台
37や隣接素子のゲート端子７と密着させることができ、
組立中のゲート端子破損や接触不良などを無くすことが
できる。また素子31と接触体32、33とを密着させられ、
熱抵抗も軽減できる。In the element of the embodiment of the present invention shown in FIG. 17,
The tip 72 of the gate terminal 7 was branched into a U shape. Since the tip portion 72 is easily deformed, even if the positions and heights of the gate terminal 7 and the gate terminal block 33 are deviated due to processing errors or the like, as shown in FIGS. 18 (a) and 18 (b), the screw 38 With terminal block
Can be closely attached to 37 and the gate terminal 7 of the adjacent element,
It is possible to eliminate damage to the gate terminals and poor contact during assembly. Further, the element 31 and the contact bodies 32 and 33 can be brought into close contact with each other,
Thermal resistance can also be reduced.
【００１７】以上、ＩＧＢＴ素子についての実施例につ
いて述べたが、他の半導体装置、例えば縦形ＭＯＳＦＥ
Ｔあるいはサイリスタのように、一主面上に主電極と制
御電極を有する半導体基板を用いた半導体装置において
も同様に実施できる。The embodiments of the IGBT element have been described above, but other semiconductor devices, such as vertical MOSFEs, have been described.
The same can be applied to a semiconductor device using a semiconductor substrate having a main electrode and a control electrode on one main surface like T or a thyristor.
【００１８】[0018]
【発明の効果】本発明によれば、半導体素体の両主面の
主電極に電極体を接合し、一主面上の制御電極からは共
通配線を介して容器側方に制御端子を引き出し、電極体
に外部の圧力により容器端子板を接触させて熱および電
気の通路の一部とするか、電極体の他面を容器外面に露
出させることにより、半導体装置両面からの放熱が可能
となり、小さな体積で大きな電流容量を持たせることが
可能となった。さらに、複数の制御電極への接続に、共
通制御配線をはさみ、各制御電極の一部に接合する突出
電極のみが露出する接触基板を用いることにより、導線
のボンディングのためのスペースが節減され、一層の小
形化が可能となった。According to the present invention, the electrode bodies are joined to the main electrodes on both main surfaces of the semiconductor element body, and the control terminals are drawn out to the side of the container from the control electrodes on one main surface through the common wiring. , It is possible to radiate heat from both sides of the semiconductor device by bringing the container terminal plate into contact with the electrode body by external pressure to form part of the heat and electricity passage or exposing the other surface of the electrode body to the outer surface of the container. , It became possible to have a large current capacity with a small volume. Furthermore, for connecting to a plurality of control electrodes, a common control wiring is sandwiched, and by using a contact substrate in which only the protruding electrodes that are joined to a part of each control electrode are exposed, the space for bonding the conductor wire is saved, Further downsizing has become possible.
【図１】本発明の一実施例のＩＧＢＴ素子を示し、(a)
が断面図、(b) が素子チップの正面図FIG. 1 shows an IGBT element according to an embodiment of the present invention, (a)
Is a sectional view, (b) is a front view of the element chip
【図２】ＩＧＢＴの基本構造の断面図FIG. 2 is a sectional view of the basic structure of the IGBT.
【図３】本発明の異なる実施例のＩＧＢＴを示し、(a)
が平面図、(b) が側面図、(c)が(a) のＡ−Ａ線断面図FIG. 3 shows an IGBT according to another embodiment of the present invention, (a)
Is a plan view, (b) is a side view, and (c) is a sectional view taken along the line AA of (a).
【図４】図３の素子のＢ−Ｂ線断面図4 is a cross-sectional view of the device of FIG. 3 taken along the line BB.
【図５】図１の素子を用いたＩＧＢＴモジュールの断面
図5 is a cross-sectional view of an IGBT module using the device of FIG.
【図６】本発明の別の実施例のＩＧＢＴ素子を示し、
(a) が平面図、(b) が(a) のＣ−Ｃ線断面図、(c) が
(a) のＤ−Ｄ線断面図FIG. 6 shows an IGBT device according to another embodiment of the present invention,
(a) is a plan view, (b) is a sectional view taken along line CC of (a), and (c) is
(a) DD line sectional view
【図７】図６の素子のゲート接触基板を示し、(a) 上平
面図、(b) が下面図FIG. 7 shows a gate contact substrate of the device of FIG. 6, (a) a top plan view, and (b) a bottom view.
【図８】本発明のさらに別の実施例のＩＧＢＴ素子を示
し、(a) が平面図、(b) が(a)のＥ−Ｅ線断面図、(c)
が(a) のＦ−Ｆ線断面図FIG. 8 shows an IGBT element according to still another embodiment of the present invention, (a) is a plan view, (b) is a sectional view taken along line EE of (a), (c).
Is a sectional view taken along line FF of (a)
【図９】本発明の他の実施例のＩＧＢＴ素子を示し、
(a) が平面図、(b) が(a) のＨ−Ｈ線断面図、(c) が
(b) のＩ−Ｉ線矢視断面図FIG. 9 shows an IGBT device according to another embodiment of the present invention,
(a) is a plan view, (b) is a sectional view taken along the line H-H of (a), and (c) is
(b) sectional view taken along the line II of FIG.
【図10】本発明の他の実施例のＩＧＢＴ素子の断面図FIG. 10 is a sectional view of an IGBT element according to another embodiment of the present invention.
【図11】本発明の実施例のＩＧＢＴ素子に用いるゲート
接触基板の一例を示し、下部絶縁板を除いての下面図FIG. 11 is a bottom view showing an example of a gate contact substrate used for the IGBT element of the embodiment of the present invention, excluding a lower insulating plate.
【図12】本発明の実施例のＩＧＢＴ素子に用いるゲート
接触基板の他の例を示し、下部絶縁板を除いての下面図FIG. 12 is a bottom view showing another example of the gate contact substrate used for the IGBT element of the embodiment of the present invention, excluding the lower insulating plate.
【図13】図６あるいは図８の素子でのリペアの方法を示
し、(a) がＩＧＢＴチップの平面図、(b) がリペア後の
ゲート接触基板の平面図、(c) がリペア後のゲート接触
基板の下面図13 shows a method of repairing the device of FIG. 6 or FIG. 8, (a) is a plan view of an IGBT chip, (b) is a plan view of a gate contact substrate after repair, and (c) is a plan view after repair. Bottom view of gate contact substrate
【図14】本発明の実施例の素子をＩＧＢＴモジュールの
組立ての際の不具合の例を示す側面図FIG. 14 is a side view showing an example of a defect in assembling the element of the embodiment of the present invention into an IGBT module.
【図15】図６あるいは図８の素子を用いたＩＧＢＴモジ
ュールの組立方法を(a) 、(b)の順に示す側面図15 is a side view showing an assembly method of an IGBT module using the device of FIG. 6 or 8 in the order of (a) and (b).
【図16】図６あるいは図８の素子のゲート端子相互を接
続した場合を示し、(a) が側面図、(b) が(a) のＧ部拡
大側面図16 shows a case where the gate terminals of the device of FIG. 6 or FIG. 8 are connected to each other, (a) is a side view, and (b) is an enlarged side view of G part of (a).
【図17】本発明のさらに異なる実施例のＩＧＢＴ素子の
平面図FIG. 17 is a plan view of an IGBT device according to still another embodiment of the present invention.
【図18】図17の素子を用いたＩＧＢＴモジュールを示
し、(a) が側面図、(b) が(a) のＪ部拡大平面図FIG. 18 shows an IGBT module using the device of FIG. 17, (a) is a side view, and (b) is an enlarged plan view of the J part of (a).
１ ＩＧＢＴチップ ２ コレクタ電極体 ３ エミッタ電極体 ４ 底板 ５ 外枠 ７ ゲート端子 ９ 蓋板 １０ 不良ユニット １５ ゲート絶縁膜 １６ ゲート電極 １７ エミッタ電極 ２１ コレクタ電極 ２２ ゲートパッド ２４ 樹脂 ２５ ゲート接触基板 ２６ 上部絶縁板 ２７ 下部絶縁板 ２８ はんだバンプ ３１ ＩＧＢＴ素子 ３２ 上部接触体 ３３ 下部接触体 ３４ 絶縁ボルト ３５ ナット ７１ ゲート端子波状部分 ７２ 分岐部 ８１ スリット 1 IGBT chip 2 collector electrode body 3 emitter electrode body 4 bottom plate 5 outer frame 7 gate terminal 9 cover plate 10 defective unit 15 gate insulating film 16 gate electrode 17 emitter electrode 21 collector electrode 22 gate pad 24 resin 25 gate contact substrate 26 upper insulation Plate 27 Lower insulating plate 28 Solder bump 31 IGBT element 32 Upper contact body 33 Lower contact body 34 Insulation bolt 35 Nut 71 Gate terminal corrugated portion 72 Branching portion 81 Slit
Claims (14)
半導体素体の１個あるいは複数個が一つの容器に収容さ
れ、複数の制御電極が共通の制御端子に接続されるもの
において、半導体素体の両主面にそれぞれ存在する主電
極に半導体材料に熱膨脹係数の近似した金属材料よりな
る電極体が接合され、両電極体の反半導体素体側の面が
それぞれ容器の端子板に対向し、各制御電極が容器の絶
縁性側壁を貫通して引き出される制御端子に接続される
共通配線と接続されたことを特徴とする半導体装置。1. A container in which one or a plurality of semiconductor elements having a main electrode and a control electrode on one main surface are housed in one container, and the plurality of control electrodes are connected to a common control terminal, An electrode body made of a metal material having a thermal expansion coefficient close to that of the semiconductor material is bonded to the main electrodes respectively present on both main surfaces of the semiconductor body, and the surfaces of the two electrode bodies on the side opposite to the semiconductor body face the terminal plates of the container, respectively. The semiconductor device is characterized in that each control electrode is connected to a common wiring connected to a control terminal that extends through the insulating side wall of the container.
面の端子板に加圧して使用される請求項１記載の半導体
装置。2. The semiconductor device according to claim 1, wherein the contact bodies each having a cooling means are pressed against the terminal plates on both sides of the container for use.
半導体素体の１個あるいは複数個が一つの容器に収容さ
れ、複数の制御電極が共通の制御端子に接続されるもの
において、半導体素体の両主面にそれぞれ存在する主電
極に半導体材料に熱膨脹係数の近似した金属材料よりな
る電極体が接合され、両電極体の一方が反半導体素体側
で容器外面に露出し、他方の反半導体素体側の面が容器
の端子板に対向し、各制御電極が容器の絶縁性側壁を貫
通して引き出される制御端子に接続される共通配線と接
続されたことを特徴とする半導体装置。3. A container in which one or a plurality of semiconductor elements having a main electrode and a control electrode on one main surface are housed in one container, and the plurality of control electrodes are connected to a common control terminal, An electrode body made of a metal material having a thermal expansion coefficient close to that of a semiconductor material is joined to the main electrodes respectively present on both main surfaces of the semiconductor body, and one of the two electrode bodies is exposed to the outer surface of the container on the side opposite to the semiconductor body, and the other is A semiconductor device in which the surface on the anti-semiconductor body side of the device is opposed to the terminal plate of the container, and each control electrode is connected to a common wiring connected to a control terminal that extends through the insulating side wall of the container. .
外面に露出する電極体および端子板に加圧して使用され
る請求項３記載の半導体装置。4. The semiconductor device according to claim 3, wherein the contact bodies each having a cooling means are used by applying pressure to the electrode body and the terminal plate exposed on both outer surfaces of the container.
半導体素体の１個あるいは複数個が一つの容器に収容さ
れ、複数の制御電極が共通の制御端子に接続されるもの
において、半導体素体の両主面にそれぞれ存在する主電
極に半導体材料に熱膨脹係数の近似した金属材料よりな
る電極体が接合され、両電極体が反半導体素体側で容器
外面に露出し、各制御電極が容器の絶縁性側壁を貫通し
て引き出される制御端子に接続される共通配線と接続さ
れたことを特徴とする半導体装置。5. A container in which one or a plurality of semiconductor elements having a main electrode and a control electrode on one main surface are housed in one container, and the plurality of control electrodes are connected to a common control terminal, An electrode body made of a metal material having a thermal expansion coefficient close to that of the semiconductor material is bonded to the main electrodes respectively present on both main surfaces of the semiconductor body, and both electrode bodies are exposed to the outer surface of the container on the side opposite to the semiconductor body, and each control electrode is exposed. Is connected to a common wire connected to a control terminal that extends through the insulating side wall of the container.
面に露出する電極体に加圧して使用される請求項５記載
の半導体装置。6. The semiconductor device according to claim 5, wherein the contact bodies each having a cooling means are used by applying pressure to the electrode bodies exposed on both sides of the container.
配線が中間で除去された請求項１ないし６のいずれかに
記載の半導体装置。7. The semiconductor device according to claim 1, wherein a connection wiring between a part of the control electrode and the common wiring is removed in the middle.
と接続された請求項１ないし７のいずれかに記載の半導
体装置。8. The semiconductor device according to claim 1, wherein each of the control electrodes is connected to a common wiring by a conductive wire.
一方の絶縁板一面に共通配線と接続される複数の突出電
極が露出し、その突出電極が各制御電極の一部分にそれ
ぞれ接合された請求項１ないし７のいずれかに記載の半
導体装置。9. A common wire is sandwiched between two insulating plates,
8. The semiconductor device according to claim 1, wherein a plurality of projecting electrodes connected to the common wiring are exposed on one surface of one insulating plate, and the projecting electrodes are respectively joined to a part of each control electrode.
する主電極に接合された電極体の断面積が制御電極と制
御端子との間の接続導体より半導体素体から遠い側にお
いて大きくされた請求項１ないし９のいずれかに記載の
半導体装置。10. The cross-sectional area of the electrode body joined to the main electrode existing on the same main surface of the control electrode and the semiconductor body is farther from the semiconductor body than the connecting conductor between the control electrode and the control terminal. The semiconductor device according to claim 1, which is enlarged.
電極と制御端子との間の接続導体の上方を避けて大きく
された請求項10記載の半導体装置。11. The semiconductor device according to claim 10, wherein the cross-sectional area of the electrode body is increased so as to avoid a portion above the connection conductor between the control electrode and the control terminal on the main surface of the semiconductor element body.
が可撓性である請求項１ないし11のいずれかに記載の半
導体装置。12. The semiconductor device according to claim 1, wherein a portion of the control terminal outside the container and close to the tip is flexible.
成された請求項12記載の半導体装置。13. The semiconductor device according to claim 12, wherein a portion of the control terminal close to the container is formed in a wavy shape.
項12記載の半導体装置。14. The semiconductor device according to claim 12, wherein a tip of the control terminal is branched in a U shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05081002A JP3129020B2 (en) | 1992-04-09 | 1993-04-08 | Semiconductor device |
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8737792 | 1992-04-09 | ||
| JP4-87377 | 1993-02-08 | ||
| JP5-19121 | 1993-02-08 | ||
| JP1912193 | 1993-02-08 | ||
| JP05081002A JP3129020B2 (en) | 1992-04-09 | 1993-04-08 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06291223A true JPH06291223A (en) | 1994-10-18 |
| JP3129020B2 JP3129020B2 (en) | 2001-01-29 |
Family
ID=27282505
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP05081002A Expired - Fee Related JP3129020B2 (en) | 1992-04-09 | 1993-04-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3129020B2 (en) |
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