JP2000223609A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2000223609A
JP2000223609A JP11021542A JP2154299A JP2000223609A JP 2000223609 A JP2000223609 A JP 2000223609A JP 11021542 A JP11021542 A JP 11021542A JP 2154299 A JP2154299 A JP 2154299A JP 2000223609 A JP2000223609 A JP 2000223609A
Authority
JP
Japan
Prior art keywords
wiring board
semiconductor chip
electrode
solder
insulating plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11021542A
Other languages
Japanese (ja)
Inventor
Atsushi Komura
敦 小村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP11021542A priority Critical patent/JP2000223609A/en
Publication of JP2000223609A publication Critical patent/JP2000223609A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device wherein the coplanarity of solder balls below a semiconductor chip is good if the balls are disposed below the chip, a stable connection to an external wiring board is obtained and a stress to the connection is relaxed to avoid deteriorating the connection reliability if the solder ball spacing is small. SOLUTION: In a semiconductor device using solder balls 11 as terminals for connecting a board to externals, the solder balls 11 are mounted on solder mounts of a wiring board 5 through an insulation plate 10 made of an electrically insulative material having a high thermal conductivity, the balls 11 are disposed below a semiconductor chip and the coplanarity of the solder balls below a semiconductor chip is good, a stable connection to an external wiring board is obtained and a stress to the connection is relaxed to avoid deteriorating the connection reliability if the solder ball spacing is small.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体チップを配
線基板に搭載し前記半導体チップと前記配線基板とを電
気的な接続を行い、その接続部を覆うように樹脂で封止
し、前記配線基板上に外部の配線基板と接続を行うため
のハンダ突起端子を設けた半導体装置に関する。The present invention relates to a method for mounting a semiconductor chip on a wiring board, electrically connecting the semiconductor chip to the wiring board, sealing the semiconductor chip with a resin so as to cover the connection portion, and connecting the semiconductor chip to the wiring board. The present invention relates to a semiconductor device provided with solder projection terminals for connecting to an external wiring board on a board.

【０００２】[0002]

【従来の技術】近年、半導体装置の高機能化にともな
い、半導体装置の外部端子の数は増大する傾向にあり、
側面に外部端子を設けいているＱＦＰのような半導体装
置は外部端子の端子ピッチを狭くしたとしても、外形サ
イズが大きくなってしまう傾向にある。これに対して、
ＢＧＡあるいはＣＳＰのような電極端子をアレイ上に配
置できる半導体装置は、外部端子の増加ができ、且つＱ
ＦＰよりも外形サイズを小さくすることが可能である。2. Description of the Related Art In recent years, the number of external terminals of a semiconductor device has been increasing with the advancement of functions of the semiconductor device.
Semiconductor devices such as QFPs provided with external terminals on the side surface tend to have a large external size even if the terminal pitch of the external terminals is reduced. On the contrary,
A semiconductor device such as BGA or CSP, in which electrode terminals can be arranged on an array, can increase the number of external terminals.
It is possible to make the outer size smaller than FP.

【０００３】従来の半導体装置として、配線基板にポリ
イミドテープ等を用いたテープタイプのＢＧＡの構造に
ついて図１１を用いて説明する。[0003] As a conventional semiconductor device, a structure of a tape type BGA using a polyimide tape or the like for a wiring board will be described with reference to FIG.

【０００４】図１１は配線基板にポリイミドテープを用
いたテープタイプのＢＧＡを示す断面図である。半導体
チップ１上にはＡｕの突起電極３１が形成されている。
ポリイミドテープ３２には半導体チップ１の突起電極３
１の配置に対応するように形成されたＣｕリード３４が
形成され、また外部の配線基板との電気的に接続するよ
うにパッド電極１３が形成されている。半導体チップ１
とポリイミドテープ３２とは半導体チップ１に形成した
突起電極３１とＣｕリード３４との接続を行っている。
ハンダボール１７は半導体チップ１よりも外側に配置
し、ハンダボール１７を搭載しているポリイミドテープ
３２上にはハンダボール１７のコプラナリティー精度を
保つために補強材３５を接着材３６を介して装着してい
る。さらに、半導体チップ１とＣｕリード３４を覆うよ
うに樹脂３７で封止されている。FIG. 11 is a sectional view showing a tape-type BGA using a polyimide tape for a wiring board. Au bump electrodes 31 are formed on the semiconductor chip 1.
The protruding electrodes 3 of the semiconductor chip 1 are provided on the polyimide tape 32.
Cu leads 34 are formed so as to correspond to the arrangement 1, and pad electrodes 13 are formed so as to be electrically connected to an external wiring board. Semiconductor chip 1
The polyimide tape 32 connects the protruding electrodes 31 formed on the semiconductor chip 1 to the Cu leads 34.
The solder balls 17 are arranged outside the semiconductor chip 1, and a reinforcing material 35 is mounted on the polyimide tape 32 on which the solder balls 17 are mounted via an adhesive 36 in order to maintain the coplanarity accuracy of the solder balls 17. are doing. Further, the semiconductor chip 1 and the Cu lead 34 are sealed with a resin 37 so as to cover the same.

【０００５】[0005]

【発明が解決しようとする課題】しかしながら、ハンダ
ボールを半導体チップよりも外側に配置するために小型
化が難しい。また、ハンダボールを半導体チップ下に配
置すると、半導体チップ下のハンダボールのコプラナリ
ティー精度が悪くなり、外部配線基板との接続が安定し
て得られないことが発生する。However, since the solder balls are arranged outside the semiconductor chip, miniaturization is difficult. In addition, when the solder balls are arranged below the semiconductor chip, the coplanarity accuracy of the solder balls below the semiconductor chip deteriorates, and the connection with the external wiring board cannot be stably obtained.

【０００６】（発明の目的）本発明の１つの目的は、上
記の課題点を解決して、ハンダボールを半導体チップ下
に配置しても、半導体チップ下のハンダボールのコプラ
ナリティー精度が良く、外部配線基板との接続が安定し
た接続が得られ、ハンダボール間の間隔が狭くなっても
接続部への応力を緩和して接続信頼性を損なわない半導
体装置を提供することにある。(Object of the Invention) One object of the present invention is to solve the above-mentioned problems and to improve the coplanarity accuracy of the solder ball under the semiconductor chip even if the solder ball is arranged under the semiconductor chip. It is an object of the present invention to provide a semiconductor device which can provide stable connection with an external wiring board and which does not impair connection reliability by reducing stress on a connection portion even when a space between solder balls is reduced.

【０００７】本発明のもう１つの目的は、半導体装置の
構造において、上記の目的に加えて熱伝導性の良い絶縁
プレートをハンダボール側に配置することで、半導体チ
ップより発生する熱を効率よく放熱することができる半
導体装置を提供することにある。Another object of the present invention is to provide a semiconductor device structure in which, in addition to the above objects, an insulating plate having good heat conductivity is arranged on the solder ball side, so that heat generated from a semiconductor chip can be efficiently consumed. An object of the present invention is to provide a semiconductor device capable of radiating heat.

【０００８】[0008]

【課題を解決するための手段】前述した目的を達成する
ために、本発明の半導体装置の構造は、下記記載の構成
を採用する。In order to achieve the above-mentioned object, the structure of the semiconductor device of the present invention adopts the following configuration.

【０００９】本発明の１つの半導体装置は、回路形成面
に形成した外部引き出し用の電極をもつ半導体チップ
と、半導体チップを搭載する側には前記半導体チップの
電極と電気的接続を行うための電極や配線を配し、外部
の配線基板と電気的な接続を行う側に配線や前記外部の
配線基板と電気的接続を行うパッド電極を形成した配線
基板と、前記配線基板よりも熱伝導率の良い材料をもち
いた絶縁プレートと、前記の配線基板と絶縁プレートと
の間に、配線基板と絶縁プレートとを接着する接着層
と、前記外部の配線基板と電気的接続を行う前記パッド
電極上にはハンダで形成した突起端子とを有し、少なく
とも前記半導体チップと電気的接続した接続部を封止樹
脂で覆われた半導体チップを配線基板にフェイスアップ
で搭載した構造を特徴としたものである。According to one aspect of the present invention, there is provided a semiconductor device having a semiconductor chip having an external lead electrode formed on a circuit forming surface, and a semiconductor chip mounting side for electrically connecting to the semiconductor chip electrode. A wiring board on which electrodes and wiring are arranged, and a wiring or a pad electrode for electrically connecting to the external wiring board is formed on the side for making an electrical connection with the external wiring board; An insulating plate using a good material, an adhesive layer for bonding the wiring board and the insulating plate between the wiring board and the insulating plate, and the pad electrode for making an electrical connection with the external wiring board. Has a protruding terminal formed of solder, and has a structure in which a semiconductor chip having at least a connection portion electrically connected to the semiconductor chip covered with a sealing resin is mounted face up on a wiring board. One in which the.

【００１０】本発明のもう１つの半導体装置は、回路形
成面に形成した外部引き出し用の電極に突起電極をもつ
半導体チップと、前記半導体チップを搭載する側には前
記半導体チップの突起電極と電気的接続を行うための電
極と配線とを配し、外部の配線基板と電気的な接続を行
う側には前記外部の配線基板と電気的接続を行うパッド
電極や配線を形成した配線基板と、前記配線基板よりも
熱伝導率が良く、かつ電気的に絶縁性である材料をもち
いた絶縁プレートと、前記の配線基板と絶縁プレートと
の間に、配線基板と絶縁プレートとを接着する接着層
と、前記外部の配線基板と電気的接続を行う前記パッド
電極上にはハンダで形成した突起端子とを有し、前記半
導体チップと前記配線基板との間隙に封止樹脂を注入し
た半導体チップを配線基板にフェイスダウンで搭載した
構造を特徴としたものである。According to another aspect of the present invention, there is provided a semiconductor device having a protruding electrode on an external lead electrode formed on a circuit forming surface, and a protruding electrode of the semiconductor chip on a side on which the semiconductor chip is mounted. An electrode and a wiring for making an electrical connection are arranged, and a wiring board on which a pad electrode or a wiring for making an electrical connection with the external wiring board is formed on a side for making an electrical connection with an external wiring board, An insulating plate using a material having a higher thermal conductivity than the wiring board and being electrically insulating; and an adhesive layer for bonding the wiring board and the insulating plate between the wiring board and the insulating plate. A semiconductor chip having a protruding terminal formed of solder on the pad electrode for making an electrical connection with the external wiring board, and injecting a sealing resin into a gap between the semiconductor chip and the wiring board. Arrangement Mounting structure face down to the substrate is obtained by said.

【００１１】[0011]

【発明の実施の形態】以下、図面を用いて本発明の第１
の実施形態における半導体装置の構成の説明を行う。BRIEF DESCRIPTION OF THE DRAWINGS FIG.
The configuration of the semiconductor device according to the embodiment will be described.

【００１２】本発明の第１の実施形態については図１〜
図５を用いて構造を説明する。図１は本発明の第１の実
施形態における半導体装置の断面図、図２は半導体チッ
プ１の電極２側から見た平面図、図３は半導体チップ１
の断面図、図４は配線基板５の半導体チップ１搭載側か
ら見た平面図、図５は配線基板１７の断面図である。FIG. 1 shows a first embodiment of the present invention.
The structure will be described with reference to FIG. FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a plan view of the semiconductor chip 1 as viewed from the electrode 2 side, and FIG.
4 is a plan view of the wiring board 5 as viewed from the side where the semiconductor chip 1 is mounted, and FIG. 5 is a cross-sectional view of the wiring board 17.

【００１３】半導体チップ１は図２、図３を用いて説明
する。Ｓｉ４上に電子回路を形成し、その回路の外部端
子としてＡｌまたはＡｕなどで電極２が形成されてい
る。電極２の材料あるいは表面処理については配線基板
５とをワイヤー１４で結線する際のワイヤー１４の材料
やボンダビリティーを考慮して選択する。半導体チップ
１の電極２以外の部分はＳｉＮ等の無機膜か前記の無機
膜にさらにその上にポリイミド等の有機膜による保護膜
３で覆われ、外部とは電気的に絶縁されている。The semiconductor chip 1 will be described with reference to FIGS. An electronic circuit is formed on Si4, and an electrode 2 is formed of Al or Au as an external terminal of the circuit. The material or surface treatment of the electrode 2 is selected in consideration of the material and bondability of the wire 14 when the wiring 2 is connected to the wiring board 5. The portion of the semiconductor chip 1 other than the electrodes 2 is covered with a protective film 3 made of an inorganic film such as SiN or the above-mentioned inorganic film or an organic film such as polyimide, and is electrically insulated from the outside.

【００１４】配線基板５については図４、図５を用いて
説明する。配線基板５の絶縁プレート１０上で半導体チ
ップ１の裏面を搭載するのエリア９には複数のサーマル
ビアホール８が形成されていて、半導体チップ１を搭載
した際の電源グランドおよび半導体チップ１を放熱する
ために形成している。つまり、半導体チップ１の裏面を
配線基板１７のパッド電極７とを電気的に接続すること
と、半導体チップ１より発生した熱を配線基板５のハン
ダボール面に逃がす役割とを兼ねている。また絶縁プレ
ート１０に形成したサーマルビアホール８や貫通穴１８
内にはハンダ１２が埋められており、配線基板６のハン
ダボール１７搭載側から半導体チップ１搭載側への水分
の侵入を抑えることができ、なおかつ電気的に接続がで
きる。The wiring board 5 will be described with reference to FIGS. A plurality of thermal via holes 8 are formed in an area 9 for mounting the back surface of the semiconductor chip 1 on the insulating plate 10 of the wiring board 5, and radiate the power ground and the semiconductor chip 1 when the semiconductor chip 1 is mounted. It is formed for. That is, the back surface of the semiconductor chip 1 is electrically connected to the pad electrode 7 of the wiring board 17, and the heat generated from the semiconductor chip 1 is released to the solder ball surface of the wiring board 5. The thermal via hole 8 and the through hole 18 formed in the insulating plate 10
The solder 12 is buried in the inside, so that intrusion of moisture from the solder ball 17 mounting side of the wiring board 6 to the semiconductor chip 1 mounting side can be suppressed, and electrical connection can be made.

【００１５】電極７は半導体チップ１の電極２とをワイ
ヤー１４で結線するための電極で、Ｃｕ上にＡｕ／Ｎｉ
メッキを施している。ワイヤー１４のボンダビリティー
を考慮し、Ｎｉ層の厚さが３〜１５μｍ、Ａｕ層の厚さ
が０．３〜１μｍで形成している。The electrode 7 is an electrode for connecting the electrode 2 of the semiconductor chip 1 to the electrode 2 by a wire 14.
Plated. In consideration of the bondability of the wire 14, the thickness of the Ni layer is 3 to 15 μm, and the thickness of the Au layer is 0.3 to 1 μm.

【００１６】配線基板５の半導体チップ１を搭載する側
は上記のダイアタッチエリア９、電極７以外部分はポリ
イミドのカバーレイ６で覆われている。The side of the wiring board 5 on which the semiconductor chip 1 is mounted is covered with the above-mentioned die attach area 9, and portions other than the electrodes 7 are covered with a polyimide coverlay 6.

【００１７】配線基板５のハンダボール搭載側は材料に
アルミナを用いた絶縁プレート１０で、貫通穴１８にハ
ンダ１２を充填し、ハンダボール１７を搭載するパッド
電極１３を形成している。The solder ball mounting side of the wiring board 5 is an insulating plate 10 using alumina as a material. The through holes 18 are filled with solder 12 to form pad electrodes 13 on which solder balls 17 are mounted.

【００１８】接着層１１は、絶縁プレート１０の貫通穴
１８と対応する位置の接着層を開口し、貫通穴１８には
無電解メッキ法でＣｕを形成する。The adhesive layer 11 is opened at a position corresponding to the through hole 18 of the insulating plate 10, and Cu is formed in the through hole 18 by electroless plating.

【００１９】配線基板５の電極７およびＣｕ配線１９と
絶縁プレート１０とは接着層１１で接着し、機械的な強
度を確保する。The electrode 7 and the Cu wiring 19 of the wiring board 5 are bonded to the insulating plate 10 with an adhesive layer 11 to secure mechanical strength.

【００２０】配線基板の電極７およびＣｕ配線１９と絶
縁プレート１０の接着後、絶縁プレート１０の貫通穴１
８にＳｎとＰｂとの比率が５：９５の比率のハンダペー
ストを埋め、ハンダの融点以上の温度でかつ、−７６０
ｍｍＨｇまで減圧した雰囲気でハンダペーストを溶融す
ることで、Ｃｕ配線１９と貫通穴１８は溶融したハンダ
１２で電気的な接続を得られる。また、減圧した雰囲気
で溶融したことで、貫通穴１８内に気泡を含むことなく
ハンダ１２が充填できる。After bonding the insulating plate 10 to the electrode 7 and the Cu wiring 19 of the wiring board, the through holes 1 in the insulating plate 10
8 is filled with a solder paste in which the ratio of Sn to Pb is 5:95, at a temperature equal to or higher than the melting point of the solder and at -760.
By melting the solder paste in an atmosphere reduced to mmHg, the Cu wiring 19 and the through hole 18 can be electrically connected by the molten solder 12. Further, by melting in a reduced-pressure atmosphere, the solder 12 can be filled in the through hole 18 without containing bubbles.

【００２１】半導体装置については上記の半導体チップ
１、配線基板５を含め図１を用いて説明する。半導体チ
ップ１は配線基板５上のダイアタッチエリア９上に接着
剤１５を用いて固定している。接着剤１５はエポキシ樹
脂にＡｇのフィラーを含有しているので、半導体チップ
１をダイアタッチエリア９上に搭載した際の電源グラン
ドへの電気的接続および半導体チップ１から発生する熱
をサーマルビアホール８へ放熱することができる。A semiconductor device including the above-described semiconductor chip 1 and wiring board 5 will be described with reference to FIG. The semiconductor chip 1 is fixed on the die attach area 9 on the wiring board 5 using an adhesive 15. Since the adhesive 15 contains an Ag filler in the epoxy resin, when the semiconductor chip 1 is mounted on the die attach area 9, electrical connection to the power ground and heat generated from the semiconductor chip 1 are transferred to the thermal via holes 8. The heat can be dissipated.

【００２２】半導体チップ１上の各電極２と配線基板５
上の電極７との電気的接続はＡｕのワイヤー１４で行わ
れている。Ａｕのワイヤー径は０．０３〜０．０５ｍｍ
程度のワイヤーを使用している。電極７とパッド電極１
３とは貫通穴１８およびハンダ１２を介して電気的に接
続している。Each electrode 2 on the semiconductor chip 1 and the wiring board 5
The electrical connection with the upper electrode 7 is made by Au wire 14. Au wire diameter is 0.03-0.05mm
We use a certain amount of wire. Electrode 7 and pad electrode 1
3 is electrically connected through the through hole 18 and the solder 12.

【００２３】半導体チップ１、ワイヤー１４および配線
基板５の電極７は、遮蔽と保護のためにモールド樹脂１
６で封止している。モールド樹脂１６には熱硬化性のエ
ポキシ系樹脂を使用している。The semiconductor chip 1, the wires 14, and the electrodes 7 of the wiring board 5 are molded resin 1 for shielding and protection.
6 is sealed. A thermosetting epoxy resin is used for the mold resin 16.

【００２４】さらに、配線基板５のパッド電極１３には
ハンダボール１７を形成している。このハンダボール１
７には、ＳｎとＰｂとの比率が６：４の組成のハンダを
用いている。このハンダボール１７を介してこの半導体
装置と外部の配線基板との電気的接続を行っている。Further, solder balls 17 are formed on the pad electrodes 13 of the wiring board 5. This solder ball 1
For No. 7, solder having a composition in which the ratio of Sn to Pb is 6: 4 is used. The semiconductor device is electrically connected to an external wiring board via the solder balls 17.

【００２５】つぎに、本発明の第２の実施形態における
半導体装置の構成の説明を行う。Next, the configuration of the semiconductor device according to the second embodiment of the present invention will be described.

【００２６】本発明の第２の実施形態については図６〜
図１０を用いて構造を説明する。図６は本発明の第２の
実施形態における半導体装置の断面図、図７は半導体チ
ップ１のハンダの突起電極２０側から見た平面図、図８
は半導体チップ１の断面図、図９は配線基板５の半導体
チップ１搭載側から見た平面図、図１０は配線基板５の
断面図である。The second embodiment of the present invention will be described with reference to FIGS.
The structure will be described with reference to FIG. FIG. 6 is a cross-sectional view of a semiconductor device according to the second embodiment of the present invention, FIG. 7 is a plan view of the solder of the semiconductor chip 1 as viewed from the protruding electrode 20 side, and FIG.
9 is a cross-sectional view of the semiconductor chip 1, FIG. 9 is a plan view of the wiring board 5 as viewed from the side where the semiconductor chip 1 is mounted, and FIG.

【００２７】半導体チップ１は図７、図８を用いて説明
する。Ｓｉ４上に電子回路を形成し、その回路の外部端
子としてＡｌなどで電極２が形成されている。電極２の
上に配線基板５の電極７との電気的接続を行うためにＳ
ｎとＰｂとの比率が６：４の組成のハンダで突起電極２
０を形成している。Ａｌの電極２上にハンダの突起電極
２０を形成するためにバリアメタル層２２を蒸着法やス
パッタリング法を用いて形成したのちに、その上にハン
ダの突起電極２０をメッキによって形成する。バリアメ
タル層２２は電極２と突起電極２０のそれぞれの金属の
相互拡散を防止するために形成している。The semiconductor chip 1 will be described with reference to FIGS. An electronic circuit is formed on Si4, and an electrode 2 is formed of Al or the like as an external terminal of the circuit. In order to make electrical connection with the electrode 7 of the wiring board 5 on the electrode 2,
The protruding electrode 2 is made of solder having a composition of n: Pb of 6: 4.
0 is formed. After the barrier metal layer 22 is formed by vapor deposition or sputtering in order to form the solder bump electrode 20 on the Al electrode 2, the solder bump electrode 20 is formed thereon by plating. The barrier metal layer 22 is formed to prevent mutual diffusion of the respective metals of the electrode 2 and the bump electrode 20.

【００２８】半導体チップ１の電極２以外の部分はＳｉ
Ｎ等の無機膜か前記の無機膜にさらにその上へポリイミ
ド等の有機膜による保護膜３で覆われ、外部とは電気的
に絶縁されている。The portion of the semiconductor chip 1 other than the electrode 2 is made of Si.
An inorganic film such as N or the above-mentioned inorganic film is further covered thereon with a protective film 3 made of an organic film such as polyimide, and is electrically insulated from the outside.

【００２９】配線基板５については図９、図１０を用い
て説明する。配線基板５の半導体チップ搭載側のパッド
電極７は半導体チップ１の電極２の配置に対応するよう
に配置している。The wiring board 5 will be described with reference to FIGS. The pad electrodes 7 on the semiconductor chip mounting side of the wiring board 5 are arranged so as to correspond to the arrangement of the electrodes 2 on the semiconductor chip 1.

【００３０】電極７は、半導体チップ１のハンダの突起
電極２０と電気的な接続を得るために、Ｎｉ−Ａｕメッ
キを施している。ハンダの濡れ性を考慮し、Ｎｉの厚さ
が５μｍ、Ａｕの厚さを０．０５μｍ程度で形成してい
る。The electrodes 7 are plated with Ni-Au in order to obtain electrical connection with the solder bump electrodes 20 of the semiconductor chip 1. In consideration of the wettability of the solder, the thickness of Ni is about 5 μm and the thickness of Au is about 0.05 μm.

【００３１】配線基板５の半導体チップ１を搭載する側
のＩＣ搭載エリア９内の一部には、半導体チップ１から
放出する熱を絶縁プレート１０を介して外部へ放出する
ために、絶縁プレート１０が露出している。上記の絶縁
プレート１０が露出している部分と電極７以外の部分は
すべてポリイミドのカバーレイ６で覆われている。In order to radiate the heat radiated from the semiconductor chip 1 to the outside through the insulating plate 10, an insulating plate 10 is provided in a part of the IC mounting area 9 on the side of the wiring board 5 on which the semiconductor chip 1 is mounted. Is exposed. The portion where the insulating plate 10 is exposed and the portion other than the electrode 7 are all covered with a polyimide coverlay 6.

【００３２】配線基板５のハンダボール搭載側は材料に
アルミナを用いた絶縁プレート１０で、貫通穴１８にハ
ンダ１２を充填し、ハンダボール１７を搭載するパッド
電極１３を形成している。The solder ball mounting side of the wiring board 5 is an insulating plate 10 using alumina as a material. The through holes 18 are filled with solder 12 to form pad electrodes 13 on which solder balls 17 are mounted.

【００３３】接着層１１は、絶縁プレート１０の貫通穴
１８と対応する位置の接着層を開口し、貫通穴１８には
無電解メッキ法でＣｕを形成する。The adhesive layer 11 is opened at a position corresponding to the through hole 18 of the insulating plate 10, and Cu is formed in the through hole 18 by electroless plating.

【００３４】半導体チップ１を搭載するパッド電極７お
よびＣｕ配線１９と絶縁プレート１０とは、接着層１１
で接着し、機械的な強度を確保する。The pad electrode 7 on which the semiconductor chip 1 is mounted, the Cu wiring 19 and the insulating plate 10 are
To ensure mechanical strength.

【００３５】電極７およびＣｕ配線１９と絶縁プレート
１０の接着後、絶縁プレート１０貫通穴１８にＳｎとＰ
ｂとの比率が５：９５の比率のハンダペーストを埋め、
ハンダの融点以上の温度でかつ、−７６０ｍｍＨｇまで
減圧した雰囲気でハンダペーストを溶融することで、Ｃ
ｕ配線１９と貫通穴１８は溶融したハンダ１２で電気的
な接続を得られる。また、減圧した雰囲気で溶融したこ
とで、貫通穴１８内に気泡を含むことなくハンダ１２が
充填できる。After bonding the electrode 7 and the Cu wiring 19 to the insulating plate 10, Sn and P
Fill the solder paste at a ratio of 5:95 with b,
By melting the solder paste at a temperature equal to or higher than the melting point of the solder and in an atmosphere reduced to -760 mmHg, C
Electrical connection can be obtained between the u wiring 19 and the through hole 18 by the molten solder 12. Further, by melting in a reduced-pressure atmosphere, the solder 12 can be filled in the through hole 18 without containing bubbles.

【００３６】半導体チップ１と配線基板５との間には接
続部の信頼性向上および半導体チップ１および配線基板
５に形成されている回路の保護のために封止樹脂２１で
封止している。半導体チップ１で発生した熱を絶縁プレ
ート１０を介して外部へ放出するために、封止樹脂２１
には熱導電性の良いアルミナを３０ｗｔ％以上含有した
熱硬化性のエポキシ系樹脂を使用している。The space between the semiconductor chip 1 and the wiring board 5 is sealed with a sealing resin 21 in order to improve the reliability of the connection portion and protect the circuits formed on the semiconductor chip 1 and the wiring board 5. . In order to release the heat generated in the semiconductor chip 1 to the outside through the insulating plate 10, the sealing resin 21
Is a thermosetting epoxy resin containing 30% by weight or more of alumina having good thermal conductivity.

【００３７】さらに、配線基板５のパッド電極１３には
ハンダボール１７を形成している。このハンダボール１
７には、ＳｎとＰｂとの比率が６：４の組成のハンダを
用いている。このハンダボール１７を介してこの半導体
装置と外部の配線基板との電気的接続を行っている。Further, solder balls 17 are formed on the pad electrodes 13 of the wiring board 5. This solder ball 1
For No. 7, solder having a composition in which the ratio of Sn to Pb is 6: 4 is used. The semiconductor device is electrically connected to an external wiring board via the solder balls 17.

【００３８】[0038]

【発明の効果】以上説明したように、本発明はハンダボ
ール搭載側に絶縁プレートを介してハンダボールを搭載
しているので、ハンダボールを半導体チップ下に配置し
ても、半導体チップ下のハンダボールのコプラナリティ
ー精度が良く、外部配線基板との接続が安定した接続が
得られ、また、ハンダボール間の間隔が狭くなっても接
続部への応力を緩和して接続信頼性を損なわない。As described above, according to the present invention, since the solder balls are mounted on the solder ball mounting side via the insulating plate, even if the solder balls are arranged under the semiconductor chip, the solder under the semiconductor chip can be obtained. The coplanarity of the ball is good, and a stable connection with the external wiring board can be obtained. Further, even if the interval between the solder balls becomes narrow, the stress on the connection portion is reduced and the connection reliability is not impaired.

【００３９】また、伝導性の良い絶縁プレートをハンダ
ボール側に配置することで、半導体チップより発生する
熱を効率よく放熱することができる。By arranging an insulating plate having good conductivity on the solder ball side, heat generated from the semiconductor chip can be efficiently radiated.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１の実施形態における半導体装置を
示す断面図である。FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

【図２】本発明の第１の実施形態における半導体チップ
の平面図である。FIG. 2 is a plan view of the semiconductor chip according to the first embodiment of the present invention.

【図３】本発明の第１の実施形態における半導体チップ
の断面図である。FIG. 3 is a cross-sectional view of the semiconductor chip according to the first embodiment of the present invention.

【図４】本発明の第１の実施形態における配線基板の平
面図である。FIG. 4 is a plan view of the wiring board according to the first embodiment of the present invention.

【図５】本発明の第１の実施形態における配線基板の断
面図である。FIG. 5 is a cross-sectional view of the wiring board according to the first embodiment of the present invention.

【図６】本発明の第２の実施形態における半導体装置を
示す断面図である。FIG. 6 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

【図７】本発明の第２の実施形態における半導体チップ
の平面図である。FIG. 7 is a plan view of a semiconductor chip according to a second embodiment of the present invention.

【図８】本発明の第２の実施形態における半導体チップ
の断面図である。FIG. 8 is a sectional view of a semiconductor chip according to a second embodiment of the present invention.

【図９】本発明の第２の実施形態における配線基板の平
面図である。FIG. 9 is a plan view of a wiring board according to a second embodiment of the present invention.

【図１０】本発明の第２の実施形態における配線基板の
断面図である。FIG. 10 is a cross-sectional view of a wiring board according to a second embodiment of the present invention.

【図１１】従来例における半導体装置を示すの断面図で
ある。FIG. 11 is a sectional view showing a semiconductor device in a conventional example.

【符号の説明】[Explanation of symbols]

１：半導体チップ ２：電極
５：配線基板 １０：絶縁プレート １１：ハンダボール １６：電極 １７：ハンダボール
１８：貫通穴1: Semiconductor chip 2: Electrode
5: Wiring board 10: Insulating plate 11: Solder ball 16: Electrode 17: Solder ball
18: Through hole

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 回路形成面に形成した外部引き出し用の
電極をもつ半導体チップと、半導体チップを搭載する側
には前記半導体チップの電極と電気的接続を行うための
電極や配線を配し、外部の配線基板と電気的な接続を行
う側に配線や前記外部の配線基板と電気的接続を行うパ
ッド電極を形成した配線基板と、前記配線基板よりも熱
伝導率の良い材料をもちいた絶縁プレートと、前記の配
線基板と絶縁プレートとのあいだに、配線基板と絶縁プ
レートとを接着する接着層と、前記外部の配線基板と電
気的接続を行う前記パッド電極上にはハンダで形成した
突起端子を有し、 少なくとも前記半導体チップと電気的接続した接続部を
封止樹脂で覆われている構造を有し、 半導体チップを配線基板にフェイスアップで搭載するこ
とを特徴とする半導体装置。1. A semiconductor chip having an external lead electrode formed on a circuit forming surface, and an electrode and a wiring for electrically connecting with the electrode of the semiconductor chip are arranged on a side on which the semiconductor chip is mounted. A wiring board on which a wiring or a pad electrode for making an electrical connection with the external wiring board is formed on a side for making an electrical connection with the external wiring board, and an insulation using a material having a higher thermal conductivity than the wiring board; A plate, an adhesive layer for bonding the wiring board and the insulating plate between the wiring board and the insulating plate, and a projection formed of solder on the pad electrode for making an electrical connection with the external wiring board. Having a structure in which at least a connection portion electrically connected to the semiconductor chip is covered with a sealing resin, and wherein the semiconductor chip is mounted face-up on a wiring board. Body apparatus. 【請求項２】 回路形成面に形成した外部引き出し用の
電極に突起電極をもつ半導体チップと、前記半導体チッ
プを搭載する側には前記半導体チップの突起電極と電気
的接続を行うための電極と配線とを配し、外部の配線基
板と電気的な接続を行う側には前記外部の配線基板と電
気的接続を行うパッド電極や配線を形成した配線基板
と、前記配線基板よりも熱伝導率が良く、かつ電気的に
絶縁性である材料をもちいた絶縁プレートと、前記の配
線基板と絶縁プレートとの間に、配線基板と絶縁プレー
トとを接着する接着層と、前記外部の配線基板と電気的
接続を行う前記パッド電極上にはハンダで形成した突起
端子を有し、 前記半導体チップと前記配線基板との間隙に封止樹脂を
注入した構造を有し、半導体チップを配線基板にフェイ
スダウンで搭載することを特徴とする半導体装置。2. A semiconductor chip having a protruding electrode on an external lead electrode formed on a circuit forming surface, and an electrode for electrically connecting to the protruding electrode of the semiconductor chip on a side on which the semiconductor chip is mounted. A wiring board on which a wiring is arranged and a pad electrode or wiring for electrically connecting to the external wiring board is formed on a side for making an electrical connection with the external wiring board; Good, and an insulating plate using a material that is electrically insulating, between the wiring board and the insulating plate, an adhesive layer that bonds the wiring board and the insulating plate, and the external wiring board The semiconductor device has a structure in which a sealing resin is injected into a gap between the semiconductor chip and the wiring board, and has a structure in which the semiconductor chip faces the wiring board. Dow In wherein a mounting. 【請求項３】 請求項１または２記載の絶縁性プレート
の貫通穴の内周面の表面材料は、 Ｓｎ、Ａｇ、Ａｕ、Ｃｕ、Ｐｄ、ハンダから選択される
ことを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein the surface material of the inner peripheral surface of the through hole of the insulating plate is selected from Sn, Ag, Au, Cu, Pd, and solder. 【請求項４】 請求項２記載の封止樹脂は、 熱導電性の良いアルミナを３０ｗｔ％以上有することを
特徴とする半導体装置。4. A semiconductor device according to claim 2, wherein the sealing resin contains 30% by weight or more of alumina having good thermal conductivity.
JP11021542A 1999-01-29 1999-01-29 Semiconductor device Pending JP2000223609A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11021542A JP2000223609A (en) 1999-01-29 1999-01-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11021542A JP2000223609A (en) 1999-01-29 1999-01-29 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2000223609A true JP2000223609A (en) 2000-08-11

Family

ID=12057878

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11021542A Pending JP2000223609A (en) 1999-01-29 1999-01-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2000223609A (en)

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