JP2003224228A - Package for semiconductor device, semiconductor device and its producing method - Google Patents
Package for semiconductor device, semiconductor device and its producing methodInfo
- Publication number
- JP2003224228A JP2003224228A JP2002023106A JP2002023106A JP2003224228A JP 2003224228 A JP2003224228 A JP 2003224228A JP 2002023106 A JP2002023106 A JP 2002023106A JP 2002023106 A JP2002023106 A JP 2002023106A JP 2003224228 A JP2003224228 A JP 2003224228A
- Authority
- JP
- Japan
- Prior art keywords
- conductor pattern
- forming layer
- semiconductor element
- semiconductor device
- pattern forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置用パッケ
ージ及び半導体装置に関し、更に詳細には搭載される半
導体素子の電極端子とフリップチップ方式で電気的に接
続される半導体装置用パッケージ、前記半導体装置用パ
ッケージに半導体素子が搭載された半導体装置及びその
製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device package and a semiconductor device, and more particularly to a semiconductor device package electrically connected to an electrode terminal of a mounted semiconductor element by a flip chip method, and the semiconductor device. TECHNICAL FIELD The present invention relates to a semiconductor device in which a semiconductor element is mounted in a package and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】半導体装置には、図７に示す半導体装置
１００が用いられている。図７に示す半導体装置１００
は、回路基板１０４に形成された導体パターン１０６，
１０６・・のうち、その一面側に形成された導体パター
ン１０６の接続パッドに半導体素子１０８の電極端子が
フリップチップ方式で電気的に接続されている。かかる
回路基板１０４の他面側には、その他面側に形成された
導体パターン１０６の接続パッドに外部接続端子として
のはんだボール１０２，１０２・・が設けられている。
この様に、回路基板１０４の一面側に搭載された半導体
素子１０８は、金属製の放熱板１１０に形成された凹部
１１２内に収容され、放熱板１１０の凹部１１２の開口
面側が回路基板１０４の一面側に接着剤１１６によって
接着されて両者は一体化されている。放熱板１１０の凹
部１１２内に収容された半導体素子１０８は、その背面
側と凹部１１２の底面との間に、銀等の伝熱性体が配合
された伝熱性樹脂１１４が充填され、半導体素子１０８
から放熱板１１０への伝熱性が向上されている。尚、回
路基板１０４の一面側に搭載された半導体素子１０８の
電極端子等は、ポッティング樹脂等によって封止されて
いる。2. Description of the Related Art As a semiconductor device, a semiconductor device 100 shown in FIG. 7 is used. The semiconductor device 100 shown in FIG.
Is a conductor pattern 106 formed on the circuit board 104,
Of 106 ..., The electrode terminals of the semiconductor element 108 are electrically connected to the connection pads of the conductor pattern 106 formed on one surface side thereof by the flip chip method. On the other surface side of the circuit board 104, solder balls 102, 102, ... As external connection terminals are provided on the connection pads of the conductor pattern 106 formed on the other surface side.
In this way, the semiconductor element 108 mounted on the one surface side of the circuit board 104 is housed in the recess 112 formed in the metal heat dissipation plate 110, and the opening surface side of the recess 112 of the heat dissipation plate 110 is the circuit board 104. The one surface is adhered by an adhesive agent 116 to be integrated with each other. The semiconductor element 108 housed in the recess 112 of the heat sink 110 is filled with a heat transfer resin 114 containing a heat transfer material such as silver between the back surface side and the bottom surface of the recess 112.
The heat transfer from the heat sink 110 to the heat sink 110 is improved. The electrode terminals and the like of the semiconductor element 108 mounted on the one surface side of the circuit board 104 are sealed with potting resin or the like.
【０００３】[0003]
【発明が解決しようとする課題】図７に示す半導体装置
１００によれば、半導体素子１０８で発生した熱は、そ
の背面側の伝熱性樹脂１１４を介して放熱板１１０に伝
熱されて放熱され、半導体素子１０８の温度上昇を抑制
し、熱に因る半導体素子１０８の誤動作等を防止でき
る。しかしながら、図７に示す半導体装置１００に用い
られている放熱板１１０には、半導体素子１０８を収容
する凹部１１２を形成することを要し、その製造コスト
も高くなる。更に、放熱板１１０には、半導体素子１０
８を収容する凹部１１２を形成するため、放熱板１１０
の厚さが半導体素子１０８よりも厚くなるため、半導体
装置１００も厚くなる。また、図７に示す半導体装置１
００は、回路基板１０４に半導体素子１０８をフリップ
チップ方式で実装した後、放熱板１１０を回路基板１０
４に接合することを要し、半導体装置１００の製造工程
を複雑化する。そこで、本発明の課題は、簡単な構造の
放熱板を用いて放熱性が向上された薄い半導体装置を容
易に製造し得る半導体装置用パッケージ並びに半導体装
置及びその製造方法を提供することにある。According to the semiconductor device 100 shown in FIG. 7, the heat generated in the semiconductor element 108 is transferred to the heat radiating plate 110 via the heat transfer resin 114 on the back side thereof and is radiated. The temperature rise of the semiconductor element 108 can be suppressed, and malfunction of the semiconductor element 108 due to heat can be prevented. However, the heat dissipation plate 110 used in the semiconductor device 100 shown in FIG. 7 needs to be provided with the recess 112 that accommodates the semiconductor element 108, and the manufacturing cost thereof increases. Further, the heat dissipation plate 110 includes the semiconductor element 10
The heat sink 110 to form the recess 112 that accommodates
Is thicker than the semiconductor element 108, the semiconductor device 100 is also thicker. Further, the semiconductor device 1 shown in FIG.
00 mounts the semiconductor element 108 on the circuit board 104 by the flip chip method and then mounts the heat sink 110 on the circuit board 10.
4 is required, which complicates the manufacturing process of the semiconductor device 100. Therefore, an object of the present invention is to provide a semiconductor device package, a semiconductor device, and a method for manufacturing the same, which can easily manufacture a thin semiconductor device having improved heat dissipation using a heat dissipation plate having a simple structure.
【０００４】[0004]
【課題を解決するための手段】本発明者は、前記課題を
解決すべく検討した結果、半導体素子の電極端子と接続
される半導体素子用接続パッドを具備する導体パターン
が形成された導体パターン形成層を一面側に形成した放
熱板と、一面側に外部接続端子用パッドを形成した枠状
の回路基板とを、形成された半導体素子を収容するキャ
ビティの底面に半導体素子用接続パッドが露出するよう
に積層し、両者の導体パターンを電気的に接合した半導
体装置用パッケージによれば、両面が平坦面の放熱板を
用いることができ、半導体素子の実装が容易で且つ形成
された半導体装置の厚さを薄くできることを知り、本発
明に到達した。すなわち、本発明は、搭載される半導体
素子の電極端子と電気的に接続される半導体素子用接続
パッドを具備する導体パターンが形成された導体パター
ン形成層が、一面側の平坦面上に形成された金属製の放
熱板と、一面側に外部接続端子用パッドが形成され、他
面側が前記導体パターン形成層に接合された枠状の回路
基板とから成る半導体装置用パッケージであって、前記
導体パターン形成層の導体パターンと回路基板に形成さ
れた導体パターンとが電気的に接続され、前記導体パタ
ーン形成層に形成された半導体素子用接続パッドに、半
導体素子の電極端子がフリップチップ方式で電気的に接
続されたとき、前記半導体素子を収容し得るキャビティ
が、前記導体パターン形成層と枠状の回路基板とから形
成されていることを特徴とする半導体装置用パッケージ
にある。As a result of studies to solve the above problems, the present inventor has formed a conductor pattern in which a conductor pattern having a semiconductor device connection pad connected to an electrode terminal of a semiconductor device is formed. A heat dissipation plate having a layer formed on one surface side and a frame-shaped circuit board having pads for external connection terminals formed on the one surface side, the connection pad for semiconductor element is exposed on the bottom surface of the cavity for housing the formed semiconductor element According to the semiconductor device package in which both conductor patterns are electrically joined to each other as described above, a heat dissipation plate having flat surfaces on both sides can be used, and a semiconductor device in which a semiconductor element can be easily mounted and formed. The inventors have reached the present invention by knowing that the thickness can be reduced. That is, according to the present invention, a conductor pattern forming layer having a conductor pattern having a semiconductor element connection pad electrically connected to an electrode terminal of a mounted semiconductor element is formed on a flat surface on one side. A heat sink made of metal, and a frame-shaped circuit board having pads for external connection terminals formed on one surface side and joined to the conductor pattern forming layer on the other surface side, wherein the conductor The conductor pattern of the pattern forming layer and the conductor pattern formed on the circuit board are electrically connected, and the electrode terminals of the semiconductor element are electrically connected to the semiconductor element connection pads formed on the conductor pattern forming layer by a flip chip method. A cavity capable of accommodating the semiconductor element, when electrically connected, is formed from the conductor pattern forming layer and a frame-shaped circuit board. In the package for the body system.
【０００５】また、本発明は、搭載された半導体素子の
電極端子と電気的に接続された半導体素子用接続パッド
を具備する導体パターンが形成された導体パターン形成
層が、一面側の平坦面上に形成された金属製の放熱板
と、一面側に外部接続端子用パッドが形成され、他面側
が前記導体パターン形成層に接合された枠状の回路基板
とから成る半導体装置であって、前記導体パターン形成
層に形成された導体パターンと回路基板に形成された導
体パターンとが電気的に接続され、前記導体パターン形
成層と回路基板とから成るキャビティの底面に露出する
半導体素子用接続パッドに、前記キャビティ内に収容さ
れた半導体素子の電極端子がフリップチップ方式で電気
的に接続されていることを特徴とする半導体装置にあ
る。更に、本発明は、前記半導体装置用パッケージに形
成されたキャビティの底面に露出する、金属製の放熱板
の一面側に形成された導体パターン形成層の半導体素子
用接続パッドに、半導体素子の電極端子をフリップチッ
プ方式で電気的に接続することを特徴とする半導体装置
の製造方法でもある。Further, according to the present invention, a conductor pattern forming layer having a conductor pattern is provided on a flat surface on one surface side, the layer including a semiconductor element connection pad electrically connected to an electrode terminal of a mounted semiconductor element. A semiconductor device comprising a metal heat dissipation plate formed on the outer surface, and a frame-shaped circuit board having external connection terminal pads formed on one surface side and the other surface side joined to the conductor pattern forming layer, A semiconductor element connection pad exposed on the bottom surface of a cavity formed by the conductor pattern forming layer and the circuit board, in which the conductor pattern formed on the conductor pattern forming layer and the conductor pattern formed on the circuit board are electrically connected. The semiconductor device is characterized in that the electrode terminals of the semiconductor element housed in the cavity are electrically connected by a flip chip method. Furthermore, the present invention provides a semiconductor element connection pad of a conductor pattern forming layer formed on one surface side of a metal heat dissipation plate exposed at a bottom surface of a cavity formed in the semiconductor device package, and an electrode of the semiconductor element. The semiconductor device manufacturing method is also characterized in that the terminals are electrically connected by a flip chip method.
【０００６】かかる本発明において、導体パターン形成
層に形成された導体パターンと回路基板に形成された導
体パターンとの電気的な接続を、前記導体パターン形成
層及び回路基板の各接合面に形成された導体パターンの
一方に立設されたバンプの先端面を、両接合面を接着す
る接着剤層を貫通して他方の導体パターンに当接して行
うことが容易である。また、回路基板の外部接続端子用
パッドの形成面側には、キャビティの底面に露出する導
体パターン形成層の半導体素子用接続パッドに、電極端
子がフリップチップ方式で接続された第１半導体素子の
背面に、第２半導体素子の背面が接合されたとき、前記
第２半導体素子の電極端子とワイヤボンディングされる
ワイヤボンディング用接続パッドを形成することによ
り、一個の半導体装置用パッケージに複数個の半導体素
子を搭載できる。更に、放熱板の一面側に形成された導
体パターン形成層に半導体素子を搭載したとき、前記半
導体素子と放熱板とを熱的に接続するサーマルヴィア
を、前記導体パターン形成層を貫通して形成することに
よって、半導体素子で発生した熱を更に迅速に放熱でき
る。In the present invention, an electrical connection between the conductor pattern formed on the conductor pattern forming layer and the conductor pattern formed on the circuit board is formed on each of the joint surfaces of the conductor pattern forming layer and the circuit board. It is easy to make the tip end surface of the bump erected on one of the conductor patterns, by penetrating the adhesive layer for adhering the both joint surfaces and contacting the other conductor pattern. Further, on the side of the external connection terminal pad formation surface of the circuit board, the first semiconductor element of which the electrode terminals are connected in a flip chip method to the semiconductor element connection pad of the conductor pattern forming layer exposed on the bottom surface of the cavity. When a back surface of the second semiconductor element is joined to the back surface, a plurality of semiconductors are packaged in a single semiconductor device package by forming wire bonding connection pads that are wire-bonded to the electrode terminals of the second semiconductor element. Elements can be mounted. Further, when a semiconductor element is mounted on the conductor pattern forming layer formed on one surface side of the heat sink, a thermal via that thermally connects the semiconductor element and the heat sink is formed through the conductor pattern forming layer. By doing so, the heat generated in the semiconductor element can be released more quickly.
【０００７】本発明によれば、放熱板の一面側の平坦面
に形成した、半導体素子用接続パッドを具備する導体パ
ターンが形成された導体パターン形成層と枠状の回路基
板とを接合し、底面に半導体素子用接続パッドが露出す
るキャビティを形成した半導体装置用パッケージを形成
する。このため、半導体素子をキャビティに収容してフ
リップチップ方式で半導体素子の電極端子と半導体素子
用接続パッドとを電気的に接続して半導体装置を形成で
き、半導体素子を搭載した後、放熱板を装着する操作を
省略できる。また、放熱板に搭載する半導体素子を収容
する凹部等を形成することを要せず、両面が平坦な放熱
板を用いることができ、放熱板の薄化を図ることができ
るため、最終的に得られる半導体装置の薄化を図ること
ができる。更に、この様に両面が平坦な放熱板を用いる
ことができ、半導体素子を収容する凹部が形成された放
熱板と比較して、その製造コストの低減も図ることがで
きる。According to the present invention, the conductor pattern forming layer having the conductor pattern having the semiconductor element connection pads formed on the flat surface on the one surface of the heat sink is joined to the frame-shaped circuit board, A semiconductor device package having a cavity on the bottom surface of which a semiconductor element connection pad is exposed is formed. Therefore, the semiconductor element can be housed in the cavity and the electrode terminals of the semiconductor element and the semiconductor element connection pads can be electrically connected by the flip chip method to form a semiconductor device. The operation of mounting can be omitted. Further, since it is not necessary to form a recess or the like for accommodating the semiconductor element to be mounted on the heat dissipation plate, a heat dissipation plate having flat surfaces on both sides can be used, and the heat dissipation plate can be thinned, so that finally. The thickness of the obtained semiconductor device can be reduced. Further, a heat dissipation plate having flat surfaces on both sides can be used, and the manufacturing cost thereof can be reduced as compared with a heat dissipation plate having a recess for accommodating a semiconductor element.
【０００８】[0008]
【発明の実施の形態】本発明に係る半導体装置の一例を
図１に示す。図１に示す半導体装置１０は、銅等の熱伝
導性が良好な金属製の両面が平坦な放熱板１２の一面側
に形成された導体パターン形成層Ａと枠状の回路基板Ｂ
とが、接着剤層２４によって一体に接合されてキャビテ
ィ２６が形成されている。このキャビティ２６内には、
半導体素子１４が収容されて封止樹脂２８によって封止
されている。かかる導体パターン形成層Ａには、導体パ
ターン１６，１６・・が形成されており、各導体パター
ン１６には、キャビティ２６に収容された半導体素子１
４の電極端子１５と電気的に接続された半導体素子用接
続パッド１８が形成されている。更に、導体パターン形
成層Ａには、搭載された半導体素子１４の放熱用端子１
７，１７・・と一端が接続され、他端が放熱板１２に接
続されるサーマルヴィア２２，２２・・が、導体パター
ン形成層Ａを貫通して形成されている。FIG. 1 shows an example of a semiconductor device according to the present invention. A semiconductor device 10 shown in FIG. 1 includes a conductor pattern forming layer A formed on one surface side of a heat dissipation plate 12 made of a metal such as copper having good thermal conductivity and having flat both surfaces, and a frame-shaped circuit board B.
Are bonded together by an adhesive layer 24 to form a cavity 26. In this cavity 26,
The semiconductor element 14 is housed and sealed with a sealing resin 28. .. are formed in the conductor pattern forming layer A, and the semiconductor element 1 housed in the cavity 26 is formed in each conductor pattern 16.
The semiconductor device connection pads 18 electrically connected to the fourth electrode terminals 15 are formed. Further, on the conductor pattern forming layer A, the heat dissipation terminal 1 of the mounted semiconductor element 14 is provided.
The thermal vias 22, 22, ..., One end of which is connected to the heat radiation plate 12, and the other end of which is connected to the heat dissipation plate 12, are formed penetrating the conductor pattern forming layer A.
【０００９】この様な放熱板１２の一面側に形成された
導体パターン形成層Ａには、一面側に外部接続端子とし
てのはんだボール３０，３０・・が設けられた回路基板
Ｂの他面側が接着剤層２４によって一体に接合されてい
る。また、回路基板Ｂには、導体パターン３４，３４・
・が多層に積層されており、導体パターン３４，３４・
・の相互はスルーホールヴィア３６等により電気的に相
互に接続されている。この回路基板Ｂの一面側に形成さ
れた最外の導体パターン３４には、外部接続端子として
のはんだボール３０が設けられた外部接続端子用パッド
３５が形成されている。かかる導体パターン形成層Ａに
形成された導体パターン１６と回路基板Ｂに形成された
導体パターン３４とは、導体パターン形成層Ａの一面側
と回路基板Ｂの他面側とを接着する接着剤層２４を貫通
するバンプ３２，３２・・によって、電気的に接続され
る。従って、キャビティ２６に収容され、放熱板１２の
一面側に形成された半導体素子用接続パッド１８に接続
された半導体素子１４の電極端子１５と、回路基板Ｂの
一面側に形成されたはんだボール３０とは、導体パター
ン形成層Ａの導体パターン１６、バンプ３２、回路基板
Ｂの導体パターン３４やスルーホールヴィア３６等を介
して電気的に接続されている。In the conductor pattern forming layer A formed on one surface side of the heat dissipation plate 12 as described above, the other surface side of the circuit board B having the solder balls 30, 30 ... They are integrally joined by the adhesive layer 24. Further, on the circuit board B, the conductor patterns 34, 34.
. Are laminated in multiple layers, and the conductor patterns 34, 34.
, Are electrically connected to each other by through-hole vias 36 and the like. On the outermost conductor pattern 34 formed on the one surface side of the circuit board B, an external connection terminal pad 35 provided with a solder ball 30 as an external connection terminal is formed. The conductor pattern 16 formed on the conductor pattern forming layer A and the conductor pattern 34 formed on the circuit board B are adhesive layers for bonding one surface side of the conductor pattern forming layer A and the other surface side of the circuit board B. Electrical connection is made by bumps 32, 32 ... Therefore, the electrode terminals 15 of the semiconductor element 14 housed in the cavity 26 and connected to the semiconductor element connection pads 18 formed on the one surface side of the heat dissipation plate 12, and the solder balls 30 formed on the one surface side of the circuit board B. Are electrically connected to each other via the conductor pattern 16 of the conductor pattern forming layer A, the bump 32, the conductor pattern 34 of the circuit board B, the through hole via 36, and the like.
【００１０】図１に示す半導体装置１０は、図２（ａ）
に示す様に、放熱板１２の一面側に形成された導体パタ
ーン形成層Ａと、中央部に矩形の貫通穴３８が形成され
た枠状の回路基板Ｂとが接合されて一体化され、図２
（ｂ）に示す半導体装置用パッケージ４０のキャビティ
２６内に、半導体素子１４を収容して形成される。かか
る半導体装置用パッケージ４０を形成する放熱板１２の
一面側に形成された導体パターン形成層Ａは、図３
（ａ）に示す様に、両面が平坦面に形成された金属製の
放熱板１２を用い、その一面側の全面に樹脂層１１を形
成する［図３（ｂ）の工程］。この樹脂層１１のサーマ
ルヴィア２２，２２・・を形成する個所に、レーザ等に
より底面に放熱板１２の面が露出するヴィア穴２２ａ，
２２ａ・・を形成した後［図３（ｃ）の工程］、ヴィア
穴２２ａ，２２ａ・・の底面及び内壁面を含む樹脂層１
１の全面に、無電解めっきにより形成した薄銅層上に放
熱板１２を給電層とする電解めっきにより、銅層１６ａ
を形成する［図３（ｄ）の工程］。次いで、銅層１６ａ
にフォトリソ法等の公知の方法により、導体パターン１
６やサーマルヴィア２２，２２・・のパッド部等を形成
する［図３（ｅ）の工程］ことにより、放熱板１２の一
面側に導体パターン形成層Ａを形成できる。尚、必要に
応じて図３（ｂ）〜（ｅ）の工程を繰り返すことによ
り、放熱板１２の一面側に、複数の導体パターン１６が
積層された多層の導体パターン形成層Ａを形成できる。The semiconductor device 10 shown in FIG. 1 is shown in FIG.
As shown in FIG. 3, the conductor pattern forming layer A formed on the one surface side of the heat dissipation plate 12 and the frame-shaped circuit board B in which the rectangular through hole 38 is formed in the center are joined and integrated. Two
The semiconductor element 14 is housed and formed in the cavity 26 of the semiconductor device package 40 shown in FIG. The conductor pattern forming layer A formed on the one surface side of the heat dissipation plate 12 forming the semiconductor device package 40 is as shown in FIG.
As shown in (a), a metal heat dissipation plate 12 having both flat surfaces is used, and a resin layer 11 is formed on the entire surface on one side thereof [step of FIG. 3 (b)]. At locations where the thermal vias 22, 22, ... Of the resin layer 11 are formed, via holes 22a through which the surface of the heat dissipation plate 12 is exposed at the bottom surface by a laser or the like.
After forming 22a ... [Process of FIG. 3 (c)], the resin layer 1 including the bottom surfaces and inner wall surfaces of the via holes 22a, 22a.
The copper layer 16a is formed on the entire surface of No. 1 by electrolytic plating using a heat dissipation plate 12 as a power feeding layer on a thin copper layer formed by electroless plating.
Are formed [step of FIG. 3 (d)]. Then, the copper layer 16a
The conductor pattern 1 is formed by a known method such as a photolithography method.
The conductor pattern forming layer A can be formed on the one surface side of the heat dissipation plate 12 by forming the pad portion of 6 or the thermal vias 22, 22 ... [Step of FIG. 3 (e)]. By repeating the steps of FIGS. 3B to 3E as necessary, a multilayer conductor pattern forming layer A in which a plurality of conductor patterns 16 are laminated can be formed on one surface side of the heat dissipation plate 12.
【００１１】更に、図２（ａ）に示す導体パターン形成
層Ａには、回路基板Ｂと接着する接着剤層２４を突き破
るバンプ３２，３２・・を立設する。このバンプ３２，
３２・・は、図３（ｅ）で形成した導体パターン形成層
Ａ上に、はんだボールやワイヤボンダによるスタッドバ
ンプによって形成できる。かかる導体パターン形成層Ａ
に接合される回路基板Ｂは、樹脂板の両面に銅箔が接合
された両面銅貼板を用い、図４（ａ）〜（ｃ）の工程で
形成できる。先ず、複数枚の両面銅貼板の各銅箔に、所
望の導体パターン３４ａ等をフォトリソ法等の公知の方
法で形成すると共に、中央部に矩形の貫通穴３８ａを穿
設した後［図４（ａ）の工程］、両面銅貼板の各々に形
成した導体パターン３４ａ，３４ａ・・を接着剤３７を
介して多層に積層する［図４（ｂ）の工程］。次いで、
積層した導体パターン３４ａ，３４ａ・・を互いに電気
的に接続するスルーホールヴィア３６，３６・・を形成
すべく、スルーホール３６ａ，３６ａ・・を形成する
［図４（ｃ）の工程］。その後、スルーホール３６ａ，
３６ａ・・内に導電性樹脂の充填又はスルーホールめっ
き等を施し、スルーホールヴィア３６，３６・・を形成
する。この様にして得られた回路基板Ｂの外部接続端子
用パッド３５が形成された面には、外部接続端子用パッ
ド３５を除いてソルダレジストを塗布してもよい。Further, on the conductor pattern forming layer A shown in FIG. 2 (a), bumps 32, 32, ... Breaking through the adhesive layer 24 adhered to the circuit board B are provided upright. This bump 32,
.. can be formed by stud bumps using solder balls or wire bonders on the conductor pattern forming layer A formed in FIG. 3 (e). Such a conductor pattern forming layer A
The circuit board B to be joined to can be formed by the steps of FIGS. 4A to 4C using a double-sided copper-clad plate in which copper foil is joined to both sides of a resin plate. First, after a desired conductor pattern 34a and the like are formed on each copper foil of a plurality of double-sided copper-clad plates by a known method such as a photolithography method, a rectangular through hole 38a is formed at the center [FIG. (Step (a)], and the conductive patterns 34a, 34a, ... Formed on each of the double-sided copper-clad boards are laminated in multiple layers with an adhesive 37 [step (FIG. 4B)]. Then
.. to form the through hole vias 36, 36 .. which electrically connect the laminated conductor patterns 34a, 34a .. .. to each other [step of FIG. 4 (c)]. After that, through holes 36a,
.. are filled with a conductive resin or through-hole plating is performed to form through-hole vias 36 ,. The surface of the circuit board B thus obtained on which the pads 35 for external connection terminals are formed may be coated with solder resist except for the pads 35 for external connection terminals.
【００１２】この様にして形成された放熱板１２の一面
側に形成された導体パターン形成層Ａと回路基板Ｂとを
用い、図１に示す半導体装置１０を形成するには、先
ず、図２（ｂ）に示す様に、導体パターン形成層Ａの導
体パターン１６と回路基板Ｂの導体パターン３４とをバ
ンプ３２によって電気的に接続しつつ、接着剤層２４に
よって接合して一体化して半導体装置用パッケージ４０
を形成する。次いで、この半導体装置用パッケージ４０
のキャビティ２６内に、半導体素子１４を収容し、キャ
ビティ２６の底面に露出する導体パターン１６，１６・
・に形成された半導体素子用接続パッド１８，１８・・
の各々と半導体素子１４の電極端子１５，１５・・の各
々とをフリップチップ方式で電気的に接合する。同時
に、半導体素子１４に設けられた放熱用端子１７，１７
・・の各々も、対応するサーマルヴィア２２に接合す
る。その後、キャビティ２６内に封止樹脂２８をポッテ
ィング等により注入し、半導体素子１４を樹脂封止し
て、半導体装置１０を形成できる。In order to form the semiconductor device 10 shown in FIG. 1 by using the conductor pattern forming layer A and the circuit board B formed on the one surface side of the heat dissipation plate 12 thus formed, first, referring to FIG. As shown in (b), the conductor pattern 16 of the conductor pattern forming layer A and the conductor pattern 34 of the circuit board B are electrically connected by the bumps 32 while being joined and integrated by the adhesive layer 24 to form a semiconductor device. Package 40
To form. Next, this semiconductor device package 40
The semiconductor patterns 14 are housed in the cavities 26 of the conductor patterns 16, 16
Connection pads for semiconductor elements 18, 18 formed on
Are electrically connected to the electrode terminals 15, 15 ... Of the semiconductor element 14 by a flip chip method. At the same time, the heat dissipation terminals 17, 17 provided on the semiconductor element 14
.. are also joined to the corresponding thermal vias 22. After that, the sealing resin 28 is injected into the cavity 26 by potting or the like, and the semiconductor element 14 is resin-sealed to form the semiconductor device 10.
【００１３】図１に示す半導体装置１０では、半導体素
子１４で発生した熱は、サーマルヴィア２２，２２・・
や導体パターン１６等を介して迅速に放熱板１２に伝熱
され、放熱板１２から放熱される。しかも、放熱板１２
には、搭載する半導体素子１４を収容する凹部等を形成
することを要せず、両面が平坦な放熱板１２を用いるこ
とができ、放熱板１２の薄化を図ることができる。この
ため、得られる半導体装置１０の薄化を図ることができ
る。更に、予め放熱板１２の一面側に形成された導体パ
ターン形成層Ａと回路基板Ｂとを接合し、底面に半導体
素子用接続パッド１８，１８・・が露出するキャビティ
２６を形成した半導体装置用パッケージを形成する。こ
のため、半導体素子１４をキャビティに収容してフリッ
プチップ方式で半導体素子１４の電極端子１５，１５・
・と半導体素子用接続パッド１８，１８・・とを電気的
に接続して半導体装置を形成できる。したがって、半導
体素子を搭載した後、放熱板を装着する操作を省略でき
ため、両面が平坦な放熱板１２を用いることができるこ
とと相俟って、半導体装置の製造コストの低減も図るこ
とができる。In the semiconductor device 10 shown in FIG. 1, the heat generated in the semiconductor element 14 is generated by the thermal vias 22, 22 ,.
The heat is rapidly transferred to the heat radiating plate 12 via the conductor pattern 16 and the like, and is radiated from the heat radiating plate 12. Moreover, the heat sink 12
In this case, it is not necessary to form a recess or the like for accommodating the mounted semiconductor element 14, and the heat dissipation plate 12 having flat surfaces on both sides can be used, and the heat dissipation plate 12 can be thinned. Therefore, the thickness of the obtained semiconductor device 10 can be reduced. Further, for the semiconductor device, the conductor pattern forming layer A previously formed on the one surface side of the heat dissipation plate 12 and the circuit board B are joined to each other, and the cavity 26 exposing the semiconductor element connection pads 18, 18 ... Is formed on the bottom surface. Form the package. Therefore, the semiconductor element 14 is housed in the cavity and the electrode terminals 15, 15 ...
. And the semiconductor element connection pads 18, 18 ... Can be electrically connected to form a semiconductor device. Therefore, since the operation of mounting the heat sink after mounting the semiconductor element can be omitted, the manufacturing cost of the semiconductor device can be reduced in combination with the fact that the heat sink 12 having flat surfaces can be used. .
【００１４】図１に示す半導体装置１０では、一個の半
導体素子１４がキャビティ２６内に収容されているが、
図５及び図６に示す様に、二個の半導体素子１４ａ，１
４ｂがキャビティ２６内に収容されていてもよい。かか
る半導体素子１４ａ，１４ｂのうち、半導体素子１４ａ
は、その電極端子１５，１５・・や放熱用端子１７，１
７・・は、放熱板１２の一面側に形成された導体パター
ン形成層Ａに形成された半導体素子用接続パッド１８や
サーマルヴィア２２にフリップチップ方式で接続されて
いる。一方、半導体素子１４ｂは、その背面が、導体パ
ターン形成層Ａに搭載された半導体素子１４ａの背面側
に接着剤４４により接合されており、その電極端子は、
図５に示す様に、回路基板Ｂの外部接続端子用パッド３
５の形成面に形成されたワイヤボンディング用接続パッ
ド４６にワイヤ４２により電気的に接続されている。こ
のワイヤボンディング用接続パッド４６は、図６に示す
様に、回路基板Ｂのキャビティ２６の内壁面に形成した
段差面に形成してもよい。また、半導体素子１４ａの背
面に接合される半導体素子１４ｂとしては、半導体素子
１４ａよりも発熱量の少ない半導体素子を用いることが
好ましい。ここで、発熱量が半導体素子１４ａと同等程
度の半導体素子１４ｂを用いる場合には、両者を接合す
る接着剤４４としては、伝熱性が良好な金属粉が配合さ
れた伝熱性接着剤を用いることが好ましい。半導体素子
１４ｂで発生した熱が半導体素子１４ａを介して迅速に
放熱板１２に伝熱され易いからである。尚、図５及び図
６に示す半導体装置を構成する部材のうち、図１に示す
半導体装置１０を構成する部材と同一部材については、
図１と同一番号を付して詳細な説明を省略した。In the semiconductor device 10 shown in FIG. 1, one semiconductor element 14 is housed in the cavity 26.
As shown in FIGS. 5 and 6, the two semiconductor elements 14a, 1
4b may be housed in the cavity 26. Of the semiconductor elements 14a and 14b, the semiconductor element 14a
, Their electrode terminals 15, 15 ...
.. are connected to the semiconductor element connection pads 18 and the thermal vias 22 formed on the conductor pattern forming layer A formed on the one surface side of the heat dissipation plate 12 by a flip chip method. On the other hand, the back surface of the semiconductor element 14b is bonded to the back surface side of the semiconductor element 14a mounted on the conductor pattern forming layer A with an adhesive 44, and its electrode terminal is
As shown in FIG. 5, the external connection terminal pad 3 of the circuit board B
The wires 42 are electrically connected to the connection pads 46 for wire bonding formed on the formation surface of the wire 5. The wire bonding connection pad 46 may be formed on a step surface formed on the inner wall surface of the cavity 26 of the circuit board B, as shown in FIG. Further, as the semiconductor element 14b joined to the back surface of the semiconductor element 14a, it is preferable to use a semiconductor element that generates less heat than the semiconductor element 14a. Here, when the semiconductor element 14b having a heat generation amount similar to that of the semiconductor element 14a is used, as the adhesive 44 for joining the two, a heat conductive adhesive containing a metal powder having good heat conductivity is used. Is preferred. This is because the heat generated in the semiconductor element 14b is likely to be quickly transferred to the heat dissipation plate 12 via the semiconductor element 14a. Among the members constituting the semiconductor device shown in FIGS. 5 and 6, the same members as those constituting the semiconductor device 10 shown in FIG.
The same numbers as in FIG. 1 are assigned and detailed description is omitted.
【００１５】以上、説明した図１〜図６に示す半導体装
置や半導体装置用パッケージにおいて、放熱板１２の一
面側に形成した導体パターン形成層Ａと回路基板Ｂとの
導体パターンを電気的に接続するバンプ３２，３２・・
を導体パターン形成層Ａ側に設けているが、回路基板Ｂ
側に設けてもよい。また、導体パターン形成層Ａには、
サーマルヴィア２２，２２・・を形成しているが、半導
体素子１４の発熱量が少ない場合には、不要である。In the semiconductor device and the semiconductor device package shown in FIGS. 1 to 6 described above, the conductor patterns of the conductor pattern forming layer A and the circuit board B formed on one surface of the heat dissipation plate 12 are electrically connected. Bumps 32, 32 ...
Is provided on the conductor pattern forming layer A side, but the circuit board B
It may be provided on the side. In addition, in the conductor pattern forming layer A,
Although the thermal vias 22 are formed, they are not necessary when the amount of heat generated by the semiconductor element 14 is small.
【００１６】[0016]
【発明の効果】本発明によれば、簡単な構造の放熱板を
用いて放熱性が向上された薄い半導体装置を容易に製造
することができ、携帯電話等に用いる半導体装置の薄型
化等の要請に応えることができる。According to the present invention, it is possible to easily manufacture a thin semiconductor device having improved heat dissipation using a heat dissipation plate having a simple structure, and to reduce the thickness of a semiconductor device used for a mobile phone or the like. Can respond to requests.
【図１】本発明に係る半導体装置の一例を説明するため
の概略断面図である。FIG. 1 is a schematic cross-sectional view for explaining an example of a semiconductor device according to the present invention.
【図２】図１に示す半導体装置１０の製造方法を説明す
る説明図である。FIG. 2 is an explanatory diagram illustrating a method of manufacturing the semiconductor device 10 shown in FIG.
【図３】図２に示す導体パターン形成層Ａの製造工程を
説明する工程図である。3A to 3C are process diagrams illustrating a manufacturing process of the conductor pattern forming layer A shown in FIG.
【図４】図２に示す回路基板Ｂの製造工程を説明する工
程図である。4A to 4C are process diagrams illustrating a manufacturing process of the circuit board B shown in FIG.
【図５】本発明に係る半導体装置の他の例を説明するた
めの概略断面図である。FIG. 5 is a schematic cross-sectional view for explaining another example of the semiconductor device according to the present invention.
【図６】本発明に係る半導体装置の一例を説明するため
の概略断面図である。FIG. 6 is a schematic cross-sectional view for explaining an example of a semiconductor device according to the present invention.
【図７】従来の半導体装置を説明するための概略断面図
である。FIG. 7 is a schematic cross-sectional view for explaining a conventional semiconductor device.
１０ 半導体装置 １２ 放熱板 １４，１４ａ，１４ｂ 半導体素子 １５ 電極端子 １６，３４ 導体パターン １７ 放熱用端子 １８ 半導体素子用接続パッド ２２ サーマルヴィア ２４ 接着剤層 ２６ キャビティ ２８ 封止樹脂 ３０ はんだバンプ（外部接続用端子） ３２ バンプ ３５ 外部接続端子用パッド ３６ スルーホールヴィア ４０ 半導体装置用パッケージ ４２ ワイヤ ４６ ワイヤボンディング用接続パッド Ａ 導体パターン形成層 Ｂ 回路基板 10 Semiconductor device 12 Heat sink 14, 14a, 14b Semiconductor element 15 electrode terminals 16,34 Conductor pattern 17 Heat dissipation terminal 18 Semiconductor element connection pads 22 Thermal Via 24 Adhesive layer 26 cavities 28 Sealing resin 30 Solder bump (terminal for external connection) 32 bumps 35 Pad for external connection terminal 36 Through Hole Via 40 Semiconductor device package 42 wire 46 Connection pad for wire bonding A conductor pattern forming layer B circuit board
フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 25/18 Continuation of front page (51) Int.Cl. 7 Identification code FI theme code (reference) H01L 25/18
Claims (9)
的に接続される半導体素子用接続パッドを具備する導体
パターンが形成された導体パターン形成層が、一面側の
平坦面上に形成された金属製の放熱板と、 一面側に外部接続端子用パッドが形成され、他面側が前
記導体パターン形成層に接合された枠状の回路基板とか
ら成る半導体装置用パッケージであって、 前記導体パターン形成層の導体パターンと回路基板に形
成された導体パターンとが電気的に接続され、 前記導体パターン形成層に形成された半導体素子用接続
パッドに、半導体素子の電極端子がフリップチップ方式
で電気的に接続されたとき、前記半導体素子を収容し得
るキャビティが、前記導体パターン形成層と枠状の回路
基板とから形成されていることを特徴とする半導体装置
用パッケージ。1. A conductor pattern forming layer, on which a conductor pattern is formed, including a semiconductor device connection pad electrically connected to an electrode terminal of a mounted semiconductor device, is formed on one flat surface. A semiconductor device package comprising a metal heat sink and a frame-shaped circuit board having pads for external connection terminals formed on one surface side and being joined to the conductor pattern forming layer on the other surface side. The conductor pattern of the forming layer and the conductor pattern formed on the circuit board are electrically connected, and the electrode terminals of the semiconductor element are electrically connected to the semiconductor element connection pads formed on the conductor pattern forming layer by a flip chip method. A semiconductor device, wherein a cavity capable of accommodating the semiconductor element is formed from the conductor pattern forming layer and a frame-shaped circuit board when connected to the semiconductor device. Storage package.
ターンと回路基板に形成された導体パターンとの電気的
な接続が、前記導体パターン形成層及び回路基板の各接
合面に形成された導体パターンの一方に立設されたバン
プの先端面が、両接合面を接着する接着剤層を貫通して
他方の導体パターンに当接してなされている請求項１記
載の半導体装置用パッケージ。2. A conductor pattern formed on each of the bonding surfaces of the conductor pattern forming layer and the circuit board by electrical connection between the conductor pattern formed on the conductor pattern forming layer and the conductor pattern formed on the circuit board. 2. The semiconductor device package according to claim 1, wherein the tip end surface of the bump erected on one side penetrates through the adhesive layer that adheres the two bonding surfaces and is in contact with the other conductor pattern.
面側には、キャビティの底面に露出する導体パターン形
成層の半導体素子用接続パッドに、電極端子がフリップ
チップ方式で接続された第１半導体素子の背面に、第２
半導体素子の背面が接合されたとき、前記第２半導体素
子の電極端子とワイヤボンディングされるワイヤボンデ
ィング用接続パッドが形成されている請求項１又は請求
項２記載の半導体装置用パッケージ。3. A first flip-chip method in which an electrode terminal is connected to a semiconductor element connection pad of a conductor pattern forming layer exposed on the bottom surface of the cavity on the side of the external connection terminal pad formation surface of the circuit board. On the back surface of the semiconductor element, the second
3. The package for a semiconductor device according to claim 1, wherein a wire bonding connection pad that is wire bonded to the electrode terminal of the second semiconductor element when the back surface of the semiconductor element is bonded is formed.
ン形成層に半導体素子が搭載されたとき、前記半導体素
子と放熱板とを熱的に接続するサーマルヴィアが、前記
導体パターン形成層を貫通して形成されている請求項１
〜３のいずれか一項記載の半導体装置用パッケージ。4. When a semiconductor element is mounted on a conductor pattern forming layer formed on one surface side of the heat sink, a thermal via that thermally connects the semiconductor element and the heat sink forms the conductor pattern forming layer. It is formed so as to penetrate therethrough.
The semiconductor device package according to any one of claims 1 to 3.
的に接続された半導体素子用接続パッドを具備する導体
パターンが形成された導体パターン形成層が、一面側の
平坦面上に形成された金属製の放熱板と、 一面側に外部接続端子用パッドが形成され、他面側が前
記導体パターン形成層に接合された枠状の回路基板とか
ら成る半導体装置であって、 前記導体パターン形成層に形成された導体パターンと回
路基板に形成された導体パターンとが電気的に接続さ
れ、 前記導体パターン形成層と回路基板とから成るキャビテ
ィの底面に露出する半導体素子用接続パッドに、前記キ
ャビティ内に収容された半導体素子の電極端子がフリッ
プチップ方式で電気的に接続されていることを特徴とす
る半導体装置。5. A conductor pattern forming layer, on which a conductor pattern is formed, including a semiconductor element connection pad electrically connected to an electrode terminal of a mounted semiconductor element, is formed on one flat surface. A semiconductor device comprising a metal heat sink and a frame-shaped circuit board having pads for external connection terminals formed on one surface side and the other surface side being joined to the conductor pattern forming layer, wherein the conductor pattern forming layer The conductor pattern formed on the circuit board and the conductor pattern formed on the circuit board are electrically connected, and the semiconductor element connection pad exposed on the bottom surface of the cavity formed of the conductor pattern forming layer and the circuit board is connected to the inside of the cavity. A semiconductor device in which the electrode terminals of the semiconductor element housed in are electrically connected by a flip-chip method.
ターンと回路基板に形成された導体パターンとの電気的
な接続が、前記導体パターン形成層及び回路基板のに形
成された各接合面に形成された導体パターンの一方に立
設されたバンプの先端面が、両接合面を接着する接着剤
層を貫通して他方の導体パターンに当接してなされてい
る請求項５記載の半導体装置用パッケージ。6. An electrical connection between the conductor pattern formed on the conductor pattern forming layer and the conductor pattern formed on the circuit board is formed on each joint surface formed on the conductor pattern forming layer and the circuit board. 6. The semiconductor device package according to claim 5, wherein a tip end surface of the bump erected on one of the formed conductor patterns penetrates an adhesive layer that adheres both bonding surfaces and is in contact with the other conductor pattern. .
面側には、導体パターン形成層の接続パッドにフリップ
チップ方式で接続された第１半導体素子の背面に接合さ
れた第２半導体素子の電極端子とワイヤボンディングさ
れたワイヤボンディング用の接続パッドが形成されてい
る請求項５又は請求項６記載の半導体装置。7. A second semiconductor element bonded to a back surface of a first semiconductor element, which is flip-chip connected to a connection pad of a conductor pattern forming layer, on a side of a circuit board on which an external connection terminal pad is formed. 7. The semiconductor device according to claim 5, wherein a connection pad for wire bonding, which is wire-bonded to the electrode terminal, is formed.
素子と放熱板とを熱的に接続するサーマルヴィアが、前
記導体パターン形成層を貫通して形成されている請求項
５〜７のいずれか一項記載の半導体装置。8. A thermal via for thermally connecting a semiconductor element mounted on a conductor pattern forming layer and a heat sink is formed penetrating the conductor pattern forming layer. The semiconductor device according to claim 1.
に形成されたキャビティの底面に露出する、金属製の放
熱板の一面側に形成された導体パターン形成層の半導体
素子用接続パッドに、半導体素子の電極端子をフリップ
チップ方式で電気的に接続することを特徴とする半導体
装置の製造方法。9. The semiconductor element connection pad of the conductor pattern forming layer formed on one surface of the metal heat dissipation plate exposed on the bottom surface of the cavity formed in the semiconductor device package according to claim 1, A method of manufacturing a semiconductor device, comprising electrically connecting the electrode terminals of the element by a flip chip method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002023106A JP2003224228A (en) | 2002-01-31 | 2002-01-31 | Package for semiconductor device, semiconductor device and its producing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002023106A JP2003224228A (en) | 2002-01-31 | 2002-01-31 | Package for semiconductor device, semiconductor device and its producing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003224228A true JP2003224228A (en) | 2003-08-08 |
| JP2003224228A5 JP2003224228A5 (en) | 2005-06-16 |
Family
ID=27745908
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002023106A Pending JP2003224228A (en) | 2002-01-31 | 2002-01-31 | Package for semiconductor device, semiconductor device and its producing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003224228A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6870249B2 (en) | 2002-12-24 | 2005-03-22 | Oki Electric Industry Co., Ltd. | Semiconductor device and manufacturing method thereof |
| JP2005340578A (en) * | 2004-05-28 | 2005-12-08 | Sanyo Electric Co Ltd | Circuit device |
| JP2008103615A (en) * | 2006-10-20 | 2008-05-01 | Shinko Electric Ind Co Ltd | Electronic component mounting multilayer wiring board and its manufacturing method |
| KR100907639B1 (en) * | 2007-12-20 | 2009-07-14 | 삼성전기주식회사 | Manufacturing method of multilayer printed circuit board and semiconductor plastic package using same |
| JP2011187919A (en) * | 2010-03-05 | 2011-09-22 | Samsung Electro-Mechanics Co Ltd | Electronic element built-in printed circuit board and method of manufacturing the same |
| JP2015026777A (en) * | 2013-07-29 | 2015-02-05 | 富士通株式会社 | Electronic component |
| KR101517541B1 (en) * | 2006-12-07 | 2015-05-04 | 스태츠 칩팩 아이엔씨. | Multi-layer semiconductor package |
-
2002
- 2002-01-31 JP JP2002023106A patent/JP2003224228A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6870249B2 (en) | 2002-12-24 | 2005-03-22 | Oki Electric Industry Co., Ltd. | Semiconductor device and manufacturing method thereof |
| JP2005340578A (en) * | 2004-05-28 | 2005-12-08 | Sanyo Electric Co Ltd | Circuit device |
| JP4511245B2 (en) * | 2004-05-28 | 2010-07-28 | 三洋電機株式会社 | Circuit equipment |
| JP2008103615A (en) * | 2006-10-20 | 2008-05-01 | Shinko Electric Ind Co Ltd | Electronic component mounting multilayer wiring board and its manufacturing method |
| US8222747B2 (en) | 2006-10-20 | 2012-07-17 | Shinko Electric Industries Co., Ltd. | Multilayer wiring substrate mounted with electronic component and method for manufacturing the same |
| KR101517541B1 (en) * | 2006-12-07 | 2015-05-04 | 스태츠 칩팩 아이엔씨. | Multi-layer semiconductor package |
| KR100907639B1 (en) * | 2007-12-20 | 2009-07-14 | 삼성전기주식회사 | Manufacturing method of multilayer printed circuit board and semiconductor plastic package using same |
| JP2011187919A (en) * | 2010-03-05 | 2011-09-22 | Samsung Electro-Mechanics Co Ltd | Electronic element built-in printed circuit board and method of manufacturing the same |
| JP2015026777A (en) * | 2013-07-29 | 2015-02-05 | 富士通株式会社 | Electronic component |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100698526B1 (en) | Substrate having heat spreading layer and semiconductor package using the same | |
| US8916958B2 (en) | Semiconductor package with multiple chips and substrate in metal cap | |
| JPH0964099A (en) | Semiconductor device and its mounting structure | |
| JP2007123524A (en) | Substrate with built-in electronic part | |
| JPH0917919A (en) | Semiconductor device | |
| WO2006132151A1 (en) | Interposer and semiconductor device | |
| JP2003249607A (en) | Semiconductor device and manufacturing method therefor, circuit board and electronic device | |
| JP4075204B2 (en) | Multilayer semiconductor device | |
| JPH09293808A (en) | Semiconductor device | |
| JP2001085603A (en) | Semiconductor device | |
| JPH10313071A (en) | Electronic part and wiring board device | |
| JP2001308258A (en) | Semiconductor package and method of manufacturing it | |
| JP2003224228A (en) | Package for semiconductor device, semiconductor device and its producing method | |
| JPH11163024A (en) | Semiconductor device and lead frame for assembling the same, and manufacture of the device | |
| KR100280083B1 (en) | Printed Circuit Board and Manufacturing Method of Printed Circuit Board and Semiconductor Package Using the Same | |
| JP3024596B2 (en) | BGA type semiconductor device using film carrier tape | |
| JP3938017B2 (en) | Electronic equipment | |
| JPH09148482A (en) | Semiconductor device | |
| JPH0897336A (en) | Semiconductor device | |
| JPH0358455A (en) | Semiconductor package | |
| JP2001267460A (en) | Semiconductor device | |
| JP2000252414A (en) | Semiconductor device | |
| JPH11135566A (en) | Method for sealing semiconductor bare chip, semiconductor integrated circuit device, and method for manufacturing semiconductor device | |
| JPH0823049A (en) | Semiconductor package | |
| JP2021145068A (en) | Semiconductor device and method of manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20040913 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20040913 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20060324 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060404 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060531 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20060531 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20070130 |