JP2000174165A5 - - Google Patents

Description

【特許請求の範囲】
【請求項１】半導体素子をフェースダウンにて回路基板上に実装した半導体装置において、前記半導体素子面の電極端子部に形成したバンプと接続する前記回路基板の電極端子部の少なくとも直下に、加えられた圧力に応じて容易に変形可能な応力緩和層が設けられていることを特徴とする半導体装置。
【請求項２】前記応力緩和層が絶縁性を有する樹脂で構成されていることを特徴とする請求項１記載の半導体装置。
【請求項３】前記応力緩和層と接する前記回路基板の配線層における、前記回路基板の前記電極端子部の下方に対応する領域には、配線が設けられていないことを特徴とする請求項２記載の半導体装置。
【請求項４】前記応力緩和層と接する前記回路基板の配線層における、前記回路基板の前記電極端子部の下方に対応する領域には、他の配線とは絶縁された配線が設けられていることを特徴とする請求項２記載の半導体装置。
【請求項５】前記応力緩和層と接する前記回路基板の配線層における、前記回路基板の前記電極端子部の下方に対応する領域には、絶縁性を有する板状の金属またはセラミクスが設けられていることを特徴とする請求項２記載の半導体装置。
【請求項６】前記応力緩和層の一部又は全てが、導電性接着剤から構成されていることを特徴とする請求項１記載の半導体装置。
【請求項７】 前記導電性接着剤から構成された前記応力緩和層は、前記回路基板の前記応力緩和層に接する配線層の配線と電気的に接触していることを特徴とする請求項６記載の半導体装置。
【請求項８】 前記導電性接着剤から構成された前記応力緩和層の前記一部は、前記回路基板の前記応力緩和層に接する配線層の配線と電気的に接触し、残る一部は前記回路基板の配線と電気的に接触していないことを特徴とする請求項６記載の半導体装置。
【請求項９】前記半導体素子に形成した前記バンプは、前記半導体素子内部の回路素子形成領域直上にも形成されていることを特徴とする請求項１記載の半導体装置。
【請求項１０】 前記半導体素子の電極端子は、エリアアレイ状に配列されていることを特徴とする請求項１記載の半導体装置。
【請求項１１】請求項１記載の半導体装置の製造方法であって、半導体素子に予め導電性材料から成る一様な高さのバンプを形成しておき、前記バンプの頂頭部に所定量の導電性接着剤を塗布した後、フェースダウンにて、前記半導体素子を回路基板上の所定の位置に載置し、その後、前記半導体素子及び前記回路基板の背面より所定の圧力及び温度を加えることにより、前記導電性接着剤を硬化させて前記半導体素子と前記回路基板との電気的接続を得ることを特徴とする半導体装置の製造方法。
【請求項１２】請求項１記載の半導体装置の製造方法であって、半導体素子に予め導電性材料から成る一様な高さのバンプを形成し、前記バンプの頂頭部に所定量の導電性接着剤を塗布しておき、一方、回路基板上に、前記半導体素子と前記回路基板との電気的接続に関与する前記回路基板の電極端子部にかからない領域に、予め絶縁性を有する樹脂を塗布しておき、前記半導体素子を前記回路基板上の所定の位置にフェースダウンにて載置した後、前記半導体素子及び前記回路基板の背面より所定の圧力及び温度を加えることにより、前記導電性接着剤及び前記絶縁性を有する樹脂を硬化させることにより前記半導体素子と前記回路基板との電気的接続を得ることを特徴とする半導体装置の製造方法。
【請求項１３】前記半導体素子と前記回路基板の隙間部に液状の絶縁樹脂を注入し充填した後、加熱して前記絶縁樹脂を硬化させることを特徴とする請求項１１または１２記載の半導体装置の製造方法。
【請求項１４】請求項１記載の半導体装置の製造方法であって、半導体素子に予め導電性材料から成るバンプを形成しておき、一方、回路基板上の前記半導体素子を載置する所定の位置に絶縁性を有する液状絶縁樹脂を塗布しておき、前記半導体素子をフェースダウンにて前記回路基板の所定の位置に載置した後、前記半導体素子及び前記回路基板の背面より所定の圧力及び温度を加えることにより、前記半導体素子に形成した前記バンプと前記回路基板に形成した電極端子を当接させ、その当接によって、前記半導体素子と前記回路基板との電気的接続を得ると共に、前記液状絶縁樹脂を硬化させることを特徴とする半導体装置の製造方法。
【請求項１５】請求項１記載の半導体装置の製造方法であって、半導体素子には予め導電性材料から成るバンプを形成しておき、一方、回路基板上の前記半導体素子を載置する所定の位置に液状絶縁樹脂中に導電性粒子を分散させた樹脂を塗布しておき、前記半導体素子をフェースダウンにて前記回路基板の所定の位置に載置した後、前記半導体素子及び前記回路基板の背面より所定の圧力及び温度を加えることにより、前記半導体素子に形成した前記バンプと前記回路基板に形成した電極端子を前記導電性粒子を介して当接させ、その当接によって、前記半導体素子と前記回路基板との電気的接続を得ると共に、前記液状絶縁樹脂を硬化させることを特徴とする半導体装置の製造方法。
【請求項１６】前記液状絶縁樹脂は、予めＢステージ硬化させたフィルム状であることを特徴とする請求項１４又は１５記載の半導体装置の製造方法。
【請求項１７】前記回路基板は、通常のプリント基板を形成する工程と、この回路基板の表面に液状の熱硬化型エポキシ樹脂を均一な膜厚となるように塗布する工程と、これを熱処理して硬化する工程と、レーザーやドリルなどを用いてビアとなる部分に物理的に貫通孔を形成する工程と、金属膜を選択的に着膜形成して表層の配線パターンと導通ビアを形成する工程とを有する回路形成用基板の製造方法によって形成されることを特徴とする請求項１１〜１６のいずれかに記載の半導体装置の製造方法。
【請求項１８】前記回路基板は、通常のプリント基板を形成する工程と、この回路基板の表面に液状の熱硬化型エポキシ樹脂を均一な膜厚となるように塗布する工程と、これを第１の熱処理を施して半硬化する工程と、フォトリソ技術とエッチング技術を用いてビアとなる部分に化学的に貫通孔を形成する工程と、第２の熱処理を施して完全硬化する工程と、金属膜を選択的に着膜形成して表層の配線パターンと導通ビアを形成する工程とを有する回路形成用基板の製造方法によって形成されることを特徴とする請求項１１〜１６のいずれかに記載の半導体装置の製造方法。
【請求項１９】前記回路基板は、離型性フィルムを備えた被圧縮性を有する多孔質基材に貫通孔を設ける工程と、前記貫通孔に導電性ペーストを充填する工程と、前記貫通孔に前記導電性ペーストを充填した前記多孔質基材から前記離型性フィルムを剥離する工程と、前記多孔質基材の前記離型性フィルムを剥離した両面に金属箔を重ねる工程と、前記金属箔を重ねた前記多孔質基材を加熱加圧して圧縮する工程とを有する回路形成用基板の製造方法によって形成されることを特徴とする請求項１１〜１６のいずれかに記載の半導体装置の製造方法。 [Claims]
1. In a semiconductor device in which a semiconductor element is mounted face-down on a circuit board, the semiconductor device is added at least directly below the electrode terminal portion of the circuit board to be connected to a bump formed on the electrode terminal portion of the semiconductor element surface. A semiconductor device characterized in that a stress relaxation layer that can be easily deformed according to the applied pressure is provided.
2. The stress relaxation layer is made of a resin having an insulating property.thingThe semiconductor device according to claim 1.
3. The stress relaxation layer is in contact with the stress relaxation layer.SaidOf the circuit board in the wiring layer of the circuit boardSaidThe semiconductor device according to claim 2, wherein no wiring is provided in the region corresponding to the lower part of the electrode terminal portion.
4. The above.ResponseIn contact with the force relaxation layerSaidOf the circuit board in the wiring layer of the circuit boardSaidThe semiconductor device according to claim 2, wherein a wiring insulated from other wiring is provided in a region corresponding to the lower part of the electrode terminal portion.
5. The above.ResponseIn contact with the force relaxation layerSaidOf the circuit board in the wiring layer of the circuit boardSaidThe semiconductor device according to claim 2, wherein a plate-shaped metal or ceramic having an insulating property is provided in a region corresponding to the lower part of the electrode terminal portion.
6. Claim 1 is characterized in that a part or all of the stress relaxation layer is made of a conductive adhesive.DescriptionSemiconductor device.
7. BeforeConsists of conductive adhesiveSaidThe semiconductor device according to claim 6, wherein the stress relaxation layer is in electrical contact with the wiring of the wiring layer in contact with the stress relaxation layer of the circuit board.
8. BeforeConsists of conductive adhesiveSaidOf stress relaxation layerSaidA part is in electrical contact with the wiring of the wiring layer in contact with the stress relaxation layer of the circuit board, and the remaining part isOf the circuit boardThe semiconductor device according to claim 6, wherein the semiconductor device is not in electrical contact with the wiring.
9. The semiconductor element is formed.SaidThe bump is also formed directly above the circuit element forming region inside the semiconductor element.Be doneingthingThe semiconductor device according to claim 1.
10. SaidThe semiconductor device according to claim 1, wherein the electrode terminals of the semiconductor element are arranged in an area array.
11. The method for manufacturing a semiconductor device according to claim 1, wherein a bump having a uniform height made of a conductive material is formed in advance on the semiconductor element, and a predetermined amount is formed on the top of the bump. After applying the conductive adhesive, face downThe semiconductor elementIt is placed in a predetermined position on the circuit board, and then the semiconductor element andSaidApply predetermined pressure and temperature from the back of the circuit boardthingCures the conductive adhesive withLet meA method for manufacturing a semiconductor device, which comprises obtaining an electrical connection between the semiconductor element and the circuit board.
12. The method of manufacturing a semiconductor device according to claim 1, wherein a bump having a uniform height made of a conductive material is formed in advance on the semiconductor element, and a predetermined amount of conductivity is formed on the top of the bump. An adhesive is applied, and on the other hand, a resin having an insulating property is previously applied to a region of the circuit board that does not cover the electrode terminals of the circuit board, which is involved in the electrical connection between the semiconductor element and the circuit board. After the semiconductor element is placed face-down at a predetermined position on the circuit board, the semiconductor element and the semiconductor elementSaidApply predetermined pressure and temperature from the back of the circuit boardthingDue to the conductivityadhesiveas well asSaidInsulationHaveHarden the resinLetA method for manufacturing a semiconductor device, which comprises obtaining an electrical connection between the semiconductor element and the circuit board.
13. A liquid insulating resin is injected and filled in a gap between the semiconductor element and the circuit board, and then heated to cure the insulating resin.LetThe method for manufacturing a semiconductor device according to claim 11 or 12, wherein the semiconductor device is manufactured.
14. The method for manufacturing a semiconductor device according to claim 1, wherein a bump made of a conductive material is formed in advance on the semiconductor element, while bumps are formed on the semiconductor element.TimesA liquid having insulating properties at a predetermined position on the road substrate on which the semiconductor element is placed.InsulationAfter applying the resin and placing the semiconductor element at a predetermined position on the circuit board face-down, the semiconductor element and the semiconductor elementSaidFormed on the semiconductor element by applying a predetermined pressure and temperature from the back surface of the circuit board.SaidThe bump and the electrode terminal formed on the circuit board are brought into contact with each other, and the contact causes the contact.,While obtaining an electrical connection between the semiconductor element and the circuit board, the aboveLiquid insulating resinHardenLetA method for manufacturing a semiconductor device.
15. The method for manufacturing a semiconductor device according to claim 1, wherein a bump made of a conductive material is formed in advance on the semiconductor element, while bumps are formed on the semiconductor element.TimesA resin in which conductive particles are dispersed in a liquid insulating resin is applied to a predetermined position on a road substrate on which the semiconductor element is placed, and the semiconductor element is faced down to a predetermined position on the circuit board. After mounting, the semiconductor element andSaidFormed on the semiconductor element by applying a predetermined pressure and temperature from the back surface of the circuit board.SaidThe bump and the electrode terminal formed on the circuit board are brought into contact with each other via the conductive particles, and the contact is achieved.,While obtaining an electrical connection between the semiconductor element and the circuit board, the aboveLiquid insulating resinHardenLetA method for manufacturing a semiconductor device.
16.Liquid insulating resinThe method for manufacturing a semiconductor device according to claim 14 or 15, wherein is in the form of a film that has been pre-cured in a B stage.
17. The circuit board has a step of forming a normal printed circuit board, a step of applying a liquid thermosetting epoxy resin to the surface of the circuit board so as to have a uniform film thickness, and a heat treatment thereof. The process of hardening by heat treatment, the process of physically forming through holes in the vias using a laser or a drill, and the process of selectively forming a metal film to form a wiring pattern on the surface layer and conductive vias. The method for manufacturing a semiconductor device according to any one of claims 11 to 16, wherein the circuit board is formed by a method for manufacturing a circuit-forming substrate, which comprises a step of making a circuit board.
18. A step of forming a normal printed circuit board and a step of applying a liquid thermosetting epoxy resin to the surface of the circuit board so as to have a uniform film thickness, the first step thereof. The step of applying the heat treatment of 1 to semi-curing, the step of chemically forming through holes in the portion to be via using the photolitho technique and the etching technique, the step of performing the second heat treatment to completely cure, and the metal. The invention according to any one of claims 11 to 16, wherein the film is formed by a method for manufacturing a circuit forming substrate, which comprises a step of selectively forming a film to form a surface layer wiring pattern and forming a conductive via. Manufacturing method of semiconductor equipment.
19. The circuit board has a step of providing a through hole in a compressible porous substrate provided with a releasable film, a step of filling the through hole with a conductive paste, and the through hole. A step of peeling the releasable film from the porous substrate filled with the conductive paste, a step of stacking a metal foil on both sides of the releasable film of the porous substrate, and the metal. The semiconductor device according to any one of claims 11 to 16, wherein the porous substrate is formed by a method for manufacturing a circuit-forming substrate, which comprises a step of heating and pressurizing and compressing the porous substrate on which foils are stacked. Production method.

また、上記した半導体装置の実装体の実装方法は、フェースダウンにて実装する際に、上記応力緩和層を加熱して軟化させて変形容易としたことを特徴とする半導体装置の実装方法である。
また、加熱硬化させて半導体素子と回路基板を接着させる接着剤として、予めＢステージ硬化させたフィルム状の液状絶縁樹脂を使用することを特徴とする半導体装置の実装方法である。 Further, the mounting method of the mounting body of the semiconductor device described above is a mounting method of the semiconductor device characterized in that the stress relaxation layer is heated and softened to be easily deformed when mounting face-down. ..
Another method for mounting a semiconductor device is to use a film-like liquid insulating resin that has been pre-cured in a B stage as an adhesive that is heat-cured to bond the semiconductor element and the circuit board.

まず、ワイヤーボンディング技術等を用いてバンプ１０２を形成した半導体素子１０１を、接続材料として用いるＡＣＦ１０７を間に挟んで、回路基板１０３の基板電極１０４の所定の位置に位置合わせを行ってフェースダウンで搭載する。その後、半導体素子１０１及び回路基板１０３の背面より加圧及び加熱を施し、ＡＣＦ１０７を構成する樹脂成分を溶融、軟化させてバンプ１０２と基板電極１０４間に介在する樹脂を押しのけると同時に、この部分に存在する導電性粒子１０８をこれらで挟み込み、当接する事で導通を得る。 First, the semiconductor device 101 formed with bumps 102 using a wire bonding technique or the like, in between the ACF 1 07 is used as the connecting material, by performing alignment at a predetermined position on the substrate electrode 104 of the circuit board 103 face Install down. After that, pressurization and heating are applied from the back surfaces of the semiconductor element 101 and the circuit board 103 to melt and soften the resin components constituting the ACF 107 to push away the resin interposed between the bump 102 and the substrate electrode 104, and at the same time, to this portion. Conduction is obtained by sandwiching the existing conductive particles 108 between them and bringing them into contact with each other.

なお、製造方法において半導体素子と回路基板の接続材料については、本実施の形態に記載したＡＣＦ１０７以外に、以下に記載する材料を用いて、実装体を作製しても良い。
(1) 接続材料として、液状樹脂中に導電性粒子を分散させたＡＣＰ（Anisotropic Conductive Paste：異方性導電ペースト）を用いる方法。なお、製造方法については、本実施の形態に記載したのとほぼ同様な方法にて作製することにより実装体を得る。
(2) 接続材料として導電性粒子を含まない絶縁樹脂フィルムを用いる方法。なお、この接続材料を用いて作製した実装体の要部断面図を図２に示し、図中、図１と同一符号は、同一または相当箇所を示し、１０９は絶縁樹脂フィルムを示す。製造方法については、まずワイヤーボンディング技術等を用いてバンプ１０２を形成した半導体素子１０１を、絶縁樹脂フィルム１０９の接続材料を間に挟んで、回路基板１０３の基板電極１０４の所定の位置に位置合わせを行ってフェースダウンで搭載する。その後、半導体素子１０１背面より加圧及び加熱を施し、前記接続材料を構成する樹脂成分を溶融、軟化させてバンプ１０２と基板電極１０４間に介在する樹脂を押しのけて、バンプ１０２と回路基板１０３に形成した基板電極１０４が直接、当接する事により導通を得る。 Note that the connection material of the semiconductor element and the circuit board in the manufacturing process, in addition ACF107 described in this embodiment, by using the materials described below, may be prepared mount assembly.
(1) A method of using ACP (Anisotropic Conductive Paste) in which conductive particles are dispersed in a liquid resin as a connecting material. As for the manufacturing method, a mounted body is obtained by manufacturing by a method substantially the same as that described in this embodiment.
(2) A method of using an insulating resin film that does not contain conductive particles as a connecting material. A cross-sectional view of a main part of a mounting body manufactured by using this connecting material is shown in FIG. 2, in which the same reference numerals as those in FIG. 1 indicate the same or corresponding parts, and 109 indicates an insulating resin film. Regarding the manufacturing method, first, the semiconductor element 101 on which the bump 102 is formed by using wire bonding technology or the like is aligned with a predetermined position of the substrate electrode 104 of the circuit board 103 with the connecting material of the insulating resin film 109 sandwiched between them. And mount it face down. After that, pressurization and heating are applied from the back surface of the semiconductor element 101 to melt and soften the resin components constituting the connecting material to push away the resin interposed between the bump 102 and the substrate electrode 104, and to the bump 102 and the circuit board 103. Conduction is obtained by directly contacting the formed substrate electrodes 104.

この際の加圧量及び加熱温度は、必要な品質を確保するためには、５０ｇｆ／バンプ以上で温度は１８０℃以上が望ましい。また、本実施の形態においてはバンプ先端の径は、φ４０〜８０μｍの範囲にある。この後、加熱し続けて絶縁樹脂フィルム１０９の樹脂を硬化させることで、接続を完了し実装体を得る。
(3) 接続材料として(2)で用いた絶縁樹脂フィルム１０９の代わりに導電性粒子を含まない液状絶縁樹脂を用いる方法。なお、製造方法としては、(2)に記載したのとほぼ同様な製造法にて作製することにより実装体を得る。 At this time, the pressurization amount and the heating temperature are preferably 50 gf / bump or more and the temperature is 180 ° C. or more in order to ensure the required quality. Further, in the present embodiment, the diameter of the bump tip is in the range of φ40 to 80 μm. After that, the resin of the insulating resin film 109 is cured by continuing heating to complete the connection and obtain the mounted body.
(3) A method in which a liquid insulating resin containing no conductive particles is used as the connecting material instead of the insulating resin film 109 used in (2). As a manufacturing method, a mounted body is obtained by manufacturing by a manufacturing method almost the same as that described in (2).

これらの構成により、実施の形態１に記載した通り、実装工程時に外部より加わる圧力は、バンプ１０２、基板電極１０４を通じて応力緩和層１０５に伝達されるが、応力緩和層１０５により吸収されることにより、この反作用によって半導体素子１０１に加わる力は小さくなるので、半導体素子１０１に形成された回路素子機能に不具合が発生する事がなくなり、極めて品質の高い半導体装置を安定して作製することを実現する。特に、エリアアレイ状に電極端子が配列された半導体素子のようにアルミ電極端子直下に回路素子が形成されている場合は、極めて有効な発明である。 With these configurations, as described in the first embodiment, the pressure applied from the outside during the mounting process, the bump 102, is transmitted to the stress relieving layer 105 through the substrate electrode 104, it is absorbed by the stress relieving layer 105 As a result, the force applied to the semiconductor element 101 due to this reaction is reduced, so that problems do not occur in the circuit element function formed in the semiconductor element 101, and it is possible to stably manufacture an extremely high quality semiconductor device. To do. In particular, it is an extremely effective invention when a circuit element is formed directly under the aluminum electrode terminal like a semiconductor element in which electrode terminals are arranged in an area array.

また、以上のように構成された半導体装置では、実施の形態１にも記載した通り、実装時の加熱及び加圧により応力緩和層１０５の変形が必要以上に大きく、厚みの減少が著しく大きくなるので、基板電極１０４と第１の下層配線層１０６間の電気的絶縁性能が劣化することにより、品質を損なうため、本実施の形態では図４に示すように基板電極１０４直下領域には、絶縁性を有する板状の金属またはセラミクスを設けた構成とすることにより、上記した品質課題発生の解決を図っている。 Further, in the semiconductor device configured as described above, as described in the first embodiment, the deformation of the stress relaxation layer 105 becomes larger than necessary due to heating and pressurization at the time of mounting, and the decrease in thickness becomes significantly large. since, the substrate electrode 104 by electrical insulation performance between the first lower wiring layer 106 is degraded, because the loss of quality, the substrate electrode 104 directly below the area as in the embodiment shown in Figure 4, The above-mentioned quality problems are solved by providing a plate-shaped metal or ceramics having an insulating property.

ワイヤーボンディング技術等を用いて一様な高さのバンプ１０２を形成した半導体素子１０１の、バンプ１０２の頂頭部のみに、スタンピング法などにより所定量の液状の導電性接着剤１１３を塗布する。その後、回路基板１０３上の所定の位置に位置合わせを行ってフェースダウンで搭載した後、半導体素子１０１及び回路基板１０３背面より加圧及び加熱を施し、導電性接着剤１１３を硬化させてバンプ１０２と基板電極１０４の接着及び接続を完了する。この際、必要な品質確保のための加圧量は、実施の形態１の中で記載したＡＣＦの場合の１／２以下で良い。 A predetermined amount of liquid conductive adhesive 113 is applied only to the top of the bump 102 of the semiconductor element 101 in which the bump 102 having a uniform height is formed by using a wire bonding technique or the like by a stamping method or the like. Then, after mounting in a face-down performs alignment in position on the circuit board 103, subjected to pressure and heating from the back surface the semiconductor element 101 and circuit board 103, to cure the conductive adhesive 113 bumps 102 and completes the adhesion and connection of the substrate electrode 104. At this time, the required pressurization amount for ensuring quality may be 1/2 or less of the case of ACF described in the first embodiment.

これらの構成により、実施の形態１に記載した通り、実装工程時に外部より加わる圧力は、バンプ１０２、基板電極１０４を通じて応力緩和層１０５に伝達されるが、応力緩和層１０５により吸収されることにより、この反作用によって半導体素子１０１に加わる力は小さくなるので、半導体素子１０１に形成された回路素子機能に不具合が発生する事がなくなり、極めて品質の高い半導体装置を安定して作製することを実現する。特に、エリアアレイ状にアルミ電極端子が配列された半導体素子１０１のようにアルミ電極端子直下に回路素子が形成されている場合は、極めて有効な発明である。 With these configurations, as described in the first embodiment, the pressure applied from the outside during the mounting process, the bump 102, is transmitted to the stress relieving layer 105 through the substrate electrode 104, it is absorbed by the stress relaxation layer 10 5 As a result, the force applied to the semiconductor element 101 due to this reaction is reduced, so that problems do not occur in the circuit element function formed in the semiconductor element 101, and an extremely high quality semiconductor device can be stably manufactured. Realize. In particular, it is an extremely effective invention when a circuit element is formed directly under the aluminum electrode terminal as in the semiconductor element 101 in which aluminum electrode terminals are arranged in an area array.

また、本実施の形態においては実装時に必要な加圧量が少なくて済むため、本発明の実施の形態１〜４に記載したような応力緩和層１０５の著しい変形に伴う、電気的絶縁劣化による品質課題が発生しないので、基板電極１０４直下に対する特別な工夫を必要としない。 Further, since the present embodiment Oite are fewer pressurization required when mounting, due to the significant deformation of the stress relaxation layer 105 as described in Embodiment 1-4 of the present invention, electrical insulation Since no quality problem occurs due to deterioration, no special device is required for the area directly under the substrate electrode 104.

（実施の形態６）
図８は本発明の第６の実施の形態を示す半導体装置の要部断面図である。図中、図７と同一符号は、同一または相当箇所を示す。図８において、１１５は仮止め用絶縁樹脂で熱硬化型樹脂である。
(Embodiment 6)
FIG. 8 is a cross-sectional view of a main part of the semiconductor device showing the sixth embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 7 indicate the same or corresponding parts. In FIG. 8, 115 is an insulating resin for temporary fixing and is a thermosetting resin.