JPH11214571A - Sheet for mounting semiconductor element - Google Patents
Sheet for mounting semiconductor elementInfo
- Publication number
- JPH11214571A JPH11214571A JP10015840A JP1584098A JPH11214571A JP H11214571 A JPH11214571 A JP H11214571A JP 10015840 A JP10015840 A JP 10015840A JP 1584098 A JP1584098 A JP 1584098A JP H11214571 A JPH11214571 A JP H11214571A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- adhesive sheet
- sheet
- wiring board
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、下面に電極が形成
された半導体素子を、上面にこの半導体素子の電極に対
応する接続パッドを有する配線基板上に、半導体素子の
電極と配線基板の接続パッドとが電気的に接続されるよ
うにして接着固定するために、半導体素子と配線基板と
の間に配置される半導体素子実装用シートに関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of connecting a semiconductor element having an electrode formed on a lower surface thereof to a wiring board having connection pads corresponding to the electrodes of the semiconductor element on an upper surface thereof. The present invention relates to a semiconductor element mounting sheet disposed between a semiconductor element and a wiring board so as to be electrically connected to a pad and fixed.
【０００２】[0002]
【従来の技術】近年、半導体素子の電極数の増加に伴
い、半導体素子を配線基板に実装する方法として、半導
体素子を搭載する配線基板の上面に半導体素子の電極と
接続される接続パッドを半導体素子の電極と対応する配
列に形成するとともにこの接続パッドと半導体素子の電
極とを対向させて半田等の金属バンプを介して接続す
る、いわゆるフリップチップ実装法が多用されるように
なってきている。2. Description of the Related Art In recent years, as the number of electrodes of a semiconductor element has increased, a method of mounting a semiconductor element on a wiring board has been proposed. A so-called flip-chip mounting method, in which the connection pads are formed in an array corresponding to the electrodes of the element and the connection pads and the electrodes of the semiconductor element are opposed to each other and connected via metal bumps such as solder, has been widely used. .
【０００３】このフリップチップ実装法では、半導体素
子の電極と配線基板の接続パッドとを半田等の金属バン
プを介して接続した後、半導体素子と配線基板との隙間
にアンダーフィルと呼ばれる未硬化の液状の熱硬化性樹
脂を注入ノズルにより注入し、これを加熱して熱硬化さ
せることによって、半導体素子を配線基板上に接着固定
すると同時に半導体素子の電極や配線基板の接続パッド
等を外部の水分等から保護するようにしている。In this flip-chip mounting method, after an electrode of a semiconductor element is connected to a connection pad of a wiring board via a metal bump such as solder, an uncured unfilled material called an underfill is formed in a gap between the semiconductor element and the wiring board. A liquid thermosetting resin is injected by an injection nozzle and heated and thermoset to bond and fix the semiconductor element on the wiring board and at the same time to remove external moisture from the electrodes of the semiconductor element and the connection pads of the wiring board. And so on.
【０００４】なお、このフリップチップ実装法では、硬
化後のアンダーフィルの熱膨張係数係数の低減および耐
湿性や熱伝導性の向上のために、アンダーフィル中に酸
化珪素粉末等の無機絶縁物粉末を約40容量％程度充填し
ている。In this flip chip mounting method, an inorganic insulating powder such as a silicon oxide powder is contained in the underfill in order to reduce the coefficient of thermal expansion coefficient of the cured underfill and to improve moisture resistance and thermal conductivity. About 40% by volume.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、この従
来の実装方法によると、実装後の半導体素子と配線基板
との間に液状の熱硬化性樹脂を注入ノズルにより注入す
るために、注入ノズルを配置するための空間を半導体素
子の実装位置周辺に設ける必要があり、そのため半導体
素子の実装位置の周囲における部品の配置が制限されて
しまうという問題点があった。However, according to this conventional mounting method, the injection nozzle is disposed between the mounted semiconductor element and the wiring board in order to inject the liquid thermosetting resin by the injection nozzle. Therefore, it is necessary to provide a space around the mounting position of the semiconductor element, and therefore, there is a problem that the arrangement of components around the mounting position of the semiconductor element is restricted.
【０００６】また、熱硬化後のアンダーフィルの熱膨張
係数の低減のため、および耐湿性や熱伝導性の向上のた
めに無機絶縁物粉末をアンダーフィル中に多量に充填さ
せると、液状におけるアンダーフィルの流動性が大きく
損なわれて半導体素子と配線基板との間にアンダーフィ
ルを良好に注入することができなくなってしまうため、
アンダーフィル中に充填させる無機絶縁物粉末はせいぜ
い40容量％程度が限度であった。その結果、硬化後のア
ンダーフィルの熱膨張係数が約30×10-6／℃以上と大き
なものとなり、熱膨張係数が３〜５×10-6／℃程度の半
導体素子や５〜20×10-6／℃程度の配線基板との熱膨張
係数の差が大きいためそれらとの間に大きな熱ストレス
を発生させ易くなって、半導体素子を配線基板に強固に
接着固定することができなかったり、あるいは耐湿性や
熱伝導性を向上させることができなくなり、半導体素子
を長期間にわたり正常かつ安定に作動させることが困難
となるという問題点があった。When a large amount of inorganic insulating powder is filled in the underfill to reduce the coefficient of thermal expansion of the underfill after thermosetting and to improve the moisture resistance and the thermal conductivity, the underfill in a liquid state may be formed. Since the fluidity of the fill is greatly impaired and the underfill cannot be injected well between the semiconductor element and the wiring board,
The limit of the inorganic insulating powder to be filled in the underfill was at most about 40% by volume. As a result, the thermal expansion coefficient of the cured underfill becomes as large as about 30 × 10 −6 / ° C. or more, and a semiconductor element having a thermal expansion coefficient of about 3 to 5 × 10 −6 / ° C. or 5 to 20 × 10 −6 / ° C. Since the difference in thermal expansion coefficient between the wiring board and the wiring board of about -6 / ° C is large, it is easy to generate a large thermal stress between them and the semiconductor element cannot be firmly bonded and fixed to the wiring board. Alternatively, there has been a problem that the moisture resistance and the thermal conductivity cannot be improved, and it is difficult to operate the semiconductor element normally and stably for a long period of time.
【０００７】本発明は上記事情に鑑みて案出されたもの
であり、その目的は、半導体素子と配線基板との間に配
置させて半導体素子を実装する接着シートから成り、半
導体素子の実装位置の周辺に部品を高密度に配置するこ
とができ、半導体素子と配線基板とを強固に接着固定す
ることができるとともに耐湿性や熱伝導性を良好なもの
として半導体素子を長期間にわたり正常かつ安定に作動
させることが可能となる半導体素子実装用シートを提供
することにある。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an adhesive sheet for mounting a semiconductor element by disposing the semiconductor element between a semiconductor element and a wiring board, and a mounting position of the semiconductor element. Components can be arranged at high density around the semiconductor element, and the semiconductor element and the wiring board can be firmly adhered and fixed, and the semiconductor element can be normally and stably for a long time with good moisture resistance and thermal conductivity. It is another object of the present invention to provide a semiconductor element mounting sheet which can be operated in a short time.
【０００８】[0008]
【課題を解決するための手段】本発明の半導体素子実装
用シートは、下面に電極が形成された半導体素子と上面
に前記電極に接続される接続パッドを有する配線基板と
の間に配置され、熱硬化させることにより前記半導体素
子と前記配線基板とを接着固定する半硬化状態の熱硬化
性樹脂から成る接着シートに、前記電極と前記接続パッ
ドとを電気的に接続するための、半硬化状態の熱硬化性
樹脂と金属粉末とを混合して成るビア導体を前記接着シ
ートを上下に貫通して配設して成ることを特徴とするも
のである。A semiconductor element mounting sheet according to the present invention is arranged between a semiconductor element having an electrode formed on a lower surface and a wiring board having connection pads connected to the electrode on an upper surface. A semi-cured state for electrically connecting the electrodes and the connection pads to an adhesive sheet made of a thermosetting resin in a semi-cured state for bonding and fixing the semiconductor element and the wiring board by thermosetting. And a via conductor formed by mixing a thermosetting resin with a metal powder.
【０００９】本発明の半導体素子実装用シートによれ
ば、半導体素子と配線基板との間にシート状で配置され
ることから、従来のアンダーフィルを用いる場合のよう
に半導体素子の実装位置の周辺に液状の熱硬化性樹脂の
注入ノズルを配置するための空間を設ける必要がないの
で、半導体素子の実装位置の周辺に部品を高密度に配置
することができる。また、接着シートは熱硬化後に半導
体素子と配線基板との間にアンダーフィルと同様に介在
する熱硬化性樹脂となることから、半導体素子と配線基
板とを強固に接着固定することができるとともに耐湿性
や熱伝導性を良好なものとすることができる。According to the semiconductor element mounting sheet of the present invention, since it is arranged in a sheet form between the semiconductor element and the wiring board, it is difficult to mount the semiconductor element around the mounting position of the semiconductor element as in the case of using the conventional underfill. There is no need to provide a space for arranging a liquid thermosetting resin injection nozzle in the liquid crystal panel, so that components can be densely arranged around the mounting position of the semiconductor element. In addition, since the adhesive sheet becomes a thermosetting resin interposed between the semiconductor element and the wiring board after the thermosetting in the same manner as the underfill, the semiconductor element and the wiring board can be firmly bonded and fixed, and the moisture resistance can be improved. Properties and thermal conductivity can be improved.
【００１０】また本発明の半導体素子実装用シートによ
れば、半導体素子と配線基板との間にシート状で配置さ
れることから、アンダーフィルに用いる未硬化の液状の
熱硬化性樹脂のように良好な流動性を接着シートに付与
する必要はなく、半導体素子と配線基板との間の所望の
位置に確実に配置して半導体素子を容易に実装すること
ができる。According to the semiconductor element mounting sheet of the present invention, since it is arranged in a sheet form between the semiconductor element and the wiring board, it can be used as an uncured liquid thermosetting resin used for underfill. It is not necessary to impart good fluidity to the adhesive sheet, and the semiconductor element can be easily mounted by reliably disposing it at a desired position between the semiconductor element and the wiring board.
【００１１】また、本発明の半導体素子実装用シートに
よれば、接着シート中に50〜80容量％の無機絶縁物粉末
を充填することによって、熱硬化後の接着シートの熱膨
張係数を20×10-6／℃以下の小さいものとして接着シー
トと半導体素子および配線基板との間の熱ストレスを小
さいものとするとともに耐湿性・耐熱性をより良好なも
のとすることが可能である。Further, according to the semiconductor element mounting sheet of the present invention, by filling the adhesive sheet with 50 to 80% by volume of the inorganic insulating powder, the thermal expansion coefficient of the heat-cured adhesive sheet is reduced to 20 ×. As small as 10 −6 / ° C. or less, it is possible to reduce the thermal stress between the adhesive sheet and the semiconductor element and the wiring board, and to further improve the moisture resistance and heat resistance.
【００１２】さらに、本発明の半導体素子実装用シート
によれば、接着シートを半硬化状態の熱硬化性樹脂中に
無機絶縁物粉末を50〜80容量％充填させた複数の接着シ
ート層を積層することにより形成するとともに各接着シ
ート層に充填された無機絶縁物粉末の充填率を接着シー
トの上面側から下面側に向けて順次小さいものとする
と、半導体素子と配線基板との熱膨張係数の差に起因し
て発生する熱ストレスをより小さいものとすることがで
きる。Further, according to the semiconductor element mounting sheet of the present invention, a plurality of adhesive sheet layers in which an inorganic insulating powder is filled in a semi-cured thermosetting resin at 50 to 80% by volume are laminated. When the filling rate of the inorganic insulating powder filled in each adhesive sheet layer is gradually decreased from the upper surface side to the lower surface side of the adhesive sheet, the coefficient of thermal expansion between the semiconductor element and the wiring substrate is reduced. Thermal stress generated due to the difference can be made smaller.
【００１３】[0013]
【発明の実施の形態】次に、本発明を添付の図面を基に
説明する。図１は本発明の半導体素子実装用シートの実
施の形態の一例を示す断面図である。同図において１は
接着シート、２はビア導体であり、この接着シート１と
ビア導体２とで本発明の半導体素子実装シート３が構成
される。４は半導体素子、５は配線基板である。Next, the present invention will be described with reference to the accompanying drawings. FIG. 1 is a sectional view showing an example of an embodiment of a semiconductor element mounting sheet according to the present invention. In FIG. 1, reference numeral 1 denotes an adhesive sheet, 2 denotes a via conductor, and the adhesive sheet 1 and the via conductor 2 constitute a semiconductor element mounting sheet 3 of the present invention. 4 is a semiconductor element and 5 is a wiring board.
【００１４】接着シート１は、半導体素子４と配線基板
５との間に配置される、半硬化状態の熱硬化性樹脂から
成る平板状のシートであり、半硬化状態であることから
この接着シート１自身および接着シート１を貫通して配
設されたビア導体２を所定の形状に保持できるだけの固
形状態であるとともに、加熱されることにより一旦軟化
した後に熱硬化し、それにより半導体素子４と配線基板
５とを接着固定するものである。The adhesive sheet 1 is a flat sheet made of a semi-cured thermosetting resin and disposed between the semiconductor element 4 and the wiring board 5. 1 and the via conductor 2 disposed through the adhesive sheet 1 is in a solid state capable of maintaining a predetermined shape, and is temporarily softened by being heated and then thermally cured, thereby forming a semiconductor element 4 The wiring board 5 is bonded and fixed.
【００１５】接着シート１を形成する熱硬化性樹脂とし
ては、エポキシ樹脂やポリイミド樹脂・ビスマレイミド
トリアジン樹脂・アクリル変性ポリフェニレンオキサイ
ド樹脂等の熱硬化性樹脂が採用され得る。例えばエポキ
シ樹脂が採用される場合であれば、ビスフェノールＡ型
エポキシ樹脂・ビスフェノールＦ型エポキシ樹脂・ノボ
ラック型エポキシ樹脂・グリシジルエステル型エポキシ
樹脂等のエポキシ樹脂主剤にアミン系硬化剤・イミダゾ
ール系硬化剤・酸無水物系硬化剤等の硬化剤を添加混合
して得た樹脂性樹脂ぺーストを従来周知のドクターブレ
ード法等のシート成形法を採用して半硬化状態の接着シ
ート層となし、この接着シート層に適当な切断加工を施
すことによって製作される。As the thermosetting resin forming the adhesive sheet 1, a thermosetting resin such as an epoxy resin, a polyimide resin, a bismaleimide triazine resin, and an acryl-modified polyphenylene oxide resin can be used. For example, when an epoxy resin is used, an amine-based curing agent, an imidazole-based curing agent, and a bisphenol A-type epoxy resin, a bisphenol F-type epoxy resin, a novolak-type epoxy resin, a glycidyl ester-type epoxy resin, and other epoxy resin base materials are used. The resinous resin paste obtained by adding and mixing a curing agent such as an acid anhydride-based curing agent is formed into a semi-cured adhesive sheet layer by using a conventionally known sheet forming method such as a doctor blade method. It is manufactured by performing an appropriate cutting process on the sheet layer.
【００１６】接着シート１は、その内部に酸化珪素粉末
や酸化アルミニウム粉末・窒化アルミニウム粉末・炭化
珪素粉末等の無機絶縁物粉末を50〜80容量％充填させて
おくと、熱硬化後の接着シート１の熱膨張係数を例えば
20×10-6／℃以下の小さいものとすることが可能とな
り、その結果、接着シート１と半導体素子４および配線
基板５との間に発生する熱ストレスを小さいものとし
て、接着シート１により半導体素子４と配線基板５とを
接着固定した後、半導体素子４と配線基板５とを長期間
にわたり強固に接着固定することができる。さらに、接
着シートの熱伝導性および耐湿性が大きく向上して半導
体素子を長期間にわたり正常かつ安定に作動させること
ができる。When the adhesive sheet 1 is filled with 50 to 80% by volume of an inorganic insulating powder such as a silicon oxide powder, an aluminum oxide powder, an aluminum nitride powder, and a silicon carbide powder, the thermosetting adhesive sheet is used. For example, the coefficient of thermal expansion of 1 is
It is possible to reduce the thermal stress generated between the adhesive sheet 1 and the semiconductor element 4 and the wiring board 5 to a small value of 20 × 10 −6 / ° C. or less. After the element 4 and the wiring board 5 are bonded and fixed, the semiconductor element 4 and the wiring board 5 can be firmly bonded and fixed for a long period of time. Furthermore, the heat conductivity and moisture resistance of the adhesive sheet are greatly improved, and the semiconductor element can be normally and stably operated for a long time.
【００１７】なお、接着シート１中に充填させる無機絶
縁物粉末は、その充填量が50容量％未満では硬化後の接
着シート１の熱膨張係数を20×10-6／℃以下の小さいも
のとすることが困難であるとともに熱伝導性および耐湿
性の大きな向上を望むことができなくなる傾向にあり、
他方、80容量％を超えると接着シート１により半導体素
子４と配線基板５とを強固に接着固定することが困難と
なる傾向にある。従って、接着シート１は、その内部に
酸化珪素粉末等の無機絶縁物粉末を50〜80容量％充填さ
せておくことが好ましい。When the amount of the inorganic insulating powder to be filled in the adhesive sheet 1 is less than 50% by volume, the thermal expansion coefficient of the cured adhesive sheet 1 is as small as 20 × 10 −6 / ° C. or less. It tends to be difficult to do so and it is not possible to expect a great improvement in thermal conductivity and moisture resistance,
On the other hand, if it exceeds 80% by volume, it tends to be difficult to firmly bond and fix the semiconductor element 4 and the wiring board 5 with the adhesive sheet 1. Therefore, it is preferable that the adhesive sheet 1 is filled with 50 to 80% by volume of an inorganic insulating powder such as a silicon oxide powder.
【００１８】接着シート１に無機絶縁物粉末を充填させ
るには、接着シート１となる絶縁性樹脂ぺースト中に粒
径が0.1 〜100 μｍ程度の無機絶縁物粉末を添加混合す
る方法が採用される。この場合、接着シート１となる絶
縁性樹脂ペーストは、絶縁性樹脂ペーストをシート状に
形成可能な流動性を有していればよいことから、50〜80
容量％の無機絶縁物粉末を充填させることが可能であ
る。In order to fill the adhesive sheet 1 with the inorganic insulating powder, a method of adding and mixing an inorganic insulating powder having a particle size of about 0.1 to 100 μm into an insulating resin paste serving as the adhesive sheet 1 is adopted. You. In this case, the insulating resin paste serving as the adhesive sheet 1 only needs to have a fluidity capable of forming the insulating resin paste into a sheet shape.
It is possible to fill the inorganic insulating powder by volume%.
【００１９】そして、このような絶縁性樹脂ペーストを
用いて半硬化状態の接着シート層、すなわちこの接着シ
ート層自身および接着シート層から成る接着シート１を
貫通して配設されるビア導体２を所定の形状に保持でき
るだけの固形状態であるとともに、加熱されることによ
り一旦軟化した後に熱硬化する特性を有する接着シート
層を成形して、半導体素子４の実装の仕様に応じた半硬
化状態の接着シート１が製作される。Using the insulating resin paste, the adhesive sheet layer in a semi-cured state, that is, the via conductor 2 disposed through the adhesive sheet layer itself and the adhesive sheet 1 composed of the adhesive sheet layer is formed. An adhesive sheet layer which is in a solid state capable of maintaining a predetermined shape and has a property of being once softened by heating and then thermosetting is formed, and is formed into a semi-cured state according to the mounting specification of the semiconductor element 4. The adhesive sheet 1 is manufactured.
【００２０】また、接着シート１には、接着シート１を
上下に貫通するビアホール１ａが穿孔されており、この
ビアホール１ａ内にはビア導体２が接着シート１を上下
に貫通するようにして配設されている。The adhesive sheet 1 is provided with a via hole 1a penetrating the adhesive sheet 1 vertically and a via conductor 2 is provided in the via hole 1a so as to penetrate the adhesive sheet 1 vertically. Have been.
【００２１】ビア導体２は、半導体素子４の電極４ａと
配線基板５の接続パッド５ａとを電気的に接続する作用
をなし、半硬化状態の熱硬化性樹脂と金属粉末とを混合
して成る。The via conductor 2 functions to electrically connect the electrode 4a of the semiconductor element 4 to the connection pad 5a of the wiring board 5, and is formed by mixing a semi-cured thermosetting resin and metal powder. .
【００２２】ビア導体２の熱硬化性樹脂としては、エポ
キシ樹脂やポリイミド樹脂・ビスマレイミドトリアジン
樹脂・アクリル変性ポリフェニレンオキサイド樹脂等の
熱硬化性樹脂が採用され得る。また、ビア導体２の金属
粉末としては、銅粉末や銀粉末・銀と銅との合金粉末・
表面が銀で被覆された銅粉末等が採用され得る。As the thermosetting resin of the via conductor 2, a thermosetting resin such as an epoxy resin, a polyimide resin, a bismaleimide triazine resin, and an acrylic-modified polyphenylene oxide resin can be used. Further, as the metal powder of the via conductor 2, copper powder, silver powder, alloy powder of silver and copper,
Copper powder or the like whose surface is coated with silver may be employed.
【００２３】ビア導体２は、例えば熱硬化性樹脂がエポ
キシ樹脂から成る場合であれば、ビスフェノールＡ型エ
ポキシ樹脂・ビスフェノールＦ型エポキシ樹脂・ノボラ
ック型エポキシ樹脂・グリシジルエステル型エポキシ樹
脂等のエポキシ樹脂主剤に、アミン系硬化剤・イミダゾ
ール系硬化剤・酸無水物系硬化剤等の硬化剤および粒径
が0.1 〜20μｍ程度の金属粉末を添加混合して得た金属
ペーストを接着シート１に設けたビアホール１ａに圧入
や吸引により充填し、半硬化状態とすることによって接
着シート１の上下を貫通するようにして配設される。If the thermosetting resin is made of an epoxy resin, the via conductor 2 is made of an epoxy resin base such as bisphenol A type epoxy resin, bisphenol F type epoxy resin, novolak type epoxy resin, glycidyl ester type epoxy resin, etc. A via hole provided in the adhesive sheet 1 with a metal paste obtained by adding and mixing a curing agent such as an amine-based curing agent, an imidazole-based curing agent, and an acid anhydride-based curing agent, and a metal powder having a particle size of about 0.1 to 20 μm. 1a is filled by press-fitting or suction, and is placed in a semi-cured state so as to penetrate the adhesive sheet 1 above and below.
【００２４】なお、ビア導体２は、これに含有される金
属粉末の量が70重量％未満であるとビア導体２の電気抵
抗が大きなものとなる傾向にあり、また95重量％を超え
るとビア導体２を接着シート１のビアホール１ａ内に充
填することが困難となる傾向にある。従って、ビア導体
２は、これに含有される金属粉末の量を70〜95重量％と
しておくことが好ましい。When the amount of the metal powder contained in the via conductor 2 is less than 70% by weight, the electric resistance of the via conductor 2 tends to be large, and when the amount exceeds 95% by weight, the via It tends to be difficult to fill the conductor 2 in the via hole 1a of the adhesive sheet 1. Therefore, it is preferable that the amount of the metal powder contained in the via conductor 2 is set to 70 to 95% by weight.
【００２５】また、ビア導体２に含有される金属粉末と
して表面が銀で被覆された銅粉末を用いると、銅および
銀がいずれも電気抵抗率が低く、また銅の表面に被覆さ
せた銀が柔らかいので、接着シート１を上下からプレス
することによってビア導体２中の金属粉末同士を圧接さ
せると銀が変形して金属粉末同士が良好に面接触すると
ともに金属粉末同士の接触界面に銀と銅との拡散層が形
成され、この拡散層を介して金属粉末同士が良好に接続
されるため、極めて低抵抗のビア導体２を得ることがで
きる。従って、ビア導体２に含有される金属粉末には、
表面が銀で被覆された銅粉末を用いることが好ましい。When a copper powder whose surface is coated with silver is used as the metal powder contained in the via conductor 2, both copper and silver have low electric resistivity, and silver coated on the copper surface has Since the metal powders in the via conductors 2 are pressed against each other by pressing the adhesive sheet 1 from above and below, the silver is deformed and the metal powders are brought into good surface contact with each other. Is formed, and the metal powders are satisfactorily connected to each other via the diffusion layer. Therefore, the via conductor 2 having extremely low resistance can be obtained. Therefore, the metal powder contained in the via conductor 2 includes:
It is preferable to use copper powder whose surface is coated with silver.
【００２６】さらに、ビア導体２に含有される金属粉末
として表面が銀で被覆された銅粉末を用いる場合、金属
粉末における銀の量が0.5 重量％未満であると銀の被覆
が薄いものとなって銅粉末の表面が酸化してビア導体２
の電気抵抗が大きなものとなり易い傾向にあり、他方、
20重量％を超えると被覆した銀がマイグレーションを起
こして隣接するビア導体２同士が電気的に短絡し易いも
のとなる傾向にある。When a copper powder whose surface is coated with silver is used as the metal powder contained in the via conductor 2, if the amount of silver in the metal powder is less than 0.5% by weight, the silver coating becomes thin. The surface of the copper powder is oxidized and the via conductor 2
Tend to have a large electrical resistance,
If the content exceeds 20% by weight, the coated silver tends to migrate, and the adjacent via conductors 2 tend to be electrically short-circuited.
【００２７】従って、ビア導体２に含有される金属粉末
として表面が銀で被覆された銅粉末を用いる場合は、金
属粉末における銀の量を0.5 〜20重量％の範囲としてお
くことが好ましい。Therefore, when a copper powder whose surface is coated with silver is used as the metal powder contained in the via conductor 2, the amount of silver in the metal powder is preferably set in the range of 0.5 to 20% by weight.
【００２８】次に、本発明の半導体素子実装用シート３
を用いて半導体素子４を配線基板５に実装する方法につ
いて説明する。Next, the semiconductor element mounting sheet 3 of the present invention
A method of mounting the semiconductor element 4 on the wiring board 5 using the method will be described.
【００２９】図２（ａ）および（ｂ）は、それぞれ本発
明の半導体素子実装用シート３を用いて半導体素子４を
配線基板５に実装する方法を説明するための工程毎の断
面図である。FIGS. 2 (a) and 2 (b) are cross-sectional views for each step for explaining a method of mounting the semiconductor element 4 on the wiring board 5 using the semiconductor element mounting sheet 3 of the present invention. .
【００３０】まず、図２（ａ）に示すように、配線基板
５の上面に半導体素子実装用シート３および半導体素子
４を、半導体素子接着用シート３のビア導体２と配線基
板５の接続パッド５ａおよび半導体素子４の電極４ａと
が接触するように順次位置決めして載置する。First, as shown in FIG. 2A, the semiconductor element mounting sheet 3 and the semiconductor element 4 are placed on the upper surface of the wiring board 5, and the via conductor 2 of the semiconductor element bonding sheet 3 is connected to the connection pad of the wiring board 5. 5a and the electrode 4a of the semiconductor element 4 are sequentially positioned and placed so as to be in contact with each other.
【００３１】このとき、半導体素子実装用シート３は配
線基板５上に載置することにより半導体素子４と配線基
板５との間に配置されることから、半導体素子４の実装
位置の周辺に、従来のアンダーフィルのように注入ノズ
ルを配置するための空間のような余計な空間を設ける必
要はない。従って、半導体素子４の周囲に部品を高密度
に配置することが可能である。At this time, since the semiconductor element mounting sheet 3 is placed between the semiconductor element 4 and the wiring board 5 by being placed on the wiring board 5, the semiconductor element mounting sheet 3 is placed around the mounting position of the semiconductor element 4. It is not necessary to provide an extra space such as a space for disposing the injection nozzle as in the conventional underfill. Therefore, it is possible to arrange components at high density around the semiconductor element 4.
【００３２】次に、図２（ｂ）に示すように、配線基板
５と半導体素子実装用シート３と半導体素子４とを図示
しないホットプレス装置を用いて約１〜300 ｋｇｆ／ｃ
ｍ2の圧力で上下から加圧するとともに約80〜300 ℃の
温度で10秒〜24時間加熱し、半導体素子実装用シート３
の接着シート１およびビア導体２に含有される半硬化状
態の熱硬化性樹脂を十分に熱硬化させることによって、
半導体素子４が接着シート１を介して配線基板５上に接
着固定されるとともに半導体素子４の電極４ａと配線基
板５の接続パッド５ａとがビア導体２を介して電気的に
接続されることとなる。Next, as shown in FIG. 2 (b), the wiring board 5, the semiconductor element mounting sheet 3 and the semiconductor element 4 are connected to each other for about 1 to 300 kgf / c using a hot press (not shown).
Pressing from above and below with a pressure of m 2 and heating at a temperature of about 80 to 300 ° C for 10 seconds to 24 hours, the semiconductor device mounting sheet 3
By fully thermosetting the semi-cured thermosetting resin contained in the adhesive sheet 1 and the via conductor 2 of
The semiconductor element 4 is bonded and fixed on the wiring board 5 via the adhesive sheet 1, and the electrodes 4 a of the semiconductor element 4 and the connection pads 5 a of the wiring board 5 are electrically connected via the via conductor 2. Become.
【００３３】このとき、ビア導体２に含有される金属粉
末同士が加圧の圧力によって互いに圧接されるとビア導
体２の電気抵抗が小さいものとなり、特に金属粉末とし
て表面が銀で被覆された銅粉末を用いておくと、同粉末
の表面に被覆させた銀が変形して金属粉末同士が良好に
面接触するとともに金属粉末同士の摩擦や熱により金属
粉末同士の接触界面に銀と銅との拡散層が形成され、こ
の拡散層を介して金属粉末同士が良好に接続されるので
ビア導体２の電気抵抗を極めて低いものとすることがで
きる。At this time, when the metal powders contained in the via conductors 2 are pressed against each other by pressurizing pressure, the electric resistance of the via conductors 2 becomes small, and in particular, copper powder whose surface is coated with silver is used as the metal powders. When the powder is used, the silver coated on the surface of the powder is deformed and the metal powders are brought into good surface contact with each other, and the frictional interface between the metal powders and heat causes the silver and copper to be in contact with each other at the contact interface between the metal powders. Since a diffusion layer is formed and the metal powders are well connected to each other via the diffusion layer, the electric resistance of the via conductor 2 can be extremely low.
【００３４】なお、本発明の半導体素子実装用シート３
は、上述の実施の形態の一例に限定されるものではな
い。例えば、上述の実施の形態の一例では接着シート１
は１枚の接着シート層から構成されていたが、接着シー
ト１は２枚以上の複数の接着シート層を積層することに
よって形成されていてもよい。この場合、各接着シート
層に充填される無機絶縁物粉末の充填量を50〜80重量％
とし、接着シートの上面側の接着シート層で80容量％程
度、下面側の接着シート層で50容量％程度となるによう
に接着シートの上面側から下面側に向けて順次小さなも
のとなるようにしておくと、半導体素子実装用シート３
の上面側の熱膨張係数を半導体素子４の熱膨張係数に近
づけるとともに半導体素子実装用シート３の下面側の熱
膨張係数を配線基板５の熱膨張係数に近づけることがで
き、その結果、実装後の半導体素子４と配線基板５との
熱膨張係数の差に起因して発生する熱ストレスをより小
さいものとすることができる。The semiconductor element mounting sheet 3 of the present invention
Is not limited to the example of the above embodiment. For example, in one example of the above-described embodiment, the adhesive sheet 1
Is composed of one adhesive sheet layer, but the adhesive sheet 1 may be formed by laminating two or more adhesive sheet layers. In this case, the filling amount of the inorganic insulating powder filled in each adhesive sheet layer is 50 to 80% by weight.
The adhesive sheet layer on the upper surface side of the adhesive sheet is about 80% by volume, and the adhesive sheet layer on the lower side is about 50% by volume. The semiconductor element mounting sheet 3
The coefficient of thermal expansion of the upper surface of the semiconductor device 4 can be made closer to the coefficient of thermal expansion of the semiconductor element 4 and the coefficient of thermal expansion of the lower surface of the semiconductor element mounting sheet 3 can be made closer to the coefficient of thermal expansion of the wiring board 5. The thermal stress generated due to the difference in the coefficient of thermal expansion between the semiconductor element 4 and the wiring board 5 can be reduced.
【００３５】[0035]
【発明の効果】本発明の半導体素子実装用シートによれ
ば、半導体素子と配線基板との間にシート状で配置され
ることから、従来の液状の熱硬化性樹脂から成るアンダ
ーフィルを注入する場合のように半導体素子の実装位置
の周辺に注入ノズルを配置するための空間のような余計
な空間を設ける必要がなく、配線基板上の半導体素子の
実装位置の周辺に部品を高密度に配置することができ
る。According to the semiconductor element mounting sheet of the present invention, the underfill made of a conventional liquid thermosetting resin is injected since it is arranged in a sheet form between the semiconductor element and the wiring board. There is no need to provide extra space such as the space for placing the injection nozzle around the mounting position of the semiconductor element as in the case, and components are densely arranged around the mounting position of the semiconductor element on the wiring board. can do.
【００３６】また本発明の半導体素子実装用シートによ
れば、半導体素子と配線基板との間にシート状で配置さ
れることから、アンダーフィルを液状の熱硬化性樹脂と
して注入する場合のような良好な流動性を接着シートに
付与する必要はなく、従って接着シート中に多量の無機
絶縁物粉末を充填させることができる。特に、50〜80容
量％の無機絶縁物粉末を充填することによって、硬化後
の接着シートの熱膨張係数を20×10-6／℃以下の小さい
ものとして接着シートと半導体素子および配線基板との
熱ストレスを小さいものとして半導体素子と配線基板と
を強固に接着固定することができるとともに接着シート
の耐湿性や耐熱性を良好なものとして半導体素子を長期
間にわたり正常かつ安定に作動させることが可能であ
る。According to the semiconductor element mounting sheet of the present invention, since the semiconductor element and the wiring board are arranged in a sheet form between the semiconductor element and the wiring board, the underfill is used as a liquid thermosetting resin. It is not necessary to impart good fluidity to the adhesive sheet, so that a large amount of the inorganic insulating powder can be filled in the adhesive sheet. In particular, by filling 50 to 80% by volume of inorganic insulating powder, the cured adhesive sheet has a small thermal expansion coefficient of 20 × 10 −6 / ° C. The semiconductor element and the wiring board can be firmly bonded and fixed with a small thermal stress, and the semiconductor element can operate normally and stably for a long period of time by improving the moisture resistance and heat resistance of the adhesive sheet. It is.
【００３７】さらに、本発明の半導体素子実装用シート
によれば、接着シートを半硬化状態の熱硬化性樹脂中に
無機絶縁物粉末を50〜80容量％充填させた複数の接着シ
ート層を積層することにより形成するとともに各接着シ
ート層に充填された無機絶縁物粉末の充填率を接着シー
トの上面側から下面側に向けて順次小さいものとする
と、半導体素子と配線基板との熱膨張係数の差に起因し
て発生する熱ストレスをより小さいものとすることがで
きる。Further, according to the semiconductor element mounting sheet of the present invention, a plurality of adhesive sheet layers in which an inorganic insulating powder is filled in a thermosetting resin in a semi-cured state with 50 to 80% by volume are laminated. When the filling rate of the inorganic insulating powder filled in each adhesive sheet layer is gradually decreased from the upper surface side to the lower surface side of the adhesive sheet, the coefficient of thermal expansion between the semiconductor element and the wiring substrate is reduced. Thermal stress generated due to the difference can be made smaller.
【図１】本発明の半導体素子実装用シートの実施の形態
の一例を示す断面図である。FIG. 1 is a sectional view showing an example of an embodiment of a semiconductor element mounting sheet of the present invention.
【図２】（ａ）および（ｂ）は、それぞれ本発明の半導
体素子実装用シートを使用して半導体素子を配線基板に
実装する半導体素子の実装方法を説明するための工程毎
の断面図である。FIGS. 2A and 2B are cross-sectional views for each process for explaining a method of mounting a semiconductor element on a wiring board using the semiconductor element mounting sheet of the present invention. is there.
１・・・接着シート ２・・・ビア導体 ３・・・半導体素子実装用シート ４・・・半導体素子 ４ａ・・電極 ５・・・配線基板 ５ａ・・接続パッド DESCRIPTION OF SYMBOLS 1 ... Adhesive sheet 2 ... Via conductor 3 ... Semiconductor element mounting sheet 4 ... Semiconductor element 4a ... Electrode 5 ... Wiring board 5a ... Connection pad
Claims (3)
面に前記電極に接続される接続パッドを有する配線基板
との間に配置され、熱硬化させることにより前記半導体
素子と前記配線基板とを接着固定する半硬化状態の熱硬
化性樹脂から成る接着シートに、前記電極と前記接続パ
ッドとを電気的に接続するための、半硬化状態の熱硬化
性樹脂と金属粉末とを混合して成るビア導体を前記接着
シートを上下に貫通して配設して成ることを特徴とする
半導体素子実装用シート。1. A semiconductor device having an electrode formed on a lower surface thereof and a wiring substrate having a connection pad connected to the electrode on an upper surface, and the semiconductor device and the wiring substrate are thermally cured to form the semiconductor device and the wiring substrate. An adhesive sheet made of a semi-cured thermosetting resin to be bonded and fixed is mixed with a semi-cured thermosetting resin and metal powder for electrically connecting the electrodes and the connection pads. A sheet for mounting a semiconductor element, comprising a via conductor disposed vertically through the adhesive sheet.
性樹脂中に無機絶縁物粉末を５０〜８０容量％充填して
成ることを特徴とする請求項１記載の半導体素子実装用
シート。2. The semiconductor element mounting sheet according to claim 1, wherein the adhesive sheet is formed by filling a semi-cured thermosetting resin with 50 to 80% by volume of an inorganic insulating powder.
性樹脂中に無機絶縁物粉末を５０〜８０容量％充填させ
た複数の接着シート層を積層して成り、該各接着シート
層に充填された無機絶縁物粉末の充填率が前記接着シー
トの上面側から下面側に向けて順次小さくなっているこ
とを特徴とする請求項１または請求項２記載の半導体素
子実装用シート。3. The adhesive sheet is formed by laminating a plurality of adhesive sheet layers in which a semi-cured thermosetting resin is filled with 50 to 80% by volume of an inorganic insulating powder. The semiconductor element mounting sheet according to claim 1, wherein a filling rate of the filled inorganic insulating powder gradually decreases from an upper surface side to a lower surface side of the adhesive sheet.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10015840A JPH11214571A (en) | 1998-01-28 | 1998-01-28 | Sheet for mounting semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10015840A JPH11214571A (en) | 1998-01-28 | 1998-01-28 | Sheet for mounting semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11214571A true JPH11214571A (en) | 1999-08-06 |
Family
ID=11900041
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10015840A Pending JPH11214571A (en) | 1998-01-28 | 1998-01-28 | Sheet for mounting semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11214571A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013018357A1 (en) * | 2011-08-01 | 2013-02-07 | 日本特殊陶業株式会社 | Semiconductor power module, method for manufacturing semiconductor power module, and circuit board |
| JP2013033803A (en) * | 2011-08-01 | 2013-02-14 | Ngk Spark Plug Co Ltd | Circuit board, semiconductor power module and manufacturing method |
| JP2013051389A (en) * | 2011-08-01 | 2013-03-14 | Ngk Spark Plug Co Ltd | Circuit board, semiconductor power module and manufacturing method |
| CN103733330A (en) * | 2011-08-01 | 2014-04-16 | 日本特殊陶业株式会社 | Semiconductor power module, method for manufacturing semiconductor power module, and circuit board |
-
1998
- 1998-01-28 JP JP10015840A patent/JPH11214571A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013018357A1 (en) * | 2011-08-01 | 2013-02-07 | 日本特殊陶業株式会社 | Semiconductor power module, method for manufacturing semiconductor power module, and circuit board |
| JP2013033803A (en) * | 2011-08-01 | 2013-02-14 | Ngk Spark Plug Co Ltd | Circuit board, semiconductor power module and manufacturing method |
| JP2013051389A (en) * | 2011-08-01 | 2013-03-14 | Ngk Spark Plug Co Ltd | Circuit board, semiconductor power module and manufacturing method |
| CN103733330A (en) * | 2011-08-01 | 2014-04-16 | 日本特殊陶业株式会社 | Semiconductor power module, method for manufacturing semiconductor power module, and circuit board |
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