JP2675714B2 - Manufacturing method of protruding electrode - Google Patents
Manufacturing method of protruding electrodeInfo
- Publication number
- JP2675714B2 JP2675714B2 JP9463492A JP9463492A JP2675714B2 JP 2675714 B2 JP2675714 B2 JP 2675714B2 JP 9463492 A JP9463492 A JP 9463492A JP 9463492 A JP9463492 A JP 9463492A JP 2675714 B2 JP2675714 B2 JP 2675714B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- electrode
- bump
- bump electrodes
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Description
【０００１】[0001]
【産業上の利用分野】本発明は、突起電極を具備した半
導体装置実装用基板と半導体装置とをフェースダウンボ
ンディングで接続搭載することにより実装する突起電極
の製法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a bump electrode which is mounted by connecting and mounting a semiconductor device mounting substrate having a bump electrode by face-down bonding.
【０００２】[0002]
【従来の技術】半導体装置を突起状電極であるバンプ電
極を介して半導体装置実装用基板にフェースダウンボン
ディングする実装構造は、ワイヤボンディングによる実
装構造に比較して高密度の実装が可能であり、ギャング
（一括）ボンディングができるために実装時間を短くす
ることができる等の優れた特長がある。2. Description of the Related Art A mounting structure in which a semiconductor device is face-down bonded to a semiconductor device mounting substrate via bump electrodes, which are protruding electrodes, enables higher density mounting than a mounting structure by wire bonding. Since gang (batch) bonding can be performed, it has excellent features such as shortening the mounting time.
【０００３】図６は従来の半導体装置実装構造に於い
て、バンプ電極を具備した半導体装置実装用基板９と半
導体装置１とをフェースダウンボンディングにより接続
したものの断面図を示している。ここで、バンプ電極
５，５′（５′は潰れて横に広がった状態のバンプ電極
を示す）は、銅層８（約１８μｍ）にニッケルメッキ層
７（約５〜１０μｍ）を施したリード上にフォトリソグ
ラフィ工程によりレジストに窓明け工作を行い、その部
分に電解金メッキを施して、最後にレジストを剥離する
ことにより形成する。FIG. 6 shows a sectional view of a conventional semiconductor device mounting structure in which a semiconductor device mounting substrate 9 having bump electrodes and a semiconductor device 1 are connected by face-down bonding. Here, the bump electrodes 5 and 5 '(5' indicates a bump electrode in a state of being crushed and spread laterally) are leads obtained by applying a nickel plating layer 7 (about 5 to 10 .mu.m) to a copper layer 8 (about 18 .mu.m). The resist is subjected to a windowing process by a photolithography process, electrolytic gold plating is applied to that portion, and finally the resist is peeled off to form the film.
【０００４】このようにして構成されたバンプ電極５，
５′は、半導体装置実装用基板９内のメッキ電流のバラ
ツキとか、メッキ液の状態及び半導体装置実装用基板９
の反り、膨れ等に起因してバンプ電極５，５′の表面の
高さが一致せず、同一平面上に揃わないのでバラツキを
生ずるのである。図６は前述のような工程を経て形成さ
れたバンプ電極の高さのバラツキを示したもので、この
ようなバラツキを有するバンプ電極５，５′と半導体装
置１の電極パッド２，２′とは、熱圧着又は導電性ペー
スト３（異方性導電接着剤を含む）を介して熱圧着又は
圧接等により電気的に接続されている。The bump electrodes 5 thus configured
5'is the variation of the plating current in the semiconductor device mounting substrate 9, the state of the plating solution, and the semiconductor device mounting substrate 9
The heights of the surfaces of the bump electrodes 5 and 5'do not match and are not aligned on the same plane due to warpage, swelling, etc., so that variations occur. FIG. 6 shows variations in the height of the bump electrodes formed through the above-mentioned steps. The bump electrodes 5 and 5'having such variations and the electrode pads 2 and 2'of the semiconductor device 1 are shown. Are electrically connected by thermocompression bonding or pressure contact or the like via thermocompression bonding or conductive paste 3 (including an anisotropic conductive adhesive).
【０００５】このバンプ電極５，５′は、表面の高さの
バラツキが大きいために半導体装置１の電極パッド２，
２′との当たり具合が様々異なるので、バンプ電極５，
５′と電極パッド２，２′とが接触しない場合が起こ
る。全てのバンプ電極５，５′を半導体装置１の電極パ
ッド２，２′と接触させるためには、最も高さの低いバ
ンプ電極５に合わせて半導体装置実装用基板９の上方向
から平行に半導体装置１を押し込むから、このとき高さ
の高い方の他のバンプ電極５′を潰して平坦化しなけれ
ばならない。The bump electrodes 5 and 5 ′ have large variations in surface height, and therefore the electrode pads 2 and 5 of the semiconductor device 1.
The bump electrode 5,
In some cases, the 5'and the electrode pads 2, 2'are not in contact with each other. In order to bring all the bump electrodes 5, 5 ′ into contact with the electrode pads 2, 2 ′ of the semiconductor device 1, the semiconductor device mounting substrate 9 is parallel to the semiconductor device mounting substrate 9 in parallel with the bump electrode 5 having the lowest height. Since the device 1 is pushed in, the other bump electrode 5'of higher height must be crushed and flattened at this time.
【０００６】然しながら、このような方法は比較的高温
の熱圧着による金属接合（バンプ電極の金と半導体装置
のパッドアルミニウムとの合金）では可能であるが、バ
ンプ電極の数が多く（例えば２００以上）、又は半導体
装置が大きい場合（例えば１０ｍｍ角以上）にはかなり
困難であり、半導体装置を押し込むための荷重制御及び
平衡度の維持が困難となり高度の実装技術を要すること
となる。However, although such a method is possible for metal bonding (alloy of gold of bump electrodes and pad aluminum of semiconductor devices) by thermocompression bonding at a relatively high temperature, the number of bump electrodes is large (for example, 200 or more). ), Or if the semiconductor device is large (for example, 10 mm square or more), it is quite difficult, and it becomes difficult to control the load for pushing the semiconductor device and maintain the equilibrium level, which requires advanced packaging technology.
【０００７】又図７に示すように比較的低温の熱圧着に
よる方法で、半導体装置１を半導体装置実装用基板９と
フェースダウンボンディングにより接続する場合は、通
常導電性粒子４，４′を、バンプ電極５，５′と半導体
装置１の電極パッド２，２′との間に介在させて、周囲
を合成樹脂接着剤層３の硬化により固めた状態を示した
ものの断面図である。導電性粒子４，４′は、合成樹脂
製ボールに金メッキしたもの、単体の銀，銅，金等の金
属粒子等があり、通常約２〜２０μｍである。Further, as shown in FIG. 7, when the semiconductor device 1 is connected to the semiconductor device mounting substrate 9 by face-down bonding by the method of thermocompression bonding at a relatively low temperature, the conductive particles 4, 4 ′ are usually FIG. 3 is a cross-sectional view showing a state in which bump electrodes 5, 5 ′ are interposed between electrode pads 2, 2 ′ of semiconductor device 1 and the periphery is hardened by curing synthetic resin adhesive layer 3. The conductive particles 4 and 4'are made of synthetic resin balls plated with gold, individual metal particles of silver, copper, gold or the like, and are usually about 2 to 20 μm.
【０００８】ここで、バンプ電極５，５′の高さのバラ
ツキが、導電性粒子４，４′の径に比較して大きい場合
は、バンプ電極５′と電極パッド２′との間に挟まれて
いる導電性粒子４′は、バンプ電極５′と電極パッド
２′に埋没することになり、導電性機能としての役割を
果たさないのである。換言すれば、バンプ電極５′の表
面と電極パッド２′とが圧接状態とになり、半導体装置
１と半導体装置実装用基板９との間の膨張等による応力
を、導電性粒子４，４′の弾性により緩和させるという
機能が無くなるのである。If the height variation of the bump electrodes 5 and 5'is larger than the diameter of the conductive particles 4 and 4 ', the bump electrodes 5 and 5'are sandwiched between the bump electrode 5'and the electrode pad 2'. The conductive particles 4'being buried in the bump electrodes 5'and the electrode pads 2'do not play a role as a conductive function. In other words, the surface of the bump electrode 5'and the electrode pad 2'become in pressure contact with each other, and stress due to expansion or the like between the semiconductor device 1 and the semiconductor device mounting substrate 9 is applied to the conductive particles 4, 4 '. The function of relaxing by the elasticity of is lost.
【０００９】[0009]
【発明が解決しようとする課題】この導電性粒子は、上
下方向から挟まれたとき、その弾性による反作用により
変形しながら半導体装置の電極パッドとバンプ電極との
接触を維持する機能を持つものであって、低温で接合す
る場合はバンプ電極の上面を同一平面内に一致させるよ
うに平坦化することが不可欠となる。When the conductive particles are sandwiched from above and below, the conductive particles have a function of maintaining contact between the electrode pads of the semiconductor device and the bump electrodes while being deformed by the reaction due to their elasticity. Therefore, when joining at a low temperature, it is essential to flatten the upper surface of the bump electrode so that the upper surface of the bump electrode is aligned with the same plane.
【００１０】本発明に係る突起電極の製法はこのような
問題点に鑑み、複数個のバンプ電極の上面を同一平面内
に一致させるように平坦化することを目的としている。In view of such a problem, the method of manufacturing the bump electrode according to the present invention aims to flatten the upper surfaces of the plurality of bump electrodes so that they are in the same plane.
【００１１】[0011]
【課題を解決するための手段】前記の目的を達成するた
めに、本発明に係る突起電極の製法は、下層に銅メッキ
層を設けると共に、その上層にニッケルメッキ層を設
け、更にその上層に金メッキ層を設けた構成を有するリ
ード表面で、フェースダウンボンディングにより搭載さ
れる半導体装置の電極パッドと対向する部分に、金メッ
キにより柱状の突起電極を形成し、且つこの突起電極を
半導体装置実装用基板の上方向から平板により押圧し
て、半導体装置の電極パッドとの接触面となる複数個の
突起電極の表面を、同一平面内に一致させるように平坦
化するものである。In order to achieve the above-mentioned object, a method of manufacturing a bump electrode according to the present invention is such that a copper plating layer is provided as a lower layer, a nickel plating layer is provided as an upper layer, and a nickel plating layer is further provided as an upper layer. A columnar protruding electrode is formed by gold plating on a portion of the lead surface having a structure provided with a gold plating layer, which faces the electrode pad of the semiconductor device mounted by face-down bonding, and the protruding electrode is used as a substrate for mounting a semiconductor device. The flat plate is pressed from above to flatten the surfaces of the plurality of projecting electrodes, which are the contact surfaces with the electrode pads of the semiconductor device, so as to coincide with each other in the same plane.
【００１２】[0012]
【作用】次に本発明に係る突起電極の製法の作用につい
て述べる。銅メッキ層の上層にニッケルメッキ層を設
け、且つそのニッケルメッキ層の上層に金メッキ層を設
けた構成を有するリード表面を設ける。そしてそのリー
ド表面に於いてフェースダウンボンディングにより搭載
される半導体装置の電極パッドと対向する部分に、金メ
ッキにより柱状の突起電極を形成するもので、この突起
電極を半導体装置実装用基板の上方向から平板により押
圧することにより、半導体装置の電極パッドとの接触面
となる複数個の突起電極の表面を同一平面内に一致する
ように平坦化するのである。Next, the function of the method of manufacturing the protruding electrode according to the present invention will be described. A lead surface having a structure in which a nickel plating layer is provided on the copper plating layer and a gold plating layer is provided on the nickel plating layer is provided. Then, a columnar protruding electrode is formed by gold plating on a portion of the lead surface facing the electrode pad of the semiconductor device mounted by face-down bonding. The protruding electrode is formed from above the semiconductor device mounting substrate. By pressing with the flat plate, the surfaces of the plurality of protruding electrodes, which are the contact surfaces with the electrode pads of the semiconductor device, are flattened so as to coincide with each other in the same plane.
【００１３】[0013]
【実施例】以下図面を参照しながら本発明に係る突起電
極の製法の実施例を具体的に説明する。図１は本発明に
係る突起電極の製法の第１実施例を示したものの断面図
である。図に於いて、半導体装置実装用基板９の材質
は、比較的高温（約２００°Ｃ以上）で半導体装置を接
合する場合は、アルミナのようなセラミック系材料を使
用し、又比較的低温で半導体装置１を接合する場合は、
ポリイミド，ガラエボ等の有機材料を使用する。Embodiments of the method for manufacturing a bump electrode according to the present invention will be specifically described below with reference to the drawings. FIG. 1 is a cross-sectional view showing a first embodiment of a method for manufacturing a bump electrode according to the present invention. In the figure, the semiconductor device mounting substrate 9 is made of a ceramic material such as alumina when the semiconductor device is bonded at a relatively high temperature (about 200 ° C. or higher). When joining the semiconductor device 1,
Use organic materials such as polyimide and glass evo.
【００１４】半導体装置実装用基板９の上に、銅導体層
８を形成するのであるが、この銅導体層８は、半導体装
置実装用基板９が、セラミック系材料の場合は無電解メ
ッキ法により又有機材料の場合は銅箔を接着したのち、
エッチングする法（サブストラクティブアデイティ法）
等の方法により形成するもので、この銅導体層８上には
ニッケルメッキ層７、更にその上層に緩衝層として金メ
ッキ層６を積層する。金メッキ層６の厚みは、この上に
形成されるバンプ電極５，５′の高さのバラツキを吸収
するだけの厚みが最小限度必要であり、バンプ電極５，
５′の高さのバラツキを例えば５μｍとすると、これ以
上の厚みが必要となる。The copper conductor layer 8 is formed on the semiconductor device mounting substrate 9. The copper conductor layer 8 is formed by electroless plating when the semiconductor device mounting substrate 9 is a ceramic material. In the case of organic materials, after bonding copper foil,
Etching method (subtractive additivity method)
The nickel plating layer 7 is laminated on the copper conductor layer 8 and the gold plating layer 6 is laminated thereon as a buffer layer. The gold plating layer 6 needs to have a minimum thickness enough to absorb the height variations of the bump electrodes 5 and 5 ′ formed on the gold plating layer 6.
If the variation of the height of 5'is 5 μm, for example, the thickness more than this is required.
【００１５】そして、この上にフォトリソグラフィ工程
によりレジストを半導体装置実装用基板９の全面に略均
一の厚さで塗布し、その後露光により窓明け工作を行
い、この窓明け部に電解金メッキを施して柱状のバンプ
電極５，５′を形成し、最後にレジストを薬剤又はドラ
イエッチング等により剥離するのである。この状態を図
３に示しているが、バンプ電極５，５′は高さのバラツ
キを想定して図３を示すように右側のバンプ電極５′
は、左側のバンプ電極５に比較して若干高く設定された
状態にある。Then, a resist is applied to the entire surface of the semiconductor device mounting substrate 9 in a substantially uniform thickness by a photolithography process, and then a window opening work is performed by exposure, and electrolytic gold plating is applied to the window opening portion. The columnar bump electrodes 5 and 5'are thus formed, and finally the resist is peeled off by chemicals or dry etching. Although this state is shown in FIG. 3, the bump electrodes 5 and 5'are provided on the right side of the bump electrode 5'as shown in FIG.
Is in a state of being set slightly higher than the left bump electrode 5.
【００１６】バンプ電極５，５′の高さのバラツキをな
くするために、図４に示すように平板１０により、半導
体装置実装用基板９の上方向から平行に加圧又は加熱し
て、高い方のバンプ電極５′を押圧するのであるが、バ
ンプ電極５′はその下部が金メッキ層６に埋設されてい
るために露出されている部分は変形しないのである。図
５は平板１０を除去して、バンプ電極５，５′の高さを
略同じ高さの線ａ上に一致させた状態を示した断面図で
ある。In order to eliminate the variation in height of the bump electrodes 5 and 5 ', the flat plate 10 is pressed or heated in parallel from above the semiconductor device mounting substrate 9 as shown in FIG. The other bump electrode 5'is pressed, but since the lower portion of the bump electrode 5'is embedded in the gold plating layer 6, the exposed portion is not deformed. FIG. 5 is a cross-sectional view showing a state in which the plate 10 is removed and the heights of the bump electrodes 5 and 5'are aligned with the line a having substantially the same height.
【００１７】このようなバンプ電極５，５′を具備した
半導体装置実装用基板９と半導体装置１は、フェースダ
ウンボンディングにより搭載するのであるが、図１の第
１実施例では、異方性導電樹脂の接着剤３を半導体装置
実装用基板９又は半導体装置１に塗布してから、半導体
装置１の電極パッド２，２′とバンプ電極５，５′の位
置を合致させた後、上方向から平行に加圧し、同時に加
熱して異方性導電樹脂の接着剤層３を硬化して固着する
ことにより接合するのである。このようにして電極パッ
ド２，２′とバンプ電極５，５′とは導電性粒子４，
４′を介して電気的に接触するのである。The semiconductor device mounting substrate 9 having the bump electrodes 5 and 5'and the semiconductor device 1 are mounted by face-down bonding. In the first embodiment shown in FIG. After the resin adhesive 3 is applied to the semiconductor device mounting substrate 9 or the semiconductor device 1, the electrode pads 2, 2 ′ of the semiconductor device 1 and the bump electrodes 5, 5 ′ are aligned with each other, and then from above. The pressure is applied in parallel and heating is performed at the same time to cure and fix the adhesive layer 3 of the anisotropic conductive resin so that the adhesive layer 3 is bonded. In this way, the electrode pads 2, 2'and the bump electrodes 5, 5'are made of the conductive particles 4,
It makes electrical contact via 4 '.
【００１８】図２は本発明に係る突起電極の製法の第２
実施例を示したものの断面図であって、バンプ電極５，
５′を形成する工程は前記した図１の第１実施例の場合
と同様であるが、半導体装置１をフェースダウンボンデ
ィングにより半導体装置実装用基板９に接合するための
実装構造が相違しており、バンプ電極５，５′と電極パ
ッド２，２′とは直接電気的に接触した状態にある。こ
れは半導体装置実装用基板９が特に高温で使用すること
ができる場合に可能な方法として、セラミック系材料を
使用した場合に熱圧着温度を約４００°Ｃ以上とする
と、アルミニウムの電極パッド２，２′とバンプ電極パ
ッド５，５′との合金接合により接合しているのであ
る。FIG. 2 shows a second method of manufacturing a protruding electrode according to the present invention.
FIG. 3 is a cross-sectional view of an example showing bump electrodes 5,
The step of forming 5'is the same as in the case of the first embodiment of FIG. 1 described above, but the mounting structure for bonding the semiconductor device 1 to the semiconductor device mounting substrate 9 by face-down bonding is different. The bump electrodes 5, 5'and the electrode pads 2, 2'are in direct electrical contact with each other. This is a possible method when the semiconductor device mounting substrate 9 can be used at a particularly high temperature, and when the thermocompression bonding temperature is about 400 ° C. or higher when a ceramic material is used, the aluminum electrode pad 2, 2'and the bump electrode pads 5, 5'are joined by alloy joining.
【００１９】なお、図８は電解金メッキで形成されたバ
ンプ電極の高さ（μｍ）とバンプ電極の個数（ｎ）との
関係を示すグラフ図である。FIG. 8 is a graph showing the relationship between the height (μm) of bump electrodes formed by electrolytic gold plating and the number (n) of bump electrodes.
【００２０】[0020]
【発明の効果】本発明に係る突起電極の製法は前記のよ
うに構成して成るもので、バンプ電極の下層に緩衝層と
なる金メッキ層を所定の厚みに設けているために、バン
プ電極の高さを揃えることができて、半導体装置実装用
基板の反りとかメッキ条件等によるバンプ電極の高さの
バラツキを軽減することができることになり、各バンプ
電極と半導体装置の電極パッドとを極めて安定した状態
で、而も略均等な強度により接合して、機械的なストレ
スは勿論のこと熱的ストレスに対しても大きな強度を付
与することになり、実装技術の信頼性を著しく向上でき
る効果がある。The method of manufacturing the bump electrode according to the present invention is configured as described above. Since the gold plating layer serving as a buffer layer is formed to a predetermined thickness under the bump electrode, the bump electrode Since the heights can be made uniform, variations in bump electrode height due to warpage of the semiconductor device mounting board, plating conditions, etc. can be reduced, and each bump electrode and the electrode pad of the semiconductor device are extremely stable. In this state, the bonding is performed with substantially equal strength, and great strength is given not only to mechanical stress but also to thermal stress, which has the effect of significantly improving the reliability of mounting technology. is there.
【図１】本発明に係る突起電極の製法の第１実施例を示
したものの断面図。FIG. 1 is a cross-sectional view showing a first embodiment of a method of manufacturing a bump electrode according to the present invention.
【図２】本発明に係る突起電極の製法の第２実施例を示
したものの断面図。FIG. 2 is a cross-sectional view showing a second embodiment of the method of manufacturing the bump electrode according to the present invention.
【図３】バンプ電極の高さのバラツキ状態を示したもの
の断面図。FIG. 3 is a cross-sectional view showing a state in which the height of bump electrodes varies.
【図４】平板により、半導体装置実装用基板の上方向か
ら平行に加圧した状態を示したものの断面図。FIG. 4 is a cross-sectional view showing a state in which pressure is applied parallel to the semiconductor device mounting board from above by a flat plate.
【図５】平板を除去して、バンプ電極の高さを略同じ高
さの線上に一致させた状態を示したものの断面図。FIG. 5 is a cross-sectional view showing a state in which the flat plate is removed and the heights of the bump electrodes are made to match the lines of substantially the same height.
【図６】従来の半導体装置実装構造に於いて、バンプ電
極の高さのバラツキを示したものの断面図。FIG. 6 is a sectional view showing a variation in height of bump electrodes in a conventional semiconductor device mounting structure.
【図７】バンプ電極と電極パッドとの間に、導電性粒子
を介在させて周囲を合成樹脂接着剤層の硬化により固め
た状態を示したものの断面図。FIG. 7 is a cross-sectional view showing a state in which conductive particles are interposed between the bump electrode and the electrode pad and the periphery is solidified by curing the synthetic resin adhesive layer.
【図８】電解金メッキにより形成されたバンプ電極の高
さとバンプ電極の個数との関係を示すグラフ図。FIG. 8 is a graph showing the relationship between the height of bump electrodes formed by electrolytic gold plating and the number of bump electrodes.
１ 半導体装置 ２，２′ 電極パッド ３，３′ 異方性導電樹脂の接着剤層 ４，４′ 導電性粒子 ５，５′ バンプ電極 ６ 金メッキ層 ７ ニッケルメッキ層 ８ 銅層 ９ 半導体実装用基板 1 Semiconductor Device 2,2 'Electrode Pad 3,3' Anisotropic Conductive Resin Adhesive Layer 4,4 'Conductive Particles 5,5' Bump Electrode 6 Gold Plating Layer 7 Nickel Plating Layer 8 Copper Layer 9 Semiconductor Mounting Substrate
Claims (1)
上層にニッケルメッキ層を設け、更にその上層に金メッ
キ層を設けた構成を有するリード表面で、フェースダウ
ンボンディングにより搭載される半導体装置の電極パッ
ドと対向する部分に、金メッキにより柱状の突起電極を
形成し、且つこの突起電極を半導体装置実装用基板の上
方向から平板により押圧して、半導体装置の電極パッド
との接触面となる複数個の突起電極の表面を、同一平面
内に一致させるように平坦化することを特徴とする突起
電極の製法。1. An electrode of a semiconductor device mounted by face down bonding on a lead surface having a copper plating layer as a lower layer, a nickel plating layer as an upper layer, and a gold plating layer as an upper layer. A plurality of pillar-shaped protruding electrodes are formed by gold plating on the portions facing the pads, and the protruding electrodes are pressed by a flat plate from above the semiconductor device mounting substrate to form contact surfaces with the electrode pads of the semiconductor device. The method for producing a bump electrode, wherein the surface of the bump electrode is flattened so as to be in the same plane.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9463492A JP2675714B2 (en) | 1992-04-15 | 1992-04-15 | Manufacturing method of protruding electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9463492A JP2675714B2 (en) | 1992-04-15 | 1992-04-15 | Manufacturing method of protruding electrode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05291261A JPH05291261A (en) | 1993-11-05 |
| JP2675714B2 true JP2675714B2 (en) | 1997-11-12 |
Family
ID=14115703
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9463492A Expired - Lifetime JP2675714B2 (en) | 1992-04-15 | 1992-04-15 | Manufacturing method of protruding electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2675714B2 (en) |
-
1992
- 1992-04-15 JP JP9463492A patent/JP2675714B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05291261A (en) | 1993-11-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2010070806A1 (en) | Semiconductor device, flip-chip mounting method and flip-chip mounting apparatus | |
| US20020084522A1 (en) | Semiconductor device using interposer substrate and manufacturing method therefor | |
| JPH09298255A (en) | Ceramic circuit board and semiconductor device using the board | |
| JP2002033411A (en) | Semiconductor device with heat spreader and its manufacturing method | |
| US6207550B1 (en) | Method for fabricating bump electrodes with a leveling step for uniform heights | |
| JP2001189337A (en) | Electrode bump, semiconductor element using the same, and semiconductor device | |
| US6528889B1 (en) | Electronic circuit device having adhesion-reinforcing pattern on a circuit board for flip-chip mounting an IC chip | |
| JPH09199635A (en) | Multilayer film for forming circuit substrate, multilayer circuit substrate using it, and package for semiconductor device | |
| JP2003007922A (en) | Method of manufacturing circuit device | |
| JP2000277649A (en) | Semiconductor and manufacture of the same | |
| JP4479582B2 (en) | Manufacturing method of electronic component mounting body | |
| JP2675714B2 (en) | Manufacturing method of protruding electrode | |
| JP3274619B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP3519924B2 (en) | Semiconductor device structure and method of manufacturing the same | |
| JP4030220B2 (en) | Semiconductor chip mounting structure | |
| JP2002289735A (en) | Semiconductor device | |
| JP2000068321A (en) | Semiconductor device and manufacture thereof | |
| JP3419398B2 (en) | Method for manufacturing semiconductor device | |
| JP3120837B2 (en) | Resin film for electrical connection and electrical connection method using the resin film | |
| JP3337922B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP4342577B2 (en) | Semiconductor chip mounting structure | |
| JPH0982835A (en) | Circuit substrate and multilayer circuit substrate | |
| JPH11214571A (en) | Sheet for mounting semiconductor element | |
| JP2003234451A (en) | Semiconductor device and its fabricating method | |
| JPH11150155A (en) | Manufacture of semiconductor device and circuit board holding jig there for |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19970701 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20070718 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080718 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090718 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090718 Year of fee payment: 12 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090718 Year of fee payment: 12 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090718 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100718 Year of fee payment: 13 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100718 Year of fee payment: 13 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110718 Year of fee payment: 14 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120718 Year of fee payment: 15 |
|
| EXPY | Cancellation because of completion of term | ||
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120718 Year of fee payment: 15 |