JP2000150557A5 - - Google Patents
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- JP2000150557A5 JP2000150557A5 JP1998324125A JP32412598A JP2000150557A5 JP 2000150557 A5 JP2000150557 A5 JP 2000150557A5 JP 1998324125 A JP1998324125 A JP 1998324125A JP 32412598 A JP32412598 A JP 32412598A JP 2000150557 A5 JP2000150557 A5 JP 2000150557A5
- Authority
- JP
- Japan
- Prior art keywords
- terminals
- electrode pads
- bumps
- main surface
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- 239000004065 semiconductor Substances 0.000 claims description 10
- 229910000679 solder Inorganic materials 0.000 claims description 4
- 239000011347 resin Substances 0.000 claims 5
- 229920005989 resin Polymers 0.000 claims 5
- 238000007747 plating Methods 0.000 claims 3
- 238000007789 sealing Methods 0.000 claims 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims 1
- 229910052802 copper Inorganic materials 0.000 claims 1
- 239000010949 copper Substances 0.000 claims 1
- 238000005498 polishing Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005755 formation reaction Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
Description
【発明の名称】半導体装置およびその実装構造体並びに半導体装置の製造方法Patent application title: SEMICONDUCTOR DEVICE, MOUNTING STRUCTURE THEREOF, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
【図６】半田バンプ形成工程を示しており、（ａ）は半田ボール供給作業を示す拡大部分正面断面図、（ｂ）は半田バンプ形成工程後を示す拡大部分正面断面図である。6A and 6B show a solder bump formation process, wherein FIG. 6A is an enlarged partial front sectional view showing a solder ball supply operation, and FIG. 6B is an enlarged partial front sectional view showing a solder bump formation process;
Claims (5)
前記半導体ウエハの第一主面上および前記複数の端子上を樹脂膜によって覆う工程と、 Covering the first main surface of the semiconductor wafer and the plurality of terminals with a resin film;
前記樹脂膜を研磨して前記複数の端子それぞれの一部を露出する工程と、 Polishing the resin film to expose a part of each of the plurality of terminals;
前記露出された複数の端子それぞれに接続する複数のバンプを形成する工程と、 Forming a plurality of bumps connected to each of the plurality of exposed terminals;
前記複数のバンプが形成された半導体ウエハをダイシングにより複数のチップに分割する工程とを有することを特徴とする半導体装置の製造方法。 And d) dividing the semiconductor wafer on which the plurality of bumps are formed into a plurality of chips by dicing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10324125A JP2000150557A (en) | 1998-11-13 | 1998-11-13 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10324125A JP2000150557A (en) | 1998-11-13 | 1998-11-13 | Semiconductor device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000150557A JP2000150557A (en) | 2000-05-30 |
| JP2000150557A5 true JP2000150557A5 (en) | 2004-10-28 |
Family
ID=18162437
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10324125A Pending JP2000150557A (en) | 1998-11-13 | 1998-11-13 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000150557A (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100881389B1 (en) | 2002-12-26 | 2009-02-05 | 주식회사 하이닉스반도체 | Method for packaging semiconductor device |
| JP2004273591A (en) * | 2003-03-06 | 2004-09-30 | Seiko Epson Corp | Semiconductor device and its fabricating process |
| JP4057017B2 (en) | 2005-01-31 | 2008-03-05 | 富士通株式会社 | Electronic device and manufacturing method thereof |
| JP4566915B2 (en) * | 2006-01-10 | 2010-10-20 | 大日本印刷株式会社 | Semiconductor device mounting body and method of manufacturing semiconductor device mounting body |
| US8742603B2 (en) | 2010-05-20 | 2014-06-03 | Qualcomm Incorporated | Process for improving package warpage and connection reliability through use of a backside mold configuration (BSMC) |
| US8461676B2 (en) | 2011-09-09 | 2013-06-11 | Qualcomm Incorporated | Soldering relief method and semiconductor device employing same |
| JP6635328B2 (en) | 2014-11-10 | 2020-01-22 | ローム株式会社 | Semiconductor device and method of manufacturing the same |
-
1998
- 1998-11-13 JP JP10324125A patent/JP2000150557A/en active Pending
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