JP2001144213A5 - - Google Patents

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Publication number
JP2001144213A5
JP2001144213A5 JP1999325159A JP32515999A JP2001144213A5 JP 2001144213 A5 JP2001144213 A5 JP 2001144213A5 JP 1999325159 A JP1999325159 A JP 1999325159A JP 32515999 A JP32515999 A JP 32515999A JP 2001144213 A5 JP2001144213 A5 JP 2001144213A5
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Japan
Prior art keywords
semiconductor
forming
insulating film
semiconductor device
chip
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Pending
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JP1999325159A
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Japanese (ja)
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JP2001144213A (en
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Priority to JP32515999A priority Critical patent/JP2001144213A/en
Priority claimed from JP32515999A external-priority patent/JP2001144213A/en
Publication of JP2001144213A publication Critical patent/JP2001144213A/en
Publication of JP2001144213A5 publication Critical patent/JP2001144213A5/ja
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Claims (7)

（ａ）分割領域によって区画された複数のチップ形成領域を有する半導体ウエハであって、前記複数のチップ形成領域の各々が複数の半導体素子と複数のボンディングパッドとを有する半導体ウエハを準備する工程、
（ｂ）前記チップ形成領域の各々の複数のボンディングパッドに電気的に接続された導体部を形成する工程、
（ｃ）前記分割領域に溝部を形成する工程、
（ｄ）前記溝部内を含む前記半導体ウエハの主面上に封止用絶縁膜を形成する工程、
（ｅ）前記半導体ウエハを前記溝部に沿って切断することにより、前記導体部が形成され、前記封止用絶縁膜の一部が側面に形成された複数の半導体チップを形成する工程、
を含むことを特徴とする半導体装置の製造方法。(A) a step of preparing a semiconductor wafer having a plurality of chip formation regions partitioned by divided regions, each of the plurality of chip formation regions having a plurality of semiconductor elements and a plurality of bonding pads;
(B) forming a conductor portion electrically connected to each of the plurality of bonding pads in the chip formation region;
(C) forming a groove in the divided region;
(D) forming a sealing insulating film on the main surface of the semiconductor c d c including the groove portion,
(E) cutting the semiconductor wafer along the groove to form a plurality of semiconductor chips in which the conductor is formed and a part of the sealing insulating film is formed on a side surface;
A method for manufacturing a semiconductor device, comprising: （ａ）分割領域によって区画された複数のチップ形成領域を有する半導体ウエハであって、前記複数のチップ形成領域の各々が複数の半導体素子と複数のボンディングパッドとを有する半導体ウエハを準備する工程、
（ｂ）前記チップ形成領域の各々の複数のボンディングパッドに電気的に接続された導体部を形成する工程、
（ｃ）前記分割領域に溝部を形成する工程、
（ｄ）前記溝部内を含む前記半導体ウエハの主面上に封止用絶縁膜を形成する工程、
（ｅ）前記半導体ウエハの裏面を研磨し、前記溝部内に形成した封止用絶縁膜を前記溝部の底面から前記半導体ウエハの裏面に露出させる工程、
（ｆ）前記半導体ウエハを前記溝部に沿って切断することにより、前記導体部が形成され、前記封止用絶縁膜の一部が側面に形成された複数の半導体チップを形成する工程、
を含むことを特徴とする半導体装置の製造方法。(A) a step of preparing a semiconductor wafer having a plurality of chip formation regions partitioned by divided regions, each of the plurality of chip formation regions having a plurality of semiconductor elements and a plurality of bonding pads;
(B) forming a conductor portion electrically connected to each of the plurality of bonding pads in the chip formation region;
(C) forming a groove in the divided region;
(D) forming a sealing insulating film on the main surface of the semiconductor c d c including the groove portion,
(E) said polishing the back surface of the semiconductor wafer, thereby exposing the sealing insulating film formed in said groove from a bottom surface of the groove on the back surface of the semiconductor c d c,
(F) cutting the semiconductor wafer along the groove to form a plurality of semiconductor chips in which the conductor is formed and a part of the sealing insulating film is formed on a side surface;
A method for manufacturing a semiconductor device, comprising: 請求項１または２記載の半導体装置の製造方法であって、前記複数の半導体チップを形成する前に前記半導体ウエハの主面上の端子位置に半田バンプを電気的に接続する工程を含むことを特徴とする半導体装置の製造方法。A method of manufacturing a semiconductor device according to claim 1, including the semiconductor c d c a step of electrically connecting the solder bumps to terminal positions on the main surface of prior to forming said plurality of semiconductor chips A method for manufacturing a semiconductor device. 半導体チップの主面上に複数の半導体素子が形成された半導体装置であって、前記半導体チップの上面および側面が封止用絶縁膜で覆われ、下面には前記半導体チップの底面が露出する構造を有することを特徴とする半導体装置。  A semiconductor device in which a plurality of semiconductor elements are formed on a main surface of a semiconductor chip, wherein a top surface and a side surface of the semiconductor chip are covered with a sealing insulating film, and a bottom surface of the semiconductor chip is exposed on a bottom surface A semiconductor device comprising: 請求項４記載の半導体装置であって、前記半導体チップの側面の一部または全面が封止用絶縁膜で覆われた構造を有することを特徴とする半導体装置。  5. The semiconductor device according to claim 4, wherein a part or the whole of the side surface of the semiconductor chip is covered with a sealing insulating film. 請求項４または５記載の半導体装置であって、前記半導体チップは封止用絶縁膜で覆われた後、下面が研磨された構造を有することを特徴とする半導体装置。A semiconductor device according to claim 4 or 5 Symbol mounting, after the semiconductor chip is covered by a sealing insulating film, semiconductor device and having a lower surface is polished structure. （ａ）分割領域によって区画された複数のチップ形成領域を有する半導体ウエハであって、前記複数のチップ形成領域の各々が複数の半導体素子と複数のボンディングパッドとを有する半導体ウエハを準備する工程、(A) a step of preparing a semiconductor wafer having a plurality of chip formation regions partitioned by divided regions, each of the plurality of chip formation regions having a plurality of semiconductor elements and a plurality of bonding pads;
（ｂ）前記チップ形成領域の各々の複数のボンディングパッドに接続される配線層を形成する工程、(B) forming a wiring layer connected to each of the plurality of bonding pads in the chip formation region;
（ｃ）前記配線層にメタルポストを形成する工程、(C) forming a metal post on the wiring layer;
（ｄ）前記半導体ウエハの主面上に前記メタルポストの上面が露出するように封止用絶縁膜を形成する工程、(D) forming a sealing insulating film on the main surface of the semiconductor wafer so that the upper surface of the metal post is exposed;
（ｅ）前記露出したメタルポスト上面に半田バンプを形成する工程、(E) forming a solder bump on the exposed metal post upper surface;
（ｆ）前記半導体ウエハを切断することにより、複数の半導体チップを形成する工程、(F) cutting the semiconductor wafer to form a plurality of semiconductor chips;
を含むことを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device, comprising:
JP32515999A 1999-11-16 1999-11-16 Method for manufacturing semiconductor device and semiconductor device Pending JP2001144213A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32515999A JP2001144213A (en) 1999-11-16 1999-11-16 Method for manufacturing semiconductor device and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32515999A JP2001144213A (en) 1999-11-16 1999-11-16 Method for manufacturing semiconductor device and semiconductor device

Publications (2)

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JP2001144213A JP2001144213A (en) 2001-05-25
JP2001144213A5 true JP2001144213A5 (en) 2005-06-30

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JP32515999A Pending JP2001144213A (en) 1999-11-16 1999-11-16 Method for manufacturing semiconductor device and semiconductor device

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KR20020091327A (en) * 2001-05-31 2002-12-06 삼성전자 주식회사 Wafer level package having a package body at its side surface and method for manufacturing the same
JP4529319B2 (en) * 2001-06-27 2010-08-25 日亜化学工業株式会社 Semiconductor chip and manufacturing method thereof
JP2003309228A (en) 2002-04-18 2003-10-31 Oki Electric Ind Co Ltd Semiconductor device and manufacturing method therefor
US7285867B2 (en) 2002-11-08 2007-10-23 Casio Computer Co., Ltd. Wiring structure on semiconductor substrate and method of fabricating the same
JP2005175327A (en) * 2003-12-15 2005-06-30 Matsushita Electric Ind Co Ltd Semiconductor device, and manufacturing method thereof
JP2006019636A (en) * 2004-07-05 2006-01-19 Renesas Technology Corp Semiconductor apparatus
JP2006032598A (en) * 2004-07-15 2006-02-02 Renesas Technology Corp Semiconductor device and method for manufacturing the same
JP4982948B2 (en) * 2004-08-19 2012-07-25 富士電機株式会社 Manufacturing method of semiconductor device
WO2006059589A1 (en) * 2004-11-30 2006-06-08 Kyushu Institute Of Technology Packaged stacked semiconductor device and method for manufacturing same
US7582556B2 (en) 2005-06-24 2009-09-01 Megica Corporation Circuitry component and method for forming the same
JP4904769B2 (en) * 2005-10-21 2012-03-28 富士通セミコンダクター株式会社 Semiconductor device
JP2007234881A (en) * 2006-03-01 2007-09-13 Oki Electric Ind Co Ltd Semiconductor device laminating semiconductor chips, and its manufacturing method
US8749065B2 (en) 2007-01-25 2014-06-10 Tera Probe, Inc. Semiconductor device comprising electromigration prevention film and manufacturing method thereof
JP2008244383A (en) * 2007-03-29 2008-10-09 Casio Comput Co Ltd Semiconductor device and its manufacturing method
JP5496445B2 (en) * 2007-06-08 2014-05-21 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
JP2009176978A (en) * 2008-01-25 2009-08-06 Rohm Co Ltd Semiconductor device
JP2010062176A (en) * 2008-09-01 2010-03-18 Casio Comput Co Ltd Semiconductor device and manufacturing method thereof
US10141202B2 (en) * 2013-05-20 2018-11-27 Qualcomm Incorporated Semiconductor device comprising mold for top side and sidewall protection
SG11201709671YA (en) * 2015-05-25 2017-12-28 Lintec Corp Semiconductor device manufacturing method

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