KR100320447B1 - Method for Manufacturing Semiconductor Package - Google Patents
Method for Manufacturing Semiconductor Package Download PDFInfo
- Publication number
- KR100320447B1 KR100320447B1 KR1019990016093A KR19990016093A KR100320447B1 KR 100320447 B1 KR100320447 B1 KR 100320447B1 KR 1019990016093 A KR1019990016093 A KR 1019990016093A KR 19990016093 A KR19990016093 A KR 19990016093A KR 100320447 B1 KR100320447 B1 KR 100320447B1
- Authority
- KR
- South Korea
- Prior art keywords
- multilayer wiring
- forming
- via hole
- semiconductor chip
- wiring substrate
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000000034 method Methods 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 229920006336 epoxy molding compound Polymers 0.000 claims abstract description 9
- 230000017525 heat dissipation Effects 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 238000000465 moulding Methods 0.000 claims abstract description 7
- 238000007747 plating Methods 0.000 claims abstract description 6
- 238000004140 cleaning Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000009966 trimming Methods 0.000 description 2
- 229940126639 Compound 33 Drugs 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- PNUZDKCDAWUEGK-CYZMBNFOSA-N Sitafloxacin Chemical compound C([C@H]1N)N(C=2C(=C3C(C(C(C(O)=O)=CN3[C@H]3[C@H](C3)F)=O)=CC=2F)Cl)CC11CC1 PNUZDKCDAWUEGK-CYZMBNFOSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
본 발명은 열방출이 용이한 반도체 패키지의 제조방법에 관한 것으로서, 다층배선 기판에 복수개의 비아홀 랜드를 형성하는 단계와, 상기 각 비아홀 랜드의 중심에 비아홀을 형성하는 단계와, 상기 비아홀에 다층배선 기판의 상면과 하면을 전기적으로 연결하기 위해 도금을 실시하는 단계와, 상기 도금된 비아 홀의 반쪽면을 제거하여 상기 다층배선 기판에 반도체 칩이 부착되는 구멍을 형성하는 단계와, 상기 구멍 양측의 다층배선 기판상에 본드 핑거를 형성하는 단계와, 상기 본드 핑거가 형성된 다층배선 기판의 하측면에 열 방출 테이프를 부착하는 단계와, 상기 다층배선 기판의 구멍에 반도체 칩을 부착하고 다이 본딩 및 와이어 본딩을 실시하여 본드 핑거와 반도체 칩을 전기적으로 연결하는 금속 와이어를 형성하는 단계와, 상기 반도체 칩의 백사이드가 노출되도록 에폭시 몰딩 컴파운드를 이용하여 몰딩하는 단계를 포함하여 형성함을 특징으로 한다.The present invention relates to a method for manufacturing a heat dissipating semiconductor package, the method comprising: forming a plurality of via hole lands in a multilayer wiring substrate, forming a via hole in the center of each via hole land, and multi-layer wiring in the via holes. Plating to electrically connect the upper and lower surfaces of the substrate, removing the half surface of the plated via hole to form holes for attaching semiconductor chips to the multilayer wiring substrate, and forming multilayers on both sides of the holes. Forming a bond finger on a wiring board, attaching a heat dissipation tape to a lower side of the multilayer wiring board on which the bond finger is formed, attaching a semiconductor chip to the hole of the multilayer wiring board, and die bonding and wire bonding Forming a metal wire electrically connecting the bond finger and the semiconductor chip to each other; Molding using an epoxy molding compound to expose the backside.
Description
본 발명은 반도체 패키지(Package)에 관한 것으로, 특히 열방출이 용이한 반도체 패키지의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly to a method for manufacturing a semiconductor package that is easy to dissipate heat.
일반적으로 반도체 패키지 제조시에는 웨이퍼에 집적회로를 형성하는 FAB공정(Fabrication Process)을 완료한 후, 상기 웨이퍼상에 만들어진 각 칩을 서로 분리시키는 다이싱(Dicing), 상기 분리된 각 칩을 리드 프레임(Lead Frame)의 패들(Paddle)에 안착시키는 칩 본딩(Chip Bonding), 칩 위의 본딩 패드(Bonding Pad)와 리드 프레임의 인너 리드(Inner Lead)를 전기적으로 접속시키는 와이어 본딩(Wire Bonding)을 순차적으로 수행한 후, 회로를 보호하기 위해 몰딩(Molding)을 수행하게 된다.In general, in manufacturing a semiconductor package, after completing a FAB process (fabrication process) for forming an integrated circuit on a wafer, dicing each chip formed on the wafer from each other, and dividing each chip into a lead frame Chip Bonding to be placed on Paddle of (Lead Frame), Wire Bonding to electrically connect Bond Pad on Chip and Inner Lead of Lead Frame After sequentially performing, molding is performed to protect the circuit.
또한, 몰딩을 수행한 후에는 리드 프레임의 써버트 바(Support Bar) 및 댐바(Dam Bar)를 자르는 트리밍(Trimming) 및 아웃 리드(Out Lead)를 소정의 형상으로 성형하는 포밍(Forming)을 차례로 수행하게 되며, 트리밍 및 포밍 완료 후에는 최종적으로 솔더링(Soldering)을 실시함으로써 패키지 공정을 완료하게 된다.In addition, after molding, trimming to cut the support bar and the dam bar of the lead frame and forming the out lead to a predetermined shape are sequentially performed. After trimming and forming, the package process is completed by soldering.
이하, 첨부된 도면을 참고하여 종래의 반도체 패키지의 제조방법을 설명하면 다음과 같다.Hereinafter, a manufacturing method of a conventional semiconductor package will be described with reference to the accompanying drawings.
도 1은 종래의 반도체 패키지의 제조방법을 나타낸 공정단면도이다.1 is a process cross-sectional view showing a conventional method for manufacturing a semiconductor package.
도 1에서와 같이, 다층 배선기판(PCB ; Printed Circuit Board)(11)위에 다이 본딩 에폭시(Die Bonding Epoxy)(12)를 이용하여 반도체 칩(13)을 부착 고정한 후 반도체 칩(13)의 본드패드(14)와 다층 배선기판(11)의 인너 리드를 금속 와이어(15)를 이용하여 전기적으로 연결한다.As shown in FIG. 1, the semiconductor chip 13 is attached and fixed by using a die bonding epoxy 12 on a printed circuit board (PCB) 11 and then bonded to the semiconductor chip 13. The inner lead of the pad 14 and the multilayer wiring board 11 are electrically connected using the metal wire 15.
이어, 상기 반도체 칩(13)을 포함한 일정영역을 에폭시 몰딩 컴파운드(EMC ; Epoxy Molding Compound)(16)를 이용하여 몰딩을 행하고, 상기 다층 배선기판(11)의 다른쪽(칩이 부착된 반대쪽)에 솔더볼(Solder Ball)(17)을 이용하여 전기적 신호를 외부로 전달되도록 부착 고정하여 제작한 에리어 어레이형 볼 그리드 에레이(Ball Grid Array) 패키지를 형성한다.Subsequently, a certain region including the semiconductor chip 13 is molded using an epoxy molding compound (EMC) 16, and the other side of the multilayer wiring board 11 (the opposite side to which the chip is attached). A solder ball 17 is used to form an area array ball grid array package manufactured by attaching and fixing electrical signals so as to be transmitted to the outside.
그러나 상기와 같은 종래의 반도체 패키지의 제조방법은 다음과 같은 문제점이 있었다.However, the conventional method of manufacturing a semiconductor package as described above has the following problems.
즉, 종래의 볼 그리드 어레이 패키지(Ball Grid Array Package)는 고온 퍼포먼스(High Thermal Performance)가 요구되는 소자에 신뢰성이 떨어지며 열방출이 높은 패키지에 적용이 어렵다.That is, the conventional ball grid array package is difficult to apply to a package having high heat dissipation and low reliability in a device requiring high thermal performance.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 디바이스의 열방출, 경박단소, 본딩패드 배치용의 전기적 향상 및 솔더 조인트(Solder Joint) 향상에 적당하도록 한 반도체 패키지의 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a method of manufacturing a semiconductor package suitable for heat dissipation, light and small thickness of the device, electrical improvement for bonding pad placement, and solder joint improvement. There is a purpose.
도 1은 종래의 반도체 패키지의 제조방법을 나타낸 공정단면도1 is a process cross-sectional view showing a conventional method for manufacturing a semiconductor package.
도 2a 내지 도 2c는 본 발명에서 사용되는 다층배선 기판의 형성방법을 나타낸 공정단면도2A to 2C are cross-sectional views illustrating a method of forming a multilayer wiring substrate used in the present invention.
도 3a와 도 3b는 본 발명에 사용되는 다층배선 기판의 상면과 하면을 나타낸 평면도3A and 3B are plan views showing top and bottom surfaces of a multilayer wiring board used in the present invention.
도 4는 본 발명에 의한 반도체 패키지를 나타낸 구조단면도Figure 4 is a structural cross-sectional view showing a semiconductor package according to the present invention
도 5a 내지 도 5c는 본 발명에 의한 반도체 패키지의 제조방법을 나타낸 공정단면도5A through 5C are cross-sectional views illustrating a method of manufacturing a semiconductor package according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
21 : 다층배선 기판 22 : 절연막21: multilayer wiring substrate 22: insulating film
23 : 비아홀 랜드 24 : 비아홀23: Via Hole Land 24: Via Hole
25 : 구멍 26 : 도금25: hole 26: plating
27 : 밴드 핑거 28 : 아웃 리드27: Band Finger 28: Out Lead
29 : 신호선 30 : 열 방출 테이프29: signal line 30: heat release tape
31 : 반도체 칩 32 : 금속 와이어31: semiconductor chip 32: metal wire
33 : 에폭시 몰딩 컴파운드33: epoxy molding compound
상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 패키지의 제조방법은 다층배선 기판에 복수개의 비아홀 랜드를 형성하는 단계와, 상기 각 비아홀 랜드의 중심에 비아홀을 형성하는 단계와, 상기 비아홀에 다층배선 기판의 상면과 하면을 전기적으로 연결하기 위해 도금을 실시하는 단계와, 상기 도금된 비아 홀의 반쪽면을 제거하여 상기 다층배선 기판에 반도체 칩이 부착되는 구멍을 형성하는 단계와, 상기 구멍 양측의 다층배선 기판상에 본드 핑거를 형성하는 단계와, 상기 본드 핑거가 형성된 다층배선 기판의 하측면에 열 방출 테이프를 부착하는 단계와, 상기 다층배선 기판의 구멍에 반도체 칩을 부착하고 다이 본딩 및 와이어 본딩을 실시하여 본드 핑거와 반도체 칩을 전기적으로 연결하는 금속 와이어를 형성하는 단계와, 상기 반도체 칩의 백사이드가 노출되도록 에폭시 몰딩 컴파운드를 이용하여 몰딩하는 단계를 포함하여 형성함을 특징으로 한다.The method of manufacturing a semiconductor package according to the present invention for achieving the above object comprises the steps of forming a plurality of via hole lands in a multilayer wiring substrate, forming a via hole in the center of each via hole land, and multi-layer in the via hole. Performing plating to electrically connect the upper and lower surfaces of the wiring board, removing the half surface of the plated via hole, and forming a hole to which the semiconductor chip is attached to the multilayer wiring board; Forming a bond finger on the multilayer wiring substrate, attaching a heat dissipation tape to a lower side of the multilayer wiring substrate on which the bond fingers are formed, attaching a semiconductor chip to the holes of the multilayer wiring substrate, and die bonding and wire Bonding to form a metal wire electrically connecting the bond finger and the semiconductor chip, and the peninsula Characterized in that the formation, including the step of molding using an epoxy molding compound so that the backside of the chip are exposed.
이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 패키지의 제조방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor package according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명에서 사용되는 다층배선 기판의 형성방법을 나타낸 공정단면도이다.2A to 2C are cross-sectional views illustrating a method of forming a multilayer wiring substrate used in the present invention.
도 2a에 도시한 바와 같이, 다층배선 기판(21)의 전면에 절연막(22)을 형성하고, 상기 절연막(22)을 선택적으로 제거하여 상기 다층배선 기판(21)에 복수개의 비아홀 랜드(Via Hole Land)(23)를 형성한다.As illustrated in FIG. 2A, an insulating film 22 is formed on the entire surface of the multilayer wiring board 21, and the insulating film 22 is selectively removed to remove a plurality of via holes in the multilayer wiring board 21. Land 23 is formed.
도 2b에 도시한 바와 같이, 상기 각 비아홀 랜드(23)의 중심에 비아홀(24)을 형성한 후, 상기 비아홀(24)에 도금을 실시하여 다층배선 기판(21)의 상면(上面)과 하면(下面)을 전기적으로 연결한다.As shown in FIG. 2B, after the via hole 24 is formed in the center of each of the via hole lands 23, the via hole 24 is plated to form a top surface and a bottom surface of the multilayer wiring substrate 21. Connect the lower part electrically.
여기서 상기 비아홀(24)의 도금에 사용되는 재료는 전기 전도율이 좋은 금이나 구리 등을 사용한다.Here, the material used for plating the via hole 24 uses gold or copper having good electrical conductivity.
도 2c에 도시한 바와 같이, 상기 다층배선 기판(21)에 라우팅(Routing) 공정을 실시하여 도금된 비아홀(24)의 반쪽면을 제거함으로써 상기 다층배선 기판(21)에 반도체 칩이 부착될 구멍(Cavity)(25)을 형성한다.As shown in FIG. 2C, a hole in which the semiconductor chip is attached to the multilayer wiring board 21 by removing a half surface of the plated via hole 24 by performing a routing process on the multilayer wiring board 21. (Cavity) 25 is formed.
도 3a와 도 3b는 본 발명에 사용되는 다층배선 기판의 상면과 하면을 나타낸 평면도이다.3A and 3B are plan views showing top and bottom surfaces of the multilayer wiring board used in the present invention.
도 3a 및 도 3b에서와 같이, 각각의 랜드 중심에 비아홀(24)이 형성되어 있고, 상기 비아홀(24)내에는 상기 다층배선 기판(21)의 상면과 하면을 전기적으로 연결하기 위하여 금이나 구리 등을 사용하여 도금(26)되어 있고, 상기 도금된 비아홀(24)의 반쪽면이 제거되어 다층배선 기판(21)에 구멍(25)이 형성되어 있다.3A and 3B, via holes 24 are formed in each land center, and in the via holes 24, gold or copper are used to electrically connect the upper and lower surfaces of the multilayer wiring board 21. Plating 26 is used, and the other half surface of the plated via hole 24 is removed to form a hole 25 in the multilayer wiring substrate 21.
도 4는 본 발명에 의한 반도체 패키지를 나타낸 구조단면도이다.4 is a structural cross-sectional view showing a semiconductor package according to the present invention.
도 4에 도시한 바와 같이, 다층배선 기판(21)에 반도체 칩(31)이 부착되는 영역에 구멍(25)이 형성되어 있고, 상기 구멍(25) 양측의 다층배선 기판(21)상에 본드 핑거(27)가 형성되어 있으며, 상기 본드 핑거(27)와 반도체 칩(31)을 전기적으로 연결하는 금속 와이어(32)가 형성되어 있고, 상기 본드 핑거(27)와 신호선(도면에는 도시되지 않음)을 통해 연결되는 아웃 리드(28)가 다층배선 기판(21)의 에지부분에 형성되어 있으며, 상기 반도체 칩(31)의 백사이드가 노출되도록 몰딩하는 에폭시 몰딩 컴파운드(33)를 포함하여 구성된다.As shown in FIG. 4, a hole 25 is formed in a region where the semiconductor chip 31 is attached to the multilayer wiring board 21, and is bonded on the multilayer wiring board 21 on both sides of the hole 25. A finger 27 is formed, and a metal wire 32 is formed to electrically connect the bond finger 27 and the semiconductor chip 31, and the bond finger 27 and a signal line (not shown). An out lead 28 connected to the through lead is formed at an edge of the multilayer wiring board 21, and includes an epoxy molding compound 33 molded to expose the backside of the semiconductor chip 31.
도 5a 내지 도 5d는 본 발명에 의한 반도체 패키지의 제조방법을 나타낸 공정단면도이다.5A to 5D are cross-sectional views illustrating a method of manufacturing a semiconductor package according to the present invention.
도 5a에 도시한 바와 같이, 반도체 칩(도면에는 도시되지 않음)이 부착되는 부분에 구멍(25)이 형성된 다층배선 기판(21)상의 일정영역에 본드 핑거(Bond Finger)(27)를 형성한다.As shown in FIG. 5A, bond fingers 27 are formed in a predetermined region on the multilayer wiring substrate 21 in which holes 25 are formed in portions where semiconductor chips (not shown) are attached. .
이어, 상기 다층배선 기판(21)의 에지부분에 아웃 리드(Out Lead)(28)를 형성하고, 상기 본드 핑거(27)와 아웃 리드(28)를 연결하는 신호선(Signal Line)(29)을 형성한다.Subsequently, an out lead 28 is formed at an edge of the multilayer wiring board 21, and a signal line 29 connecting the bond finger 27 and the out lead 28 is formed. Form.
도 5b에 도시한 바와 같이, 상기 본드 핑거(27)가 형성된 다층배선 기판(21)의 하측면에 열 방출 테이프(Thermal Release Tape)(30)를 부착한다.As shown in FIG. 5B, a thermal release tape 30 is attached to a lower side of the multilayer wiring board 21 on which the bond fingers 27 are formed.
이어, 상기 다층배선 기판(21)의 구멍(24)에 반도체 칩(31)을 부착 고정하고, 상기 반도체 칩(31)과 다층배선 기판(21)을 전기적으로 연결하기 위해 다이 본딩(Die Bonding) 및 와이어 본딩(Wire Bonding)을 실시하여 본드 핑거(27)과 반도체 칩(31)을 연결하는 금속 와이어(32)를 형성한다.Subsequently, die bonding is performed to attach and fix the semiconductor chip 31 to the hole 24 of the multilayer wiring board 21 and to electrically connect the semiconductor chip 31 and the multilayer wiring board 21 to each other. And wire bonding to form a metal wire 32 connecting the bond finger 27 and the semiconductor chip 31 to each other.
도 5c에 도시한 바와 같이, 상기 반도체 칩(31)의 백사이드(Backside)가 노출되도록 에폭시 몰딩 컴파운드(EMC : Epoxy Molding Compound)(33)를 이용하여 몰딩을 실시한다.As shown in FIG. 5C, molding is performed using an epoxy molding compound (EMC) 33 so that the backside of the semiconductor chip 31 is exposed.
도 5d에 도시한 바와 같이, 상기 열 방출 테이프(30)를 제거한 후, 클리닝(Cleaning) 공정을 실시하여 반도체 칩(31)과 다층배선 기판(21)의 이물질을 제거한다.As shown in FIG. 5D, after the heat release tape 30 is removed, a cleaning process is performed to remove foreign substances from the semiconductor chip 31 and the multilayer wiring substrate 21.
이상에서 설명한 바와 같이 본 발명에 의한 반도체 패키지의 제조방법에 있어서 다음과 같은 효과가 있다.As described above, the method of manufacturing a semiconductor package according to the present invention has the following effects.
첫째, 하이 핀(High Pin) 반도체 패키지를 구현하면서 동시에 열방출 효과(즉, 반도체 칩의 백사이드 노광 효과)를 극대화시킬 수 있다.First, it is possible to maximize the heat dissipation effect (ie, the backside exposure effect of the semiconductor chip) while implementing a high pin semiconductor package.
둘째, 비아홀 랜드와 도금된 비아홀 내벽이 외부단자로 함께 이용되므로 솔더 필렛(Solder Filet)의 형성이 용이하고 솔더 조인(Solder Join)의 신뢰성을 향상시킬 수 있다.Second, since the via hole land and the plated via hole inner wall are used together as an external terminal, it is easy to form a solder fillet and improve the reliability of solder join.
셋째, 다층배선 기판에 구멍을 형성한 후 구멍에 반도체 칩을 부착 고정시킴으로써 열방출 효과를 극대화시킨 반도체 패키지를 형성할 수 있다.Third, by forming a hole in the multi-layered wiring substrate and attaching and fixing a semiconductor chip in the hole, it is possible to form a semiconductor package that maximizes the heat dissipation effect.
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| KR101130166B1 (en) * | 2010-03-05 | 2012-03-28 | 김용진 | Apparatus and method for replacing bearings of box girder bridge |
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| KR970004322Y1 (en) * | 1994-10-31 | 1997-05-08 | 대우자동차 주식회사 | Remote controlled rear visor for a vehicle |
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