JP2000133819A - Silicon carbide schottky barrier diode and manufacture thereof - Google Patents
Silicon carbide schottky barrier diode and manufacture thereofInfo
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- JP2000133819A JP2000133819A JP30494598A JP30494598A JP2000133819A JP 2000133819 A JP2000133819 A JP 2000133819A JP 30494598 A JP30494598 A JP 30494598A JP 30494598 A JP30494598 A JP 30494598A JP 2000133819 A JP2000133819 A JP 2000133819A
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- silicon carbide
- intermediate layer
- carrier concentration
- barrier diode
- layer
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、炭化けい素（以下
ＳｉＣと記す）を用いたショットキーバリアダイオード
に関する。[0001] 1. Field of the Invention [0002] The present invention relates to a Schottky barrier diode using silicon carbide (hereinafter referred to as SiC).
【０００２】[0002]
【従来技術】高周波、大電力の制御を目的として、けい
素（以下Ｓｉと記す）を用いた電力用半導体素子（以下
パワーデバイスと称する）では、各種の工夫により高性
能化が進められている。しかし、パワーデバイスは高温
や放射線等の存在下で使用されることもあり、そのよう
な条件下ではＳｉデバイスは使用できないことがある。
また、Ｓｉのパワーデバイスより更に高性能のパワーデ
バイスを求める声に対して、新しい材料の適用が検討さ
れている。2. Description of the Related Art For the purpose of controlling high frequency and high power, a power semiconductor device (hereinafter, referred to as a power device) using silicon (hereinafter, referred to as Si) has been improved in performance by various means. . However, the power device may be used in the presence of high temperature or radiation, and the Si device may not be used under such conditions.
Further, in response to a demand for a power device having higher performance than a Si power device, application of a new material is being studied.
【０００３】ＳｉＣは広い禁制帯幅（４Ｈ型で３．２６
ｅＶ、６Ｈ型で３．０２ｅＶ）をもつため、高温での電
気伝導度の制御性や耐放射線性に優れ、またＳｉより約
１桁高い絶縁破壊電圧をもつため、高耐圧素子への適用
が可能である。さらに、ＳｉＣはＳｉの約２倍の電子飽
和ドリフト速度をもつので、高周波大電力制御にも適す
る。このようなＳｉＣの物性を活かしたデバイスのひと
つにショットキーバリアダイオードがある。[0003] SiC has a wide bandgap (3.26 for 4H type).
(eV, 3.02 eV for 6H type), it is excellent in controllability of electric conductivity at high temperature and radiation resistance, and it has dielectric breakdown voltage about one digit higher than that of Si, so it can be applied to high breakdown voltage elements. It is possible. Further, since SiC has an electron saturation drift speed about twice as high as that of Si, it is also suitable for high-frequency high-power control. One of the devices utilizing such physical properties of SiC is a Schottky barrier diode.
【０００４】[0004]
【発明が解決しようとする課題】逆方向もれ電流は、シ
ョットキーバリアダイオードの重要な特性であり、その
低減は、高電圧への適用や、損失低減のための重大な課
題であった。従来もれ電流を低減するためには、ショッ
トキー電極周辺に酸化膜や、イオン注入によるガードリ
ングを形成する方法が提案されている［例えば、A.Ito
h, IEEE, ElectronDevice Lett., 17(3) p.139 (1996)
参照］。この方法は電極周辺からのもれ電流低減を意図
したものである。本発明の目的は、逆方向もれ電流を低
減したＳｉＣショットキーダイオードを提供することに
ある。The reverse leakage current is an important characteristic of the Schottky barrier diode, and its reduction has been a serious problem for application to a high voltage and reduction of loss. In order to reduce the leakage current, a method of forming an oxide film around the Schottky electrode or a guard ring by ion implantation has been proposed [for example, A. Ito
h, IEEE, ElectronDevice Lett., 17 (3) p.139 (1996)
reference]. This method is intended to reduce leakage current from the periphery of the electrode. An object of the present invention is to provide a SiC Schottky diode in which the reverse leakage current is reduced.
【０００５】[0005]
【課題を解決するための手段】上記の課題解決のため本
発明は、炭化けい素ショットキーバリアダイオードにお
いて、高キャリア濃度の炭化けい素基板上に、炭化けい
素からなる低キャリア濃度の高抵抗層と、その高抵抗層
上に同じ導電型で更に低キャリア濃度の薄い中間層とを
有し、炭化けい素基板にオーミック電極を、中間層表面
にショットキー電極をそれぞれ設けるもとのする。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention relates to a silicon carbide Schottky barrier diode, in which a silicon carbide substrate having a high carrier concentration is provided on a silicon carbide substrate having a high resistance having a low carrier concentration. A layer and an intermediate layer having the same conductivity type and a lower carrier concentration are further provided on the high resistance layer. An ohmic electrode is provided on the silicon carbide substrate, and a Schottky electrode is provided on the surface of the intermediate layer.
【０００６】そのようにすれば、後記実施例のようにオ
ン抵抗の増分を小さく抑えたまま、逆方向バイアス時の
漏れ電流を大幅に低減できる。特に、中間層の厚さが１
０ｎｍ〜１μｍの範囲にあるものとする。In this case, the leakage current at the time of reverse bias can be greatly reduced while the increment of the on-resistance is kept small as in the embodiment described later. In particular, when the thickness of the intermediate layer is 1
It is assumed to be in the range of 0 nm to 1 μm.
【０００７】中間層の厚さが１μｍより厚くなると、特
にキャリア濃度が低い場合にオン抵抗の増分が大きくな
る。逆に中間層の厚さが１０ｎｍより薄くなると、高抵
抗層の影響が現れて漏れ電流低減作用が十分に得られな
い。When the thickness of the intermediate layer is larger than 1 μm, the increase of the on-resistance becomes large especially when the carrier concentration is low. Conversely, if the thickness of the intermediate layer is less than 10 nm, the effect of the high-resistance layer appears, and the effect of reducing the leakage current cannot be sufficiently obtained.
【０００８】更に、中間層のキャリア濃度が１×１０15
〜１×１０16ｃｍ-3の範囲にあるものとする。キャリア
濃度が１×１０15ｃｍ-3より低いと、オン抵抗の増分が
大きくなり、１×１０16ｃｍ-3より高いと、漏れ電流の
低減効果が小さい。Further, the carrier concentration of the intermediate layer is 1 × 10 15
１1 × 10 16 cm −3 . When the carrier concentration is lower than 1 × 10 15 cm −3 , the increase of the on-resistance is increased. When the carrier concentration is higher than 1 × 10 16 cm −3 , the effect of reducing the leakage current is small.
【０００９】製造方法としては、高キャリア濃度の炭化
けい素基板上に、炭化けい素からなる低キャリア濃度の
高抵抗層と、その高抵抗層上に同じ導電型で更に低キャ
リア濃度の薄い中間層とをエピタキシャル成長により形
成し、炭化けい素基板にオーミック電極を、中間層表面
にショットキー電極をそれぞれ設けても、高キャリア濃
度の炭化けい素基板上に、炭化けい素からなる低キャリ
ア濃度の高抵抗層をエピタキシャル成長により形成し、
その高抵抗層の表面層に逆導電型の不純物をイオン注入
して同じ導電型で更に低キャリア濃度の薄い中間層を形
成し、炭化けい素基板にオーミック電極を、中間層表面
にショットキー電極をそれぞれ設けても上記のような炭
化けい素ショットキーバリアダイオードを製造できる。As a manufacturing method, a high-resistance layer made of silicon carbide having a low carrier concentration is formed on a silicon carbide substrate having a high carrier concentration, and an intermediate layer having the same conductivity type and a further lower carrier concentration is formed on the high-resistance layer. Even if an ohmic electrode is formed on the silicon carbide substrate and a Schottky electrode is provided on the surface of the intermediate layer, a low carrier concentration of silicon carbide is formed on the silicon carbide substrate having a high carrier concentration. Forming a high resistance layer by epitaxial growth,
An impurity of the opposite conductivity type is ion-implanted into the surface layer of the high resistance layer to form a thinner intermediate layer of the same conductivity type and a lower carrier concentration, and an ohmic electrode is formed on the silicon carbide substrate, and a Schottky electrode is formed on the surface of the intermediate layer. Are provided, the silicon carbide Schottky barrier diode as described above can be manufactured.
【００１０】[0010]
【発明の実施の形態】以下図面を参照しながら本発明の
実施例を説明する。なお以下において、ｎを冠記した層
は、電子を多数キャリアとする層を意味し、- は比較的
低濃度を、- - は一層不純物濃度が低いことを意味して
いる。 ［実施例１］図１は、本発明にかかるＳｉＣショットキ
ーダイオードの断面図である。図において、４は高不純
物濃度のＳｉＣ基板、３は低不純物濃度のｎ- 高抵抗
層、２は更に低不純物濃度のｎ- - 中間層、５はニッケ
ルのオーミック電極、１は金のショットキー電極であ
る。各層のディメンションは例えば、ＳｉＣ基板４の不
純物濃度は５×１０18ｃｍ-3、厚さ３００μｍ、ｎ- 高
抵抗層３の不純物濃度は４×１０16ｃｍ-3、厚さ５μ
ｍ、ｎ- - 中間層２の不純物濃度は５×１０15ｃｍ-3、
厚さ１００ｎｍである。オーミック電極５の厚さは２０
０ｎｍ、ショットキー電極１の厚さは２００ｎｍとし
た。Embodiments of the present invention will be described below with reference to the drawings. In the following, the layer prefixed to n, means the layer in which electrons are majority carriers, - the relatively low concentrations, - - the means that even low impurity concentration. Embodiment 1 FIG. 1 is a sectional view of a SiC Schottky diode according to the present invention. In the figure, 4 is a SiC substrate having a high impurity concentration, 3 is an n - high resistance layer having a low impurity concentration, 2 is an n -- intermediate layer having a further low impurity concentration, 5 is an ohmic electrode of nickel, and 1 is a Schottky of gold. Electrodes. The dimensions of each layer are, for example, the impurity concentration of the SiC substrate 4 is 5 × 10 18 cm −3 , the thickness is 300 μm, the impurity concentration of the n − high resistance layer 3 is 4 × 10 16 cm −3 , and the thickness is 5 μm.
The impurity concentration of the m, n − -intermediate layer 2 is 5 × 10 15 cm −3 ,
The thickness is 100 nm. The thickness of the ohmic electrode 5 is 20
0 nm, and the thickness of the Schottky electrode 1 was 200 nm.
【００１１】以下このダイオードの作製方法を述べる。
ＳｉＣ基板４には鏡面研磨された４Ｈ型ＳｉＣ単結晶を
用いた。ＳｉＣウェハからダイサーにより５ｍｍ□のチ
ップに切り分け、ＳｉＣ基板４とした。本実施例では、
（０００１）Ｓｉ面から〈１１、−２、０〉方向に８度
傾けて研磨した面を使用した。Hereinafter, a method for manufacturing this diode will be described.
For the SiC substrate 4, a mirror-polished 4H-type SiC single crystal was used. The SiC wafer was cut into 5 mm square chips by a dicer to obtain a SiC substrate 4. In this embodiment,
A surface polished at an angle of 8 degrees from the (0001) Si surface in the <11, -2, 0> direction was used.
【００１２】低抵抗のＳｉＣ基板４を有機溶剤と酸によ
る洗浄で清浄にする。次にエッチングするＳｉ面を上に
して、ＳｉＣ基板４をＳｉＣで被覆した黒鉛のサセプタ
にのせ、そのサセプタを石英反応管内に挿入し、１Ｐａ
より低圧の真空にひく。The low-resistance SiC substrate 4 is cleaned by washing with an organic solvent and an acid. Next, the SiC substrate 4 is placed on a graphite susceptor coated with SiC with the Si surface to be etched facing up, and the susceptor is inserted into a quartz reaction tube, and 1 Pa
Apply to a lower pressure vacuum.
【００１３】次に水素（以下Ｈ2 と記す）と塩酸ガス
（以下ＨＣｌと記す）とをそれぞれ毎分１Ｌ、１０ｍＬ
の流量で混ぜた混合ガスを流しながら１３５０℃で５分
間加熱して、気相エッチングをおこなう。サセプタの加
熱法は高周波誘導加熱である。Next, hydrogen (hereinafter, referred to as H 2 ) and hydrochloric acid gas (hereinafter, referred to as HCl) are added at 1 L / min and 10 mL / min, respectively.
The mixture is heated at 1350 ° C. for 5 minutes while flowing a mixed gas mixed at a flow rate of 1 to perform gas phase etching. The method of heating the susceptor is high-frequency induction heating.
【００１４】続いて化学気相成長（ＣＶＤ）法でｎ- 高
抵抗層３をエピタキシャル成長する。Ｈ2 、モノシラン
ガス（以下ＳｉＨ4 と記す）、プロパンガス（以下Ｃ3
Ｈ8と記す）をそれぞれ毎分３Ｌ、０．３ｍＬ、０．２
５ｍＬの流量比率で混合し、微量のＮ2 を添加したガス
を反応管内に流しながら、１５００℃で２時間加熱する
と、基板４上に厚さ約５μｍの４Ｈ型のｎ- 高抵抗層３
が成長する。ｎ- 高抵抗層３のキャリア密度は４×１０
16ｃｍ-3であった。Subsequently, an n - high resistance layer 3 is epitaxially grown by a chemical vapor deposition (CVD) method. H 2 , monosilane gas (hereinafter referred to as SiH 4 ), propane gas (hereinafter referred to as C 3
Each H 8 and denoted), respectively partial 3L, 0.3 mL, 0.2
When mixed at a flow rate of 5 mL and heated at 1500 ° C. for 2 hours while flowing a gas containing a small amount of N 2 into the reaction tube, a 4H-type n − high resistance layer 3 having a thickness of about 5 μm is formed on the substrate 4.
Grows. The carrier density of n − high resistance layer 3 is 4 × 10
It was 16 cm -3 .
【００１５】次にｎ- - 中間層２を形成する。形成方法
は上記ＣＶＤ法による。Ｈ2 、ＳｉＨ4 、Ｃ3 Ｈ8 の混
合流量比率を毎分３Ｌ、０．１５ｍＬ、０．１２ｍＬの
ガスを反応管内に流しながら、成長時間を５分とする。
このとき成長した薄膜の厚さは約１００ｎｍ、キャリア
密度は１×１０15ｃｍ-3であった。Next, an n -- intermediate layer 2 is formed. The formation method is based on the above CVD method. The mixing time of H 2 , SiH 4 , and C 3 H 8 is 3 L, 0.15 mL, and 0.12 mL of gas per minute, and the growth time is set to 5 minutes while flowing into the reaction tube.
At this time, the thickness of the grown thin film was about 100 nm, and the carrier density was 1 × 10 15 cm −3 .
【００１６】ｎ- 高抵抗層３、ｎ- - 中間層２を成長し
た後、ＳｉＣ基板４の裏面すなわち炭素（Ｃ）面にニッ
ケルを２００ｎｍの厚さに真空蒸着し、アルゴン雰囲気
中において１０５０℃、１０分加熱しオーミック電極５
とする。After the n − high resistance layer 3 and the n − − intermediate layer 2 are grown, nickel is vacuum-deposited to a thickness of 200 nm on the back surface of the SiC substrate 4, that is, the carbon (C) surface, and 1050 ° C. in an argon atmosphere. Heat for 10 minutes, ohmic electrode 5
And
【００１７】それからｎ- - 中間層２の表面に厚さが２
００ｎｍ、直径が２００μｍとなるように金（Ａｕ）を
蒸着してショットキー電極１とし、ショットキーダイオ
ードを作製する。[0017] Then n - - thickness on the surface of the intermediate layer 2 is 2
Gold (Au) is vapor-deposited so as to have a thickness of 00 nm and a diameter of 200 μm to form a Schottky electrode 1 to produce a Schottky diode.
【００１８】同様にして、ｎ- - 中間層２の成長時間を
３〜６０分間として厚さを変え、また、その際に微量の
Ｎ2 を添加して、ｎ- - 中間層２のキャリア密度を２〜
５×１０15ｃｍ-3と変えたショットキーダイオードを作
製した。Similarly, the growth time of the n − -intermediate layer 2 is changed from 3 to 60 minutes to change the thickness. At that time, a small amount of N 2 is added, and the carrier density of the n − -intermediate layer 2 is changed. To 2
A Schottky diode having a size of 5 × 10 15 cm −3 was manufactured.
【００１９】図２は、ｎ- - 中間層２の厚さとｎ- - 中
間層２によるオン抵抗の増分との関係を示す特性図であ
る。横軸はｎ- - 中間層２の厚さ、縦軸はオン抵抗の増
分であり、ｎ- - 中間層２のキャリア濃度をパラメータ
とした。オン抵抗は順方向の電流−電圧特性から求め
た。FIG. 2, n - - the intermediate layer 2 thickness and n - - is a characteristic diagram showing the relationship between the on-resistance with the intermediate layer 2 increments. The horizontal axis represents the thickness of the n − − intermediate layer 2, the vertical axis represents the increase of the on-resistance, and the carrier concentration of the n − − intermediate layer 2 was used as a parameter. The on-resistance was determined from the forward current-voltage characteristics.
【００２０】ｎ- - 中間層２の厚さを厚くするほど、ま
た、ｎ- - 中間層２のキャリア濃度が低い程オン抵抗の
増分が大きくなっている。例えば、ｎ- - 中間層２のキ
ャリア濃度が１×１０15ｃｍ-3で、厚さが１μｍである
と、オン抵抗の増分は７．５×１０-3Ω・ｃｍ2 であ
る。すなわち１００Ａ・ｃｍ-2の電流密度では、オン電
圧の増分が０．７５Ｖ、キャリア濃度が低いとそれ以上
となり、実用が困難になると思われる。従ってｎ- - 中
間層２の厚さは、１μｍ以下とするのが良い。[0020] n - - it becomes thicker the intermediate layer 2 thickness, also, n - - as the carrier concentration of the intermediate layer 2 is low on-resistance increment is increased. For example, if the carrier concentration of the n − -intermediate layer 2 is 1 × 10 15 cm −3 and the thickness is 1 μm, the increase in on-resistance is 7.5 × 10 −3 Ω · cm 2 . That is, at a current density of 100 A · cm −2 , the increase of the on-state voltage is 0.75 V, and the increase is low when the carrier concentration is low. Therefore, the thickness of the n − − intermediate layer 2 is preferably set to 1 μm or less.
【００２１】図３は、逆方向に５００Ｖ印加したときの
もれ電流のキャリア濃度依存性を示す特性図である。横
軸はｎ- - 中間層２の不純物濃度、縦軸はｎ- - 中間層
２を形成しないもののもれ電流値で規格化した漏れ電流
である。ｎ- - 中間層２の厚さは１００ｎｍとした。FIG. 3 is a characteristic diagram showing the carrier concentration dependence of the leakage current when 500 V is applied in the reverse direction. The horizontal axis n - - the impurity concentration of the intermediate layer 2, the ordinate n - - is a leakage current standardized on the leakage current of which do not form an intermediate layer 2. The thickness of the n − -intermediate layer 2 was 100 nm.
【００２２】図から、ｎ- - 中間層２のキャリア濃度が
低いほど漏れ電流は低減され、８×１０15ｃｍ-3以下で
あれば１／１０以下に、１×１０16ｃｍ-3以下でも１／
８以下に低減されることがわかる。図２の結果と合わせ
てｎ- - 中間層２のキャリア濃度としては、１×１０15
〜１×１０16ｃｍ-3とすると良いことになる。[0022] From Figure, n - - higher carrier concentration in the intermediate layer 2 is low leakage current is reduced, 1/10 or less as long as 8 × 10 15 cm -3 or less, even more than 1 × 10 16 cm -3 1 /
It can be seen that it is reduced to 8 or less. In combination with the result of FIG. 2, the carrier concentration of the n − -intermediate layer 2 is 1 × 10 15
It is good to set it to １1 × 10 16 cm −3 .
【００２３】ｎ- - 中間層２の厚さを１０ｎｍとしたシ
ョットキーダイオードも試作したが、キャリア濃度にか
かわらず、いずれも漏れ電流の低減作用は僅かであっ
た。これは、ｎ- - 中間層２の厚さが薄くて、下層の高
抵抗層の影響が現れるためと考えられる。従って、図
２、３の結果からｎ- - 中間層２の厚さは１０ｎｍ〜１
μｍとすることが重要であると結論される。A Schottky diode in which the thickness of the n − − intermediate layer 2 was set to 10 nm was also experimentally manufactured, but the effect of reducing the leakage current was small in any case regardless of the carrier concentration. This is presumably because the thickness of the n − − intermediate layer 2 is small, and the influence of the underlying high resistance layer appears. Therefore, from the results of FIGS. 2 and 3, the thickness of the n − -intermediate layer 2 is 10 nm to 1 nm.
It is concluded that μm is important.
【００２４】［実施例２］ｎ- - 中間層２は、イオン注
入によって形成することもできる。その方法によるショ
ットキーバリアダイオードの製造方法を以下に述べる。
ｎ- 高抵抗層３の成長までは、実施例１の方法と同じと
する。[Embodiment 2] The n -- intermediate layer 2 can also be formed by ion implantation. A method for manufacturing a Schottky barrier diode by this method will be described below.
Up to the growth of the n - high resistance layer 3, the same method as in the first embodiment is used.
【００２５】ｎ- 高抵抗層３の表面層にアルミニウムイ
オンを注入する。注入条件はドーズ量を２×１０11ｃｍ
-2、加速電圧を５０ｋｅＶとした。注入後Ａｒ雰囲気中
で１６００℃、３０分間加熱し、注入したイオンを活性
化した。これにより、ｎ- 高抵抗層層３の表面層の電子
が補償され、ｎ- - 中間層２が生じる。この後のオーミ
ック電極５、ショットキー電極１の形成は実施例１と同
様とする。Aluminum ions are implanted into the surface layer of the n - high resistance layer 3. The implantation condition is a dose amount of 2 × 10 11 cm.
-2 , and the accelerating voltage was 50 keV. After the implantation, the substrate was heated in an Ar atmosphere at 1600 ° C. for 30 minutes to activate the implanted ions. Thereby, electrons in the surface layer of the n − high resistance layer 3 are compensated, and the n − − intermediate layer 2 is generated. The subsequent formation of the ohmic electrode 5 and the Schottky electrode 1 is the same as in the first embodiment.
【００２６】同様にして、イオン注入時の加速電圧を変
えてｎ- - 中間層２の厚さを変え、また、その際のドー
ズ量を変えて、キャリア密度を変えたショットキーバリ
アダイオードを作製した。それらのショットキーバリア
ダイオードの順方向電流−電圧特性、および逆電圧印加
時のもれ電流を測定したところ、図２、３とほぼ同様の
結果が得られた。Similarly, a Schottky barrier diode is manufactured in which the acceleration voltage at the time of ion implantation is changed to change the thickness of the n − -intermediate layer 2 and the dose is changed to change the carrier density. did. When the forward current-voltage characteristics of these Schottky barrier diodes and the leakage current when a reverse voltage was applied were measured, results substantially similar to those in FIGS.
【００２７】以上の実施例では４Ｈ−ＳｉＣのＳｉ面上
に中間層を形成する例を述べたが、本発明の方法は４Ｈ
−ＳｉＣのＣ面や６Ｈ−ＳｉＣのＳｉ、Ｃ面にも適用で
きると考えられる。またイオン注入法で中間層を形成す
るためのアルミニウムの代わりに、Ｂ（ほう素）、Ｖ
（バナジウム）を用いてもよい。In the above embodiment, an example in which an intermediate layer is formed on the Si surface of 4H-SiC has been described.
It is considered that the present invention can be applied to the C-plane of -SiC and the Si and C-planes of 6H-SiC. Also, instead of aluminum for forming the intermediate layer by ion implantation, B (boron), V
(Vanadium) may be used.
【００２８】[0028]
【発明の効果】以上説明したように本発明によれば炭化
けい素ショットキーバリアダイオードにおいて、高キャ
リア濃度の炭化けい素基板上に、低キャリア濃度の高抵
抗層と、更に低キャリア濃度の薄い中間層とを有し、そ
の中間層表面にショットキー電極を設けたＳｉＣショッ
トキーダイオードとすることにより、逆方向もれ電流を
低減することができる。As described above, according to the present invention, in a silicon carbide Schottky barrier diode, a high resistance layer having a low carrier concentration and a thin layer having a low carrier concentration are formed on a silicon carbide substrate having a high carrier concentration. By using an SiC Schottky diode having an intermediate layer and a Schottky electrode provided on the surface of the intermediate layer, the leakage current in the reverse direction can be reduced.
【００２９】特に、中間層の厚さが１０ｎｍ〜１μｍの
範囲、キャリア濃度が１×１０15〜１×１０16ｃｍ-3の
範囲とすることにより、オン抵抗の増分は僅かに抑えな
がら、もれ電流を約１／１０に低減できることを示し
た。本発明は、Ｓｉショットキーダイオードを超えた電
力用半導体素子としてのＳｉＣショットキーダイオード
の発展、普及に極めて重要な貢献をなすものである。In particular, when the thickness of the intermediate layer is in the range of 10 nm to 1 μm and the carrier concentration is in the range of 1 × 10 15 to 1 × 10 16 cm −3 , the increase of the on-resistance is slightly suppressed. This indicates that the current can be reduced to about 1/10. The present invention makes a very important contribution to the development and spread of SiC Schottky diodes as power semiconductor elements beyond Si Schottky diodes.
【図１】本発明のＳｉＣショットキーダイオードの断面
図FIG. 1 is a cross-sectional view of a SiC Schottky diode of the present invention.
【図２】オン抵抗のｎ- - 中間層厚さ依存性を示す特性
図FIG. 2 is a characteristic diagram showing the dependence of on-resistance on the thickness of an n − -intermediate layer.
【図３】もれ電流のキャリア濃度依存性を示す特性図FIG. 3 is a characteristic diagram showing carrier concentration dependence of leakage current.
１ ショットキー電極 ２ ｎ- - 中間層 ３ ｎ- 高抵抗層 ４ ＳｉＣ基板 ５ オーミック電極DESCRIPTION OF SYMBOLS 1 Schottky electrode 2 n -- Intermediate layer 3 n - High resistance layer 4 SiC substrate 5 Ohmic electrode
Claims (5)
トキーバリアダイオードにおいて、高キャリア濃度の炭
化けい素基板上に、炭化けい素からなる低キャリア濃度
の高抵抗層と、その高抵抗層上に同じ導電型で更に低キ
ャリア濃度の薄い中間層とを有し、炭化けい素基板にオ
ーミック電極を、中間層表面にショットキー電極をそれ
ぞれ設けたことを特徴とする炭化けい素ショットキーバ
リアダイオード。1. A silicon carbide Schottky barrier diode using a silicon carbide crystal, wherein a low carrier concentration high resistance layer made of silicon carbide and a high resistance layer thereof are formed on a silicon carbide substrate having a high carrier concentration. A silicon carbide substrate having an ohmic electrode on the silicon carbide substrate and a schottky electrode on the surface of the intermediate layer. diode.
あることを特徴とする請求項１記載の炭化けい素ショッ
トキーバリアダイオード。2. The silicon carbide Schottky barrier diode according to claim 1, wherein the thickness of the intermediate layer is in the range of 10 nm to 1 μm.
１０16ｃｍ-3の範囲にあることを特徴とする請求項１ま
たは２に記載の炭化けい素ショットキーバリアダイオー
ド。3. The method according to claim 1, wherein the carrier concentration of the intermediate layer is 1 × 10 15 to 1 ×.
3. The silicon carbide Schottky barrier diode according to claim 1, wherein the silicon carbide Schottky barrier diode is in a range of 10 16 cm −3 .
ョットキーバリアダイオードの製造方法において、高キ
ャリア濃度の炭化けい素基板上に、炭化けい素からなる
低キャリア濃度の高抵抗層と、その高抵抗層上に同じ導
電型で更に低キャリア濃度の薄い中間層とをエピタキシ
ャル成長により形成し、炭化けい素基板にオーミック電
極を、中間層表面にショットキー電極をそれぞれ設ける
ことを特徴とする炭化けい素ショットキーバリアダイオ
ードの製造方法。4. A method of manufacturing a silicon carbide Schottky barrier diode using a silicon carbide semiconductor crystal, comprising: a low-carrier-concentration high-resistance layer made of silicon carbide on a high-carrier-concentration silicon carbide substrate; A thin intermediate layer of the same conductivity type and a lower carrier concentration is formed on the high resistance layer by epitaxial growth, and an ohmic electrode is provided on the silicon carbide substrate, and a Schottky electrode is provided on the surface of the intermediate layer. A method for manufacturing an elementary Schottky barrier diode.
ョットキーバリアダイオードの製造方法において、高キ
ャリア濃度の炭化けい素基板上に、炭化けい素からなる
低キャリア濃度の高抵抗層をエピタキシャル成長により
形成し、その高抵抗層の表面層に逆導電型の不純物をイ
オン注入して更に低キャリア濃度の薄い中間層を形成
し、炭化けい素基板にオーミック電極を、中間層表面に
ショットキー電極をそれぞれ設けることを特徴とする炭
化けい素ショットキーバリアダイオードの製造方法。5. A method for manufacturing a silicon carbide Schottky barrier diode using a silicon carbide semiconductor crystal, wherein a high resistance layer having a low carrier concentration made of silicon carbide is epitaxially grown on a silicon carbide substrate having a high carrier concentration. Then, an impurity of the opposite conductivity type is ion-implanted into the surface layer of the high-resistance layer to form a thin intermediate layer having a lower carrier concentration, and an ohmic electrode is formed on the silicon carbide substrate, and a Schottky electrode is formed on the intermediate layer surface. A method for manufacturing a silicon carbide Schottky barrier diode, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30494598A JP2000133819A (en) | 1998-10-27 | 1998-10-27 | Silicon carbide schottky barrier diode and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30494598A JP2000133819A (en) | 1998-10-27 | 1998-10-27 | Silicon carbide schottky barrier diode and manufacture thereof |
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| Publication Number | Publication Date |
|---|---|
| JP2000133819A true JP2000133819A (en) | 2000-05-12 |
Family
ID=17939216
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30494598A Withdrawn JP2000133819A (en) | 1998-10-27 | 1998-10-27 | Silicon carbide schottky barrier diode and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000133819A (en) |
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