JPH0770695B2 - Method for manufacturing silicon carbide semiconductor device - Google Patents
Method for manufacturing silicon carbide semiconductor deviceInfo
- Publication number
- JPH0770695B2 JPH0770695B2 JP7566589A JP7566589A JPH0770695B2 JP H0770695 B2 JPH0770695 B2 JP H0770695B2 JP 7566589 A JP7566589 A JP 7566589A JP 7566589 A JP7566589 A JP 7566589A JP H0770695 B2 JPH0770695 B2 JP H0770695B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon carbide
- single crystal
- layer
- semiconductor device
- crystal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は電気絶縁層として高抵抗炭化珪素単結晶層を有
する炭化珪素半導体装置の製造方法に関する。TECHNICAL FIELD The present invention relates to a method for manufacturing a silicon carbide semiconductor device having a high resistance silicon carbide single crystal layer as an electric insulating layer.
（従来の技術） 珪素（Si）を初めとして，ヒ化ガリウム（GaAs）やリン
化ガリウム（GaP）などの化合物半導体を用いた半導体
装置（例えば，ダイオード，トランジスタ，集積回路，
大規模集積回路，発光ダイオード，半導体レーザ，およ
び電荷結合素子）がエレクトロニクスの各分野において
広範囲に実用化されている。(Prior Art) Semiconductor devices using compound semiconductors such as gallium arsenide (GaAs) and gallium phosphide (GaP) starting with silicon (Si) (eg, diodes, transistors, integrated circuits,
Large-scale integrated circuits, light-emitting diodes, semiconductor lasers, and charge-coupled devices) have been widely used in various fields of electronics.
炭化珪素（SiC）は広い禁制帯幅（2.2〜3.3eV）を有す
る半導体材料であって，熱的，化学的，および機械的に
極めて安定であり，放射線損傷にも強いという優れた特
徴を持っている。珪素のような従来の半導体材料を用い
た半導体装置は，特に高温，高出力駆動，放射線照射な
どの苛酷な条件下では使用が困難である。従って，炭化
珪素を用いた半導体装置は，このような苛酷な条件下で
も使用し得る半導体装置として広範な分野での応用が期
待されている。Silicon carbide (SiC) is a semiconductor material with a wide bandgap (2.2 to 3.3 eV), which is extremely stable thermally, chemically, and mechanically, and has excellent characteristics that it is also resistant to radiation damage. ing. A semiconductor device using a conventional semiconductor material such as silicon is difficult to use, especially under severe conditions such as high temperature, high output drive, and radiation irradiation. Therefore, a semiconductor device using silicon carbide is expected to be applied in a wide range of fields as a semiconductor device that can be used even under such severe conditions.
しかしながら，大きな面積を有し，かつ高品質の炭化珪
素単結晶を，生産性を考慮した工業的規模で安定に供給
し得る結晶成長技術は確立されていない。それゆえ，炭
化珪素は，上述のような多くの利点および可能性を有す
る半導体材料であるにもかかわらず，その実用化が阻ま
れている。However, a crystal growth technique that has a large area and is capable of stably supplying a high-quality silicon carbide single crystal on an industrial scale in consideration of productivity has not been established. Therefore, although silicon carbide is a semiconductor material having many advantages and possibilities as described above, its practical use is hindered.
従来，研究室規模では，例えば昇華再結晶法（レーリー
法）で炭化珪素単結晶を成長させたり，該方法で得られ
た炭化珪素単結晶を基板として，その上に気相成長法
（CVD法）や液相エピタキシャル成長法（LPE法）で炭化
珪素単結晶層をエピタキシャル成長させることにより，
半導体装置の試作が可能なサイズの炭化珪素単結晶を得
ている。しかしながら，これらの方法では，得られた単
結晶の面積が小さく，その寸法や形状を高精度に制御す
ることは困難である。また，炭化珪素が有する結晶多形
および不純物濃度の制御も容易ではない。Conventionally, in a laboratory scale, for example, a silicon carbide single crystal is grown by a sublimation recrystallization method (Rayleigh method), or a silicon carbide single crystal obtained by the method is used as a substrate, and a vapor phase growth method (CVD method is applied thereto. ) Or a liquid phase epitaxial growth method (LPE method) to epitaxially grow a silicon carbide single crystal layer,
We have obtained a silicon carbide single crystal of a size that allows trial manufacture of semiconductor devices. However, with these methods, the area of the obtained single crystal is small, and it is difficult to control the size and shape with high accuracy. Further, it is not easy to control the crystal polymorphism and the impurity concentration of silicon carbide.
これらの問題点を解決するために，本発明者らは，安価
で入手の容易な珪素単結晶基板上に，大きな面積を有す
る良質の炭化珪素単結晶を気相成長させる方法を提案し
た（特開昭59-203799号）。該方法において，炭化珪素
を気相成長させる際に不純物を添加すれば，得られた炭
化珪素単結晶における不純物濃度および伝導型を制御す
ることが可能である。In order to solve these problems, the present inventors have proposed a method of vapor-depositing a good-quality silicon carbide single crystal having a large area on an inexpensive and easily available silicon single crystal substrate (special feature (Kaisho 59-203799). In this method, if an impurity is added when vapor-depositing silicon carbide, it is possible to control the impurity concentration and conductivity type in the obtained silicon carbide single crystal.
炭化珪素半導体装置における電気絶縁層として高抵抗炭
化珪素単結晶層を用いる場合には，その形成方法が問題
となる。このような形成方法としては，例えば上記の気
相成長法により，炭化珪素単結晶層を成長させる際に不
純物を添加する方法や，予め成長させた炭化珪素単結晶
層に不純物を熱拡散させる方法などがある。When a high resistance silicon carbide single crystal layer is used as an electrical insulating layer in a silicon carbide semiconductor device, a method of forming the same becomes a problem. As such a forming method, for example, a method of adding impurities when the silicon carbide single crystal layer is grown by the above-described vapor phase growth method, or a method of thermally diffusing the impurities into the previously grown silicon carbide single crystal layer and so on.
（発明が解決しようとする課題） しかしながら，気相成長の際に添加された炭化珪素単結
晶層中の不純物は，室温では全てがイオン化しているわ
けではなく，温度が上昇するにつれて，該炭化珪素単結
晶層中のキャリア濃度が上昇する。従って，第３図に示
すように，該炭化珪素単結晶層の抵抗率は，温度が上昇
するにつれて低下する。（例えば,A.Suzuki et al.,App
l.Phys.Lett.,49,450（1986）およびM.Yamanaka et a
l.,J.Appl.Phys.,61,599（1987）を参照されたい。）そ
れゆえ，このような方法は，高温動作用の炭化珪素半導
体装置における電気絶縁層の形成には適当ではない。(Problems to be Solved by the Invention) However, not all impurities in the silicon carbide single crystal layer added during vapor phase growth are ionized at room temperature, and as the temperature rises, the impurities are not ionized. The carrier concentration in the silicon single crystal layer increases. Therefore, as shown in FIG. 3, the resistivity of the silicon carbide single crystal layer decreases as the temperature rises. (For example, A. Suzuki et al., App
l. Phys. Lett., 49, 450 (1986) and M. Yamanaka et a.
See l., J. Appl. Phys., 61,599 (1987). Therefore, such a method is not suitable for forming an electrically insulating layer in a silicon carbide semiconductor device for high temperature operation.
他方，予め成長させた炭化珪素単結晶層に不純物を熱拡
散させて高抵抗層を形成する場合には，炭化珪素中にお
ける不純物の拡散定数が小さく,1,600℃以上の高い拡散
温度が必要である。従って，不純物濃度を制御すること
が困難であり，しかも用いた半導体基板や炭化珪素単結
晶層が劣化するおそれがあるため，不純物熱拡散法は炭
化珪素半導体装置のプロセス技術として適当ではない。On the other hand, when a high resistance layer is formed by thermally diffusing impurities into a pre-grown silicon carbide single crystal layer, the diffusion constant of impurities in silicon carbide is small and a high diffusion temperature of 1,600 ° C or higher is required. . Therefore, it is difficult to control the impurity concentration, and the used semiconductor substrate or silicon carbide single crystal layer may be deteriorated. Therefore, the impurity thermal diffusion method is not suitable as a process technology for a silicon carbide semiconductor device.
本発明は上記従来の問題点を解決するものであり，その
目的とするところは，不純物濃度を制御することが容易
であり,500℃付近の高温領域においても電気絶縁層とし
て機能する高抵抗炭化珪素単結晶層を形成し得る炭化珪
素半導体装置の製造方法を提供することにある。The present invention solves the above-mentioned conventional problems, and an object of the present invention is to easily control the impurity concentration and to perform high-resistance carbonization that functions as an electric insulating layer even in a high temperature region near 500 ° C. It is to provide a method for manufacturing a silicon carbide semiconductor device capable of forming a silicon single crystal layer.
（課題を解決するための手段） 本発明は，電気絶縁層として高抵抗炭化珪素層を有する
炭化珪素半導体装置の製造方法であって，半導体基板上
に炭化珪素単結晶層を成長させる工程と，該炭化珪素単
結晶層に所定量のイオンを注入することにより，その表
面領域にイオン注入層を形成する工程と，該イオン注入
層を熱アニール処理することにより，高抵抗炭化珪素単
結晶層を形成する工程とを包含し，そのことにより上記
目的が達成される。(Means for Solving the Problem) The present invention is a method for manufacturing a silicon carbide semiconductor device having a high resistance silicon carbide layer as an electrical insulating layer, which comprises a step of growing a silicon carbide single crystal layer on a semiconductor substrate, By implanting a predetermined amount of ions into the silicon carbide single crystal layer to form an ion implantation layer in its surface region, and by subjecting the ion implantation layer to thermal annealing, a high resistance silicon carbide single crystal layer is formed. Forming step, whereby the above-mentioned object is achieved.
上記イオン注入層を形成する際には，イオン注入は１回
で行うこともできるし，複数回に分けて行うこともでき
る。この場合，注入条件を適切に調節することにより，
所定の不純物濃度および層厚を有するイオン注入層が得
られる。注入するイオンとしては，例えば，ホウ素
（Ｂ）イオン，アルミニウム（Al）イオン，ガリウム
（Ga）イオンなどのIII族元素イオンが挙げられ，特に
ホウ素イオンが好ましい。When forming the above-mentioned ion-implanted layer, the ion-implantation may be performed once or may be divided into a plurality of times. In this case, by adjusting the injection conditions appropriately,
An ion-implanted layer having a predetermined impurity concentration and layer thickness is obtained. Examples of the ions to be implanted include group III element ions such as boron (B) ions, aluminum (Al) ions, and gallium (Ga) ions, with boron ions being particularly preferred.
得られたイオン注入層は，次いで熱アニール処理が施さ
れる。熱アニール処理は，不活性ガス（例えば,Arガ
ス）雰囲気下，約1,000〜1,300℃の温度で行われる。こ
の熱アニール処理により，上記イオン注入層は活性化さ
れて高い抵抗率を有するようになり，電気絶縁層として
機能し得る高抵抗炭化珪素単結晶層が形成される。The obtained ion-implanted layer is then subjected to thermal annealing treatment. The thermal annealing process is performed in an inert gas (for example, Ar gas) atmosphere at a temperature of about 1,000 to 1,300 ° C. By this thermal annealing treatment, the ion-implanted layer is activated and has a high resistivity, and a high-resistance silicon carbide single crystal layer that can function as an electric insulating layer is formed.
（実施例） 以下に本発明の実施例について説明する。(Examples) Examples of the present invention will be described below.
第１図（ａ）は，本発明の製造方法により得られる炭化
珪素半導体装置の一例であるショットキーゲート型電界
効果トランジスタ（MESFET）を示す。該MESFETは以下の
ようにして作製された。FIG. 1A shows a Schottky gate type field effect transistor (MESFET) which is an example of a silicon carbide semiconductor device obtained by the manufacturing method of the present invention. The MESFET was manufactured as follows.
まず，第１図（ｂ）に示すように，気相成長（CVD）法
により,Si単結晶基板１上にノンドープSiC単結晶層２
（層厚約10μｍ）を1,350℃で成長させた。次いで，イ
オン注入装置を用いて，ノンドープSiC単結晶層２の表
面領域にホウ素イオン（11B+）を２回に分けて注入する
ことにより，第１図（ｃ）に示すようなＢイオン注入層
３（層厚約0.5μｍ）を形成した。なお，注入条件は，
加速電圧がそれぞれ200keVおよび100kevであり,Bイオン
の注入量がいずれも１×1015cm-2であった。First, as shown in FIG. 1 (b), a non-doped SiC single crystal layer 2 is formed on a Si single crystal substrate 1 by a vapor phase growth (CVD) method.
(Layer thickness of about 10 μm) was grown at 1,350 ° C. Then, by using an ion implanter, boron ions ( 11 B + ) are implanted into the surface region of the non-doped SiC single crystal layer 2 in two steps, so that B ion implantation as shown in FIG. 1 (c) is performed. Layer 3 (layer thickness about 0.5 μm) was formed. The injection conditions are
The accelerating voltage was 200 keV and 100 kev, respectively, and the implantation amount of B ion was 1 × 10 15 cm -2 .
そして,Ar雰囲気下，約1,300℃にて30分間の熱アニール
処理を行うことにより,Bイオン注入層３を活性化させ，
第１図（ｄ）に示すような高抵抗SiC単結晶層（すなわ
ち，電気絶縁層）４を形成した。該高抵抗SiC単結晶層
４の抵抗率を測定したところ，室温では約５×102Ω・c
mであった。しかも，室温から500℃付近までの広い温度
領域にわたって，抵抗率の低下はほとんど観察されず，
上記の高抵抗SiC単結晶層４が電気絶縁層として充分な
性能を有することがわかった。第２図に，高抵抗SiC単
結晶層（電気絶縁層）４の抵抗率の温度変化を示す。Then, the B ion implantation layer 3 is activated by performing a thermal annealing process at about 1,300 ° C. for 30 minutes in an Ar atmosphere.
A high resistance SiC single crystal layer (that is, an electric insulating layer) 4 as shown in FIG. 1 (d) was formed. When the resistivity of the high-resistance SiC single crystal layer 4 was measured, it was about 5 × 10 2 Ω · c at room temperature.
It was m. Moreover, almost no decrease in resistivity was observed over a wide temperature range from room temperature to around 500 ° C,
It was found that the high resistance SiC single crystal layer 4 described above has sufficient performance as an electric insulating layer. FIG. 2 shows the temperature change of the resistivity of the high resistance SiC single crystal layer (electrical insulating layer) 4.
続いて,CVD法により，電気絶縁層４上にノンドープSiC
単結晶層（層厚約0.5μｍ）を成長させてチャネル層５
とした（第１図（ｅ））。さらに,CVD法またはプラズマ
CVD法により，チャネル層５上にSiO2膜（層厚約１μ
ｍ）を形成した。次いで，ホトリングラフィーを用い
て，SiO2膜の所定領域をエッチングにより開口して，フ
ィールド絶縁膜６とした（第１図（ａ））。なお，エッ
チングにはフッ化水素（HF）溶液を用いた。最後に，ソ
ース領域およびドレイン領域に対応する開口部分には，
それぞれオーミック電極としてニッケル（Ni）を，ゲー
ト領域に対応する開口部分には，ショットキー電極とし
て金（Au）を真空蒸着した後，ホトリングラフィーを用
いて，ソース電極7,ドレイン電極8,およびゲート電極９
を形成することにより，第１図（ａ）に示すようなMESF
ETを得た。Then, non-doped SiC is formed on the electric insulating layer 4 by the CVD method.
A channel layer 5 is formed by growing a single crystal layer (layer thickness of about 0.5 μm).
(Fig. 1 (e)). In addition, CVD method or plasma
The SiO 2 film (layer thickness of about 1 μm was formed on the channel layer 5 by the CVD method.
m) was formed. Next, using photolithography, a predetermined region of the SiO 2 film was opened by etching to form a field insulating film 6 (FIG. 1 (a)). A hydrogen fluoride (HF) solution was used for etching. Finally, in the openings corresponding to the source and drain regions,
Nickel (Ni) was used as an ohmic electrode, and gold (Au) was vacuum-deposited as a Schottky electrode in the opening corresponding to the gate region. Then, the source electrode 7, drain electrode 8, and Gate electrode 9
To form the MESF as shown in Fig. 1 (a).
Got ET.
このようにして得られたMESFETのトランジスタ特性につ
いて調べたところ，チャネル層５の下方に形成された電
気絶縁層４として,Bイオンを注入した高抵抗SiC単結晶
層が用いられているため，該チャネル層５からSiC単結
晶基板１方向へのリーク電流が低減し，良好なトランジ
スタ特性が得られた。また，電気絶縁層４とチャネル層
５との整流特性について調べたところ，室温から500℃
付近の高温まで良好な結果が得られ，特に高温における
上記リーク電流の増加による整流特性の劣化は観察され
なかった。When the transistor characteristics of the MESFET obtained in this way were investigated, it was found that a B ion-implanted high-resistance SiC single crystal layer was used as the electrical insulating layer 4 formed below the channel layer 5. The leak current from the channel layer 5 toward the SiC single crystal substrate 1 was reduced, and good transistor characteristics were obtained. Moreover, when the rectification characteristics of the electric insulating layer 4 and the channel layer 5 were examined, it was found that the temperature was 500 ° C
Good results were obtained up to high temperatures in the vicinity, and no deterioration in rectification characteristics was observed due to the increase in the above leak current, especially at high temperatures.
（発明の効果） 本発明の製造方法によれば，電気絶縁層を形成するのに
イオン注入法を用いるため、500℃付近の高温領域まで
素子特性が劣化しない炭化珪素半導体装置が得られる。
このような炭化珪素半導体装置は，特に高温動作用の半
導体装置として有用である。また，本発明の製造方法
は，通常のイオン注入技術を利用しているため，種々の
炭化珪素半導体装置（例えば，トランジスタや集積回路
など）を工業的規模で生産することが可能になる。(Effect of the Invention) According to the manufacturing method of the present invention, since the ion implantation method is used to form the electrical insulating layer, a silicon carbide semiconductor device in which element characteristics do not deteriorate even in a high temperature region near 500 ° C. can be obtained.
Such a silicon carbide semiconductor device is particularly useful as a semiconductor device for high temperature operation. Further, since the manufacturing method of the present invention uses the ordinary ion implantation technique, it becomes possible to manufacture various silicon carbide semiconductor devices (for example, transistors and integrated circuits) on an industrial scale.
第１図（ａ）〜（ｅ）は本発明の製造方法により得られ
る炭化珪素半導体装置の一例であるショットキー型電界
効果トランジスタの製造工程を説明するための断面図，
第２図は該電界効果トランジスタにおける電気絶縁層の
抵抗率の温度変化を示す図，第３図は従来の製造方法で
形成された電気絶縁層の抵抗率の温度変化を示す図であ
る。 １……Si単結晶基板,2……ノンドープSiC単結晶層,3…
…Ｂイオン注入層,4……電気絶縁層（高抵抗SiC単結晶
層）,5……チャネル層,6……フィールド絶縁層,7……ソ
ース電極,8……ドレイン電極,9……ゲート電極（ショッ
トキー電極）。1 (a) to 1 (e) are sectional views for explaining a manufacturing process of a Schottky field effect transistor which is an example of a silicon carbide semiconductor device obtained by the manufacturing method of the present invention,
FIG. 2 is a diagram showing the temperature change of the resistivity of the electric insulating layer in the field effect transistor, and FIG. 3 is a diagram showing the temperature change of the resistivity of the electric insulating layer formed by the conventional manufacturing method. 1 ... Si single crystal substrate, 2 ... Non-doped SiC single crystal layer, 3 ...
… B ion-implanted layer, 4 …… electrical insulation layer (high resistance SiC single crystal layer), 5 …… channel layer, 6 …… field insulation layer, 7 …… source electrode, 8 …… drain electrode, 9 …… gate Electrode (Schottky electrode).
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/338 21/76 29/812 Ｈ０１Ｌ 21/265 Ｊ (72)発明者 鈴木 彰 大阪府大阪市阿倍野区長池町22番22号 シ ャープ株式会社内 (56)参考文献 特開 昭63−47983（ＪＰ，Ａ) 特開 昭60−264399（ＪＰ，Ａ) 特開 昭60−142568（ＪＰ，Ａ) 特開 昭62−188373（ＪＰ，Ａ)─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical indication location H01L 21/338 21/76 29/812 H01L 21/265 J (72) Inventor Akira Suzuki Osaka, Osaka 22-22 Nagaike-cho, Abeno-ku, Yokohama, Japan (56) References JP-A 63-47983 (JP, A) JP-A 60-264399 (JP, A) JP-A 60-142568 (JP, A) ) JP-A-62-188373 (JP, A)
Claims (1)
を有する炭化珪素半導体装置の製造方法であって， 半導体基板上に炭化珪素単結晶層を成長させる工程と， 該炭化珪素単結晶層に所定量のイオンを注入することに
より，その表面領域にイオン注入層を形成する工程と， 該イオン注入層を熱アニール処理することにより，高抵
抗炭化珪素単結晶層を形成する工程と， を包含する炭化珪素半導体装置の製造方法。1. A method of manufacturing a silicon carbide semiconductor device having a high-resistance silicon carbide single crystal layer as an electrically insulating layer, comprising: a step of growing a silicon carbide single crystal layer on a semiconductor substrate; and the silicon carbide single crystal layer. A step of forming a high-resistance silicon carbide single crystal layer by thermally implanting an ion-implanted layer in the surface region by implanting a predetermined amount of ions into the surface region. A method of manufacturing a silicon carbide semiconductor device including.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7566589A JPH0770695B2 (en) | 1989-03-27 | 1989-03-27 | Method for manufacturing silicon carbide semiconductor device |
| DE4009837A DE4009837A1 (en) | 1989-03-27 | 1990-03-27 | METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE |
| US07/499,889 US5135885A (en) | 1989-03-27 | 1990-03-27 | Method of manufacturing silicon carbide fets |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7566589A JPH0770695B2 (en) | 1989-03-27 | 1989-03-27 | Method for manufacturing silicon carbide semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02253622A JPH02253622A (en) | 1990-10-12 |
| JPH0770695B2 true JPH0770695B2 (en) | 1995-07-31 |
Family
ID=13582738
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7566589A Expired - Fee Related JPH0770695B2 (en) | 1989-03-27 | 1989-03-27 | Method for manufacturing silicon carbide semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0770695B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01246127A (en) * | 1987-12-19 | 1989-10-02 | Idemitsu Petrochem Co Ltd | Recovery of lithium chloride |
| US5270554A (en) * | 1991-06-14 | 1993-12-14 | Cree Research, Inc. | High power high frequency metal-semiconductor field-effect transistor formed in silicon carbide |
| ZA933939B (en) * | 1992-06-05 | 1993-12-30 | De Beers Ind Diamond | Diamond doping |
| JP2666757B2 (en) * | 1995-01-09 | 1997-10-22 | 日本電気株式会社 | Method for manufacturing SOI substrate |
| JP3647515B2 (en) * | 1995-08-28 | 2005-05-11 | 株式会社デンソー | Method for manufacturing p-type silicon carbide semiconductor |
| KR20010061495A (en) * | 1999-12-28 | 2001-07-07 | 박종섭 | SiBC film for interlayer insulation film in a semiconductor device and method of forming a metal wiring using the same |
| JP5298470B2 (en) * | 2007-07-11 | 2013-09-25 | 三菱電機株式会社 | Semiconductor device and method for manufacturing semiconductor device |
-
1989
- 1989-03-27 JP JP7566589A patent/JPH0770695B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02253622A (en) | 1990-10-12 |
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