WO2009090974A1 - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
WO2009090974A1
WO2009090974A1 PCT/JP2009/050417 JP2009050417W WO2009090974A1 WO 2009090974 A1 WO2009090974 A1 WO 2009090974A1 JP 2009050417 W JP2009050417 W JP 2009050417W WO 2009090974 A1 WO2009090974 A1 WO 2009090974A1
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well region
semiconductor device
low
forming
concentration diffusion
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PCT/JP2009/050417
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French (fr)
Japanese (ja)
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Masayasu Tanaka
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Nec Corporation
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66643—Lateral single gate silicon transistors with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a MISFET whose source and drain electrodes are in Schottky contact with a channel region in a semiconductor substrate, and a manufacturing method thereof.
  • MISFET Metal-Insulator-Semiconductor Field Effect Transistor
  • MISFET Metal-Insulator-Semiconductor Field Effect Transistor
  • a metal electrode made of a compound of a metal such as a refractory metal or a noble metal and a semiconductor is used as a source electrode and a drain electrode, and a Schottky junction is formed on a semiconductor substrate.
  • a formed Schottky-Source / Drain (SSD) -MISFET structure has been proposed.
  • an LSI (Large-Scale Integration) circuit in which a MISFET is integrated on a semiconductor substrate is required to suppress various leakage currents generated in the MISFET and reduce standby power consumption.
  • One of the leakage currents is a junction leakage current that flows between the source and drain electrodes and the semiconductor substrate (substrate electrode).
  • the SSD-MISFET in order to reduce the junction leakage current, it is preferable to use a material that has a high junction potential barrier (Schottky barrier) with respect to the substrate for the metal electrodes constituting the source and drain electrodes. .
  • Schottky barrier junction potential barrier
  • Patent Document 1 describes a technique using a material having a high potential barrier. Specifically, bulk Si crystal is used as a semiconductor substrate, and Er silicide or Yb silicide is used for an N-type MISFET and Pt silicide or Ir silicide is used for a P-type MISFET as a metal electrode. Patent Document 2 describes a technique for reducing junction leakage current by using an SOI (Silicon-on-Insulator) substrate as a semiconductor substrate in addition to using the above materials.
  • SOI Silicon-on-Insulator
  • the junction leakage current can be significantly suppressed by using the SOI substrate.
  • the SOI substrate has a problem that the manufacturing process is complicated and the manufacturing cost is very high as compared with a normal bulk Si substrate.
  • an object of the present invention is to provide a semiconductor in which an SSD-MISFET is formed on a semiconductor substrate, which does not require the use of an SOI substrate, has low junction leakage current, and can suppress the short channel effect.
  • An object of the present invention is to provide a device manufacturing method and a semiconductor device formed by such a method.
  • the present invention includes a first conductivity type well region formed on a surface portion of a semiconductor substrate, a gate insulating film formed on the well region, a gate electrode formed on the gate insulating film, and the gate A pair of first-conductivity type low-concentration diffusion regions having an impurity concentration lower than the impurity concentration of the well region, and a surface portion of the pair of low-concentration diffusion regions formed on the surface portion of the well region across the electrode
  • a semiconductor device comprising a source electrode and a drain electrode, each of which is formed of a metal or a compound of a metal and a semiconductor and forms a Schottky junction with the semiconductor substrate.
  • the present invention further includes introducing a impurity into a surface portion of a semiconductor substrate to form a well region, forming a gate insulating film and a gate electrode on the surface of the well region, and sandwiching the gate electrode Forming a pair of low-concentration diffusion regions having an impurity concentration lower than that of the well region on a surface portion of the well region; and forming a Schottky junction with the semiconductor substrate on the surface of the pair of low-concentration diffusion regions
  • a method for manufacturing a semiconductor device is provided. The method includes forming a source electrode and a drain electrode.
  • an SSD-MISFET having a small junction leakage current, low power consumption, a short channel effect is suppressed, and a manufacturing cost can be reduced. can get.
  • FIG. 2A to 2E are cross-sectional views sequentially showing the manufacturing method of the first example for manufacturing the semiconductor device of the embodiment step by step.
  • 3A to 3C are cross-sectional views sequentially showing the manufacturing method of the second example for manufacturing the semiconductor device of the embodiment step by step.
  • FIG. 1 is a cross-sectional view of a semiconductor device having an SSD-MISFET according to this embodiment.
  • the semiconductor device shown in FIG. 1 includes a Si substrate (semiconductor substrate) 11, a trench type element isolation region 12 formed on the surface portion of the Si substrate 11, and a well region 20 formed on the surface portion of the Si substrate 11. And have.
  • the SSD-MISFET includes a gate insulating film 13 formed between the element isolation regions 12 on the surface of the well region 20, a gate electrode 14 formed immediately above the gate insulating film 13, and the gate electrode 14 and the gate insulating film 13.
  • An interlayer insulating film 17 is formed so as to cover the gate electrode 14 and the side wall film 15, and a wiring / contact 18 is connected to the source electrode 16a and the drain electrode 16b.
  • the low concentration region 19 is different from the conventional SSD-MISFET semiconductor device.
  • the low concentration region 19 is a semiconductor having the same conductivity type as the well region 20, and the net impurity concentration is lower in the low concentration region 19 than in the well region 20.
  • the depletion layer of the Schottky junction extending to the bottoms of the source and drain electrodes 16a and 16b becomes longer by providing the low-concentration region 19 as compared with the case where it is not provided. For this reason, the electric field inside the depletion layer is weakened, and the junction leakage current can be reduced for the following reason.
  • the junction leakage current of the SSD-MISFET is a reverse current that flows through the Schottky junction.
  • the reverse current JR is theoretically expressed as a depletion layer internal electric field E, Richardson coefficient A ** , Schottky barrier height ⁇ B0 , semiconductor dielectric constant ⁇ s , elementary charge q, Boltzmann coefficient k, and
  • the absolute temperature T is expressed by the following formula.
  • the semiconductor substrate was assumed to be p-type and the impurity distribution was assumed to be uniform.
  • the depletion layer internal electric field E, the impurity concentration N in the semiconductor substrate at the contact surface, the diffusion potential V B in the semiconductor substrate, and a reverse voltage V R applied to the junction the formula:
  • the diffusion potential V B is expressed by the following equation depending on the Schottky barrier ⁇ B0 , the semiconductor band gap E G , the intrinsic carrier concentration n i of the semiconductor, and the impurity concentration N.
  • Equation (1) by reducing the impurity concentration N in the semiconductor at the contact surface, the diffusion potential V B is reduced from equation (3), and the internal electric field is derived from equation (2). E decreases, and the junction leakage current decreases from Equation (1).
  • the semiconductor device according to the above embodiment can be applied to a semiconductor device having MISFETs of both N-type MISFET and P-type MISFET.
  • the N type and the P type are separately formed by the structure described in the background art, for example.
  • an impurity to be introduced into the semiconductor substrate 11 (well region 20) in the case of an N-type MISFET, an acceptor-type impurity such as B, Al, In, or Ga is introduced, and in the case of a P-type MISFET. May be activated by introducing a donor-type impurity such as P, As, or Sb.
  • the gate electrode 14 may be manufactured so that the work function is optimal for each conductivity type.
  • the gate electrode 14 has a gate length on the gate insulating film 13 of a predetermined length or less, and the effect of the present invention is particularly great for a structure having a gate length of 300 nm or less.
  • it is suitable for a fine MISFET in which an impurity having a high concentration of 5 ⁇ 10 16 cm ⁇ 3 or more is introduced into the well region 20.
  • the upper limit of the impurity in the well region 20 is not limited, but in general, if the impurity is too high, the mobility of minority carriers is significantly deteriorated, so that it is preferably 5 ⁇ 10 19 cm ⁇ 3 or less.
  • the present invention is not limited to the gate length and the impurity concentration of the well region, and can be applied to any structure.
  • the source electrode 16a and the drain electrode 16b are made of a metal that forms a Schottky contact with the semiconductor substrate or a compound of a metal and a semiconductor.
  • a metal that forms a Schottky contact with the semiconductor substrate or a compound of a metal and a semiconductor.
  • Er silicide or Yb silicide is preferable for the N-type MISFET.
  • Pt silicide and Ir silicide are preferable for the P-type MISFET.
  • Pb silicide, Ni silicide, Co silicide, Ti silicide, and W silicide are also applicable.
  • a material obtained by mixing a metal such as Au, Ag, Al, or Ru into the above-described silicide material may be used.
  • the impurity concentration in the well region 20 and in the channel region inside the well region 20, particularly below the gate insulating film In order to reduce the junction leakage current in the Schottky junction of the source and drain electrodes, the impurity concentration of the low concentration region 19 at the bottom of the source and drain electrodes is lowered. Further, the short channel effect is suppressed by setting the impurity concentration of the other well regions 20 sufficiently high. Furthermore, in order to strengthen the suppression of the short channel effect, it is possible to partially increase the impurity concentration of the channel region.
  • the low concentration region 19 is formed so that the bottom thereof is in contact with the well region 20 below the source electrode 16a and the drain electrode 16b.
  • the boundary in the depth direction of the low-concentration region 19 is desirably a position that does not exceed the bottom of the element isolation region 12 even in the deepest case in order to maintain insulation with other semiconductor elements.
  • a bulk substrate having a low substrate manufacturing cost is used as a semiconductor substrate, not an SOI substrate or an SGOI (SiGe-on-Insulator) substrate.
  • it may be an SOI substrate or an SGOI substrate.
  • the effect of the present invention is remarkable by providing the low concentration region 19. Is obtained.
  • the semiconductor substrate which is the low concentration region 19 is etched once in a self-aligned manner after the impurities are introduced into the well region 20. Thereafter, a method of crystal growth of Si using an epitaxial growth technique is used.
  • a well region 20 is formed by introducing a first conductivity type impurity at a depth of 500 nm from the surface of the Si substrate 11 by using an ion implantation technique and performing a heat treatment for activating the impurity. .
  • This state is shown in FIG.
  • the impurity distribution in the well region 20 is substantially uniform, and the impurity concentration is 5 ⁇ 10 17 cm ⁇ 3 on average.
  • a gate insulating film 13 is formed.
  • a silicon oxide film, a silicon oxynitride film, or a high-k film can be used.
  • an example using a silicon oxide film will be described.
  • the silicon oxide film is formed using a thermal oxidation method and has a thickness of 10 nm or less, for example, 3 nm.
  • a gate electrode 14 is formed on the gate insulating film 13.
  • the material of the gate electrode 14 polycrystalline silicon or a metal material can be used. An example using polycrystalline silicon will be described.
  • LPCVD low pressure chemical vapor deposition
  • a protective film 21 of a silicon oxide film is formed using LPCVD. This film is necessary for forming the low concentration region 19 described later.
  • the thickness of the protective film 21 is 15 nm.
  • the pattern of the gate electrode is transferred to the resist film using a photolithography technique, and the protective film 21 and the polycrystalline silicon film are etched using a dry etching technique.
  • the gate electrode 14 is formed through the above steps.
  • the gate length is 50 nm.
  • an impurity of the first conductivity type is implanted using an ion implantation technique, and a heat treatment for impurity activation is performed.
  • This implantation is called so-called pocket implantation, and the effective impurity concentration of the channel region becomes, for example, 5 ⁇ 10 18 cm ⁇ 3 by this implantation.
  • a sidewall film 15 is formed on the side surface of the gate electrode 14.
  • the sidewall film 15 is formed by performing highly anisotropic dry etching after forming a 15 nm silicon oxide film, for example, by LPCVD.
  • the silicon substrate is etched from the surface to a depth of, for example, 150 nm using a dry etching growth technique.
  • a condition that the etching rate of the silicon substrate is sufficiently higher than the etching rate of the silicon oxide film (protective film 21) is used so that the gate electrode 14 is not etched.
  • a silicon crystal is grown on the etched Si substrate 11 using an epitaxial growth technique to form a low concentration region 19. Since crystal growth is sensitive to the surface state, it is preferable to perform acid cleaning, APM cleaning, or DHF cleaning immediately before this step. By this cleaning, the sidewall film 15 and the protective film 21 are etched to a thickness of about 10 nm.
  • a crystal growth condition a condition for growing an intrinsic silicon crystal or a condition for introducing an impurity may be used. At this time, a condition is adopted in which the impurity concentration is lower than that of the well region 20.
  • the height of the upper surface of the crystal-grown silicon crystal is preferably substantially the same as the height of the lower surface of the gate insulating film 13.
  • the protective film 21 is removed if necessary.
  • DHF cleaning is performed.
  • the side wall film 15 is also completely removed, but it is necessary to maintain insulation with respect to the gate electrode 14 in the formation of a source electrode 16a and a drain electrode 16b described later. For this reason, the sidewall film 15 is formed again by using the same method as described above. At this time, the thickness of the sidewall film 15 is, for example, 10 nm.
  • a pretreatment for forming the source electrode 16a and the drain electrode 16b cleaning such as DHF cleaning is performed to clean and expose the surface of the Si substrate.
  • cleaning such as DHF cleaning is performed to clean and expose the surface of the Si substrate.
  • the sidewall film 15 is not completely removed.
  • the thickness of the sidewall film 15 after this pretreatment is, for example, 5 nm.
  • a physical vapor deposition (PVD) method is used to deposit a metal film that will later become a source electrode and a drain electrode to a thickness of 10 nm.
  • PVD physical vapor deposition
  • Er is used for the N-type MISFET and Pt is used for the P-type MISFET.
  • a TiN film may be further sputtered by about 10 nm continuously while maintaining a high degree of vacuum.
  • the material of the metal film one or more metals selected from the group of Er, Yb, Pt, Ir, Pb, Ni, Co, Ti, and W can be used.
  • a heat treatment for causing a silicidation reaction is performed, and a metal film and silicon react to form a silicide film of approximately 20 nm.
  • the heat treatment for the silicidation reaction is preferably performed at a temperature of 150 ° C. or higher and 700 ° C. or lower. In this embodiment, this heat treatment is performed for 5 minutes at a substrate temperature of 500 ° C., for example, in a nitrogen atmosphere. Thereafter, the unreacted surplus metal is removed by acid cleaning, whereby the source electrode 16a and the drain electrode 16b are formed.
  • acid cleaning for example, aqua regia is used for Pt and nitric acid is used for erbium.
  • the upper portion of the gate electrode may be silicided at the same time. Since the silicide films of the source electrode 16a and the drain electrode 16b are grown under the sidewall film 15, the source and drain electrodes reach a part below the gate electrode. This state is preferable from the viewpoint of reducing parasitic resistance.
  • a silicon oxide film is formed at a low temperature of 450 ° C. or lower by using a plasma CVD method or an atmospheric pressure CVD method to form an interlayer insulating film 17.
  • the contact hole pattern is transferred to the resist film using a photolithography technique, and the interlayer insulating film 17 is etched using a dry etching technique to form a contact hole.
  • the resist film is peeled off, and a TiN / Al film, for example, is sequentially deposited on the interlayer insulating film 17 and in the contact hole by the PVD method.
  • a TiN / Al film for example, is sequentially deposited on the interlayer insulating film 17 and in the contact hole by the PVD method.
  • the wiring pattern is patterned into a resist film, and the deposited TiN / Al film is dry-etched to form the wiring / contact 18.
  • the manufacturing method of the first embodiment realizes a high-performance SSD-MISFET with low cost, low power consumption, excellent short channel characteristics. Further, in the manufacturing method of the first embodiment, by using the epitaxial growth technique, the low concentration region 19 is provided at the bottom of the source and drain electrodes forming the Schottky barrier with respect to the substrate, so that the electric field inside the Schottky junction can be increased. Relaxing and achieving a reduction in junction leakage current even in a fine MISFET structure. At the same time, the impurity concentration of the well region 20 and the channel region is increased, and the short channel effect can be suppressed.
  • the above-mentioned effect was confirmed, and in particular, when the gate length is 50 nm which is 300 nm or less, the influence of the short channel effect is significantly reduced. The effect was obtained. Note that the gate length is not limited to 300 nm or less.
  • the manufacturing method of the second embodiment differs from the manufacturing method of the first embodiment in that an ion implantation technique is used to form the low concentration region 19. Specifically, in order to reduce the net impurity concentration while maintaining the low concentration region 19 in the first conductivity type, a method of introducing the second conductivity type impurity within a range not exceeding the impurity concentration before ion implantation. Is used.
  • the other manufacturing steps have many parts in common with the first embodiment, and the different process parts will be mainly described below.
  • FIG. 3A the steps from forming the element isolation region 12 on the surface portion of the Si substrate 11 to the step of forming the sidewall film 15 are performed in the same steps as in the first embodiment.
  • the second embodiment it is not necessary to form the protective film 21 on the gate electrode, and the process of forming the protective film 21 and the process of etching the protective film 21 may not be performed.
  • an impurity of the second conductivity type is implanted into a region having a depth of 150 nm from the surface of the silicon substrate using an ion implantation technique.
  • the impurity concentration of the first conductivity type that is not exceeded the concentration of the first conductivity type existing before the ion implantation is activated, and the impurity is activated by heat treatment to reduce the net impurity concentration.
  • a low concentration region 19 is formed.
  • the wiring / contact 18 is formed from the step of forming the source electrode 16a and the drain electrode 16b on the low concentration region 19 in the same process as in the first embodiment. Perform up to the process.
  • a low-cost, low power consumption, excellent short channel characteristic and high-performance SSD-MISFET can be manufactured.
  • an ion implantation technique is used to provide the low concentration region 19 at the bottom of the source and drain electrodes forming a Schottky barrier with respect to the substrate.
  • the electric field inside the Schottky junction is relaxed, and the junction leakage current is reduced even in a fine MISFET structure.
  • the impurity concentration of the well region 20 and the channel region is increased, and the short channel effect can be suppressed.
  • the above-mentioned effect was confirmed.
  • the gate length is 50 nm which is 300 nm or less, the influence of the short channel effect is significantly reduced. The effect was obtained. Also in this embodiment, the gate length is not limited to 300 nm or less.

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Abstract

Disclosed is a semiconductor device comprising a well region of a first conductivity type, which is formed in the surface portion of a semiconductor substrate, a gate insulating film formed on the well region, a gate electrode formed on the gate insulating film, a pair of low-concentration diffusion regions of the first conductivity type, which are respectively formed in surface portions of the well region sandwiching the gate electrode and have an impurity concentration lower than that of the well region, and a source electrode and a drain electrode respectively formed in the surface portions of the low-concentration diffusion regions and composed of a metal or a compound of a metal and a semiconductor. The source electrode and the drain electrode form a Schottky junction with the semiconductor substrate.

Description

半導体装置及びその製造方法Semiconductor device and manufacturing method thereof
　本発明は半導体装置及びその製造方法に関し、更に詳しくは、半導体基板中のチャネル領域に対して、ソース及びドレイン電極がショットキー接触をするＭＩＳＦＥＴを有する半導体装置、及び、その製造方法に関する。 The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a MISFET whose source and drain electrodes are in Schottky contact with a channel region in a semiconductor substrate, and a manufacturing method thereof.
　ＭＩＳＦＥＴ（Metal-Insulator-Semiconductor Field Effect Transistor）では、短チャネル効果の抑制と、ソース及びドレイン電極の寄生抵抗低減による駆動能力の高性能化が求められている。この要求を達成するための技術の１つとして、ソース電極及びドレイン電極に、高融点金属や貴金属などの金属と半導体との化合物からなる金属電極を使用し、半導体基板に対してショットキー接合を形成したSchottky-Source/Drain（ＳＳＤ）－ＭＩＳＦＥＴ構造が提案されている。 MISFET (Metal-Insulator-Semiconductor Field Effect Transistor) is required to suppress the short channel effect and to improve the driving performance by reducing the parasitic resistance of the source and drain electrodes. As one of the techniques for achieving this requirement, a metal electrode made of a compound of a metal such as a refractory metal or a noble metal and a semiconductor is used as a source electrode and a drain electrode, and a Schottky junction is formed on a semiconductor substrate. A formed Schottky-Source / Drain (SSD) -MISFET structure has been proposed.
　ところで、ＭＩＳＦＥＴを半導体基板上に集積化したＬＳＩ（Large-Scale Integration）回路では、ＭＩＳＦＥＴで発生する各種リーク電流を抑制し、スタンバイ消費電力を低減することも求められている。リーク電流の一つに、ソース電極及びドレイン電極と半導体基板（基板電極）との間に流れる接合リーク電流がある。 Incidentally, an LSI (Large-Scale Integration) circuit in which a MISFET is integrated on a semiconductor substrate is required to suppress various leakage currents generated in the MISFET and reduce standby power consumption. One of the leakage currents is a junction leakage current that flows between the source and drain electrodes and the semiconductor substrate (substrate electrode).
　前記ＳＳＤ－ＭＩＳＦＥＴでは、接合リーク電流の低減のために、ソース及びドレイン電極を構成する金属電極に、基板に対して接合のポテンシャル障壁（ショットキー障壁）が高くなるような材料を用いることが好ましい。これは、Ｎ型ＭＩＳＦＥＴには金属電極にフェルミ準位が伝導帯近傍に近い材料を用い、また、Ｐ型ＭＩＳＦＥＴには金属電極にフェルミ準位が価電子帯に近い材料を用いることで可能となる。 In the SSD-MISFET, in order to reduce the junction leakage current, it is preferable to use a material that has a high junction potential barrier (Schottky barrier) with respect to the substrate for the metal electrodes constituting the source and drain electrodes. . This is possible by using a material whose Fermi level is close to the conduction band in the metal electrode for the N-type MISFET and a material whose Fermi level is close to the valence band for the metal electrode in the P-type MISFET. Become.
　特許文献１には、上記のポテンシャル障壁が高い材料を用いる技術が記載されている。具体的には、半導体基板としてバルクＳｉ結晶が用いられ、金属電極には、Ｎ型ＭＩＳＦＥＴではＥｒシリサイドやＹｂシリサイドが、Ｐ型ＭＩＳＦＥＴではＰｔシリサイドやＩｒシリサイドが用いられている。また、特許文献２には、上記の材料を用いることに加えて、半導体基板にＳＯＩ（Silicon-on-Insulator）基板を用いることで、接合リーク電流の低減を図る技術が記載されている。
特開２００６－２７８８１８号公報 特表２００３－５１７２１０号公報 Patent Document 1 describes a technique using a material having a high potential barrier. Specifically, bulk Si crystal is used as a semiconductor substrate, and Er silicide or Yb silicide is used for an N-type MISFET and Pt silicide or Ir silicide is used for a P-type MISFET as a metal electrode. Patent Document 2 describes a technique for reducing junction leakage current by using an SOI (Silicon-on-Insulator) substrate as a semiconductor substrate in addition to using the above materials.
JP 2006-278818 A Special Table 2003-517210
　上記した特許文献１及び２の技術では、微細なＳＳＤ－ＭＩＳＦＥＴの製造に際しては、製造コストを抑えつつ、半導体装置の接合リーク電流を低減し、短チャネル効果を抑制することが困難である。 In the techniques of Patent Documents 1 and 2 described above, when manufacturing a fine SSD-MISFET, it is difficult to suppress the short channel effect by reducing the junction leakage current of the semiconductor device while suppressing the manufacturing cost.
　本発明者を含む研究グループの調査によると、特許文献１の背景技術に記載された手法では、微細なＳＳＤ－ＭＩＳＦＥＴを形成すると、接合リーク電流の増加を招くことが判った。その原因は、短チャネル効果抑制としきい値電圧制御のために必然となる、基板の不純物濃度の高濃度化に起因していることを確認した。 According to the research of the research group including the present inventor, it was found that, when the fine SSD-MISFET was formed, the junction leakage current was increased by the method described in the background art of Patent Document 1. The cause was confirmed to be due to the increase in the impurity concentration of the substrate, which is inevitable for suppressing the short channel effect and controlling the threshold voltage.
　特許文献２の背景技術に記載された手法では、ＳＯＩ基板を用いることにより、接合リーク電流が大幅に抑制できる。しかし、ＳＯＩ基板は、通常のバルクＳｉ基板と比較して製造工程が複雑であり、製造コストが非常に高いことが問題である。 In the method described in the background art of Patent Document 2, the junction leakage current can be significantly suppressed by using the SOI substrate. However, the SOI substrate has a problem that the manufacturing process is complicated and the manufacturing cost is very high as compared with a normal bulk Si substrate.
　上記に鑑み、本発明の目的は、ＳＯＩ基板を用いることを必須の条件とせずに、接合リーク電流が少なく、且つ、短チャネル効果の抑制が可能なＳＳＤ－ＭＩＳＦＥＴを半導体基板上に形成する半導体装置の製造方法、及び、そのような方法で形成した半導体装置を提供することである。 In view of the above, an object of the present invention is to provide a semiconductor in which an SSD-MISFET is formed on a semiconductor substrate, which does not require the use of an SOI substrate, has low junction leakage current, and can suppress the short channel effect. An object of the present invention is to provide a device manufacturing method and a semiconductor device formed by such a method.
　本発明は、半導体基板の表面部分に形成された第１導電型のウェル領域と、前記ウェル領域上に形成されたゲート絶縁膜と、前記ゲート絶縁膜上に形成されたゲート電極と、前記ゲート電極を挟んだ前記ウェル領域の表面部分に形成され、不純物濃度が前記ウェル領域の不純物濃度よりも低い一対の第１導電型の低濃度拡散領域と、前記一対の低濃度拡散領域の表面部分にそれぞれ形成され、金属又は金属と半導体との化合物からなり、前記半導体基板とショットキー接合を形成するソース電極及びドレイン電極と、を備えることを特徴とする半導体装置を提供する。 The present invention includes a first conductivity type well region formed on a surface portion of a semiconductor substrate, a gate insulating film formed on the well region, a gate electrode formed on the gate insulating film, and the gate A pair of first-conductivity type low-concentration diffusion regions having an impurity concentration lower than the impurity concentration of the well region, and a surface portion of the pair of low-concentration diffusion regions formed on the surface portion of the well region across the electrode Provided is a semiconductor device comprising a source electrode and a drain electrode, each of which is formed of a metal or a compound of a metal and a semiconductor and forms a Schottky junction with the semiconductor substrate.
　本発明は、更に、半導体基板の表面部分に不純物を導入し、ウェル領域を形成する工程と、前記ウェル領域の表面に、ゲート絶縁膜及びゲート電極を形成する工程と、前記ゲート電極を挟んだ前記ウェル領域の表面部分に、前記ウェル領域よりも不純物濃度が低い一対の低濃度拡散領域を形成する工程と、前記一対の低濃度拡散領域の表面に、前記半導体基板とショットキー接合を形成するソース電極及びドレイン電極を形成する工程とを有することを特徴とする半導体装置の製造方法を提供する。 The present invention further includes introducing a impurity into a surface portion of a semiconductor substrate to form a well region, forming a gate insulating film and a gate electrode on the surface of the well region, and sandwiching the gate electrode Forming a pair of low-concentration diffusion regions having an impurity concentration lower than that of the well region on a surface portion of the well region; and forming a Schottky junction with the semiconductor substrate on the surface of the pair of low-concentration diffusion regions A method for manufacturing a semiconductor device is provided. The method includes forming a source electrode and a drain electrode.
　本発明の半導体装置、及び、本発明方法で製造された半導体装置では、接合リーク電流が小さく、消費電力が低く、短チャネル効果が抑制され、且つ、製造コストの低減が可能なＳＳＤ－ＭＩＳＦＥＴが得られる。 In the semiconductor device of the present invention and the semiconductor device manufactured by the method of the present invention, an SSD-MISFET having a small junction leakage current, low power consumption, a short channel effect is suppressed, and a manufacturing cost can be reduced. can get.
　本発明の上記及び他の目的、特徴及び利益は、図面を参照する以下の説明により明らかになる。 The above and other objects, features, and benefits of the present invention will become apparent from the following description with reference to the drawings.
本発明の一実施形態に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on one Embodiment of this invention. 図２Ａ～２Ｅは、実施形態の半導体装置を製造する、第１の実施例の製造方法を段階毎に順次に示す断面図である。2A to 2E are cross-sectional views sequentially showing the manufacturing method of the first example for manufacturing the semiconductor device of the embodiment step by step. 図３Ａ～３Ｃは、実施形態の半導体装置を製造する、第２の実施例の製造方法を段階毎に順次に示す断面図である。3A to 3C are cross-sectional views sequentially showing the manufacturing method of the second example for manufacturing the semiconductor device of the embodiment step by step.
発明を実施するための形態BEST MODE FOR CARRYING OUT THE INVENTION
　以下、図面を参照して本発明の実施形態について詳細に説明する。図１は本実施形態に係るＳＳＤ－ＭＩＳＦＥＴを有する半導体装置の断面図である。図１に示す半導体装置は、Ｓｉ基板（半導体基板）１１と、このＳｉ基板１１の表面部分に形成されたトレンチ型の素子分離領域１２と、Ｓｉ基板１１の表面部分に形成されたウェル領域２０とを有する。ＳＳＤ－ＭＩＳＦＥＴは、ウェル領域２０の表面に素子分離領域１２の間に形成されたゲート絶縁膜１３と、ゲート絶縁膜１３の直上に形成されたゲート電極１４と、ゲート電極１４及びゲート絶縁膜１３の側壁に形成された側壁膜１５と、ゲート絶縁膜１３の下部にゲート絶縁膜１３を挟んで形成されたソース電極１６ａ及びドレイン電極１６ｂと、ソース電極１６ａ及びドレイン電極１６ｂの底部と接触する半導体基板に形成された低濃度拡散領域（低濃度領域）１９とを有する。ゲート電極１４と側壁膜１５とを覆って層間絶縁膜１７が形成され、また、ソース電極１６ａ及びドレイン電極１６ｂには配線／コンタクト１８が接続される。後述するように、低濃度領域１９を設置したことが、従来のＳＳＤ－ＭＩＳＦＥＴ半導体装置と異なる。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a cross-sectional view of a semiconductor device having an SSD-MISFET according to this embodiment. The semiconductor device shown in FIG. 1 includes a Si substrate (semiconductor substrate) 11, a trench type element isolation region 12 formed on the surface portion of the Si substrate 11, and a well region 20 formed on the surface portion of the Si substrate 11. And have. The SSD-MISFET includes a gate insulating film 13 formed between the element isolation regions 12 on the surface of the well region 20, a gate electrode 14 formed immediately above the gate insulating film 13, and the gate electrode 14 and the gate insulating film 13. A side wall film 15 formed on the side wall, a source electrode 16a and a drain electrode 16b formed with the gate insulating film 13 sandwiched between the gate insulating film 13 and a semiconductor in contact with the bottoms of the source electrode 16a and the drain electrode 16b. And a low concentration diffusion region (low concentration region) 19 formed on the substrate. An interlayer insulating film 17 is formed so as to cover the gate electrode 14 and the side wall film 15, and a wiring / contact 18 is connected to the source electrode 16a and the drain electrode 16b. As will be described later, the low concentration region 19 is different from the conventional SSD-MISFET semiconductor device.
　本実施形態の半導体装置では、低濃度領域１９がウェル領域２０と同じ導電型の半導体であり、正味の不純物濃度は低濃度領域１９の方がウェル領域２０の不純物濃度よりも低い。ソース及びドレイン電極１６ａ、１６ｂの底部に延びるショットキー接合の空乏層は、低濃度領域１９を設けることで、設けない場合と比較して長くなる。このため、空乏層内部の電界が弱められ、以下の理由で接合リーク電流の低減が可能となる。 In the semiconductor device of this embodiment, the low concentration region 19 is a semiconductor having the same conductivity type as the well region 20, and the net impurity concentration is lower in the low concentration region 19 than in the well region 20. The depletion layer of the Schottky junction extending to the bottoms of the source and drain electrodes 16a and 16b becomes longer by providing the low-concentration region 19 as compared with the case where it is not provided. For this reason, the electric field inside the depletion layer is weakened, and the junction leakage current can be reduced for the following reason.
　ＳＳＤ－ＭＩＳＦＥＴの接合リーク電流は、ショットキー接合を流れる、逆方向電流である。逆方向電流ＪＲは、理論的に、空乏層内部電界Ｅ、リチャードソン係数Ａ＊＊、ショットキー障壁高さφB0、半導体の誘電率εs 、素電荷量ｑ、ボルツマン係数ｋ、及び、絶対温度Ｔによって、以下の式で表される。なお、半導体基板はｐ型を仮定し、また、不純物分布は均一であると仮定した。
Figure JPOXMLDOC01-appb-M000001
　ここで、空乏層内部電界Ｅは、接触面での半導体基板中の不純物濃度Ｎ、半導体基板中の拡散電位ＶB、及び、接合に印加した逆方向電圧ＶＲによって、以下の式で表される。
Figure JPOXMLDOC01-appb-M000002
　また、拡散電位ＶBは、ショットキー障壁φB0、半導体のバンドギャップＥG, 半導体の真性キャリア濃度ｎi、及び、不純物濃度Ｎによって、以下の式で表される。
Figure JPOXMLDOC01-appb-M000003
 The junction leakage current of the SSD-MISFET is a reverse current that flows through the Schottky junction. The reverse current JR is theoretically expressed as a depletion layer internal electric field E, Richardson coefficient A ** , Schottky barrier height φ B0 , semiconductor dielectric constant ε s , elementary charge q, Boltzmann coefficient k, and The absolute temperature T is expressed by the following formula. The semiconductor substrate was assumed to be p-type and the impurity distribution was assumed to be uniform.
Figure JPOXMLDOC01-appb-M000001
Herein, the depletion layer internal electric field E, the impurity concentration N in the semiconductor substrate at the contact surface, the diffusion potential V B in the semiconductor substrate, and a reverse voltage V R applied to the junction, the formula: The
Figure JPOXMLDOC01-appb-M000002
The diffusion potential V B is expressed by the following equation depending on the Schottky barrier φ B0 , the semiconductor band gap E G , the intrinsic carrier concentration n i of the semiconductor, and the impurity concentration N.
Figure JPOXMLDOC01-appb-M000003
　式（１）～（３）を参照すると、接触面での半導体中の不純物濃度Ｎを低くすることで、式（３）から、拡散電位ＶBが小さくなり、式（２）から、内部電界Ｅは下がり、式（１）から、接合リーク電流が低減する。 Referring to equations (1) to (3), by reducing the impurity concentration N in the semiconductor at the contact surface, the diffusion potential V B is reduced from equation (3), and the internal electric field is derived from equation (2). E decreases, and the junction leakage current decreases from Equation (1).
（ＭＩＳＦＥＴの導電型）
　上記実施形態に係る半導体装置は、Ｎ型ＭＩＳＦＥＴ及びＰ型ＭＩＳＦＥＴの双方の導電型のＭＩＳＦＥＴを有する半導体装置に適用可能である。Ｎ型とＰ型とは、例えば背景技術で説明した構造で作り分ける。Ｓｉ基板の例では、半導体基板１１（ウェル領域２０）に導入する不純物として、Ｎ型ＭＩＳＦＥＴの場合には、Ｂ，Ａｌ，Ｉｎ，Ｇａ等のアクセプター型不純物を導入し、Ｐ型ＭＩＳＦＥＴの場合には、Ｐ，Ａｓ，Ｓｂ等のドナー型不純物を導入し、活性化させればよい。また、ゲート電極１４は、仕事関数がそれぞれの導電型で最適となるように製造すればよい。 (MISFET conductivity type)
The semiconductor device according to the above embodiment can be applied to a semiconductor device having MISFETs of both N-type MISFET and P-type MISFET. The N type and the P type are separately formed by the structure described in the background art, for example. In the case of the Si substrate, as an impurity to be introduced into the semiconductor substrate 11 (well region 20), in the case of an N-type MISFET, an acceptor-type impurity such as B, Al, In, or Ga is introduced, and in the case of a P-type MISFET. May be activated by introducing a donor-type impurity such as P, As, or Sb. The gate electrode 14 may be manufactured so that the work function is optimal for each conductivity type.
（ゲート長と基板不純物濃度）
　ゲート電極１４は、ゲート絶縁膜１３上のゲート長が所定長以下であり、特に、ゲート長が３００ｎｍ以下の構造に対して、本発明による効果が大きい。同様に、短チャネル効果の抑制のため、ウェル領域２０に５×１０１６ｃｍ－３以上の高濃度の不純物を導入する微細なＭＩＳＦＥＴに適している。ウェル領域２０の不純物の上限に制限はないが、一般に、不純物が高濃度すぎると少数キャリアの移動度が大幅に劣化するため、５×１０１９ｃｍ－３以下であることが望ましい。しかし、本発明は、上記のゲート長や、上記のウェル領域の不純物濃度には限られず、任意の構造に適用可能である。 (Gate length and substrate impurity concentration)
The gate electrode 14 has a gate length on the gate insulating film 13 of a predetermined length or less, and the effect of the present invention is particularly great for a structure having a gate length of 300 nm or less. Similarly, in order to suppress the short channel effect, it is suitable for a fine MISFET in which an impurity having a high concentration of 5 × 10 16 cm −3 or more is introduced into the well region 20. The upper limit of the impurity in the well region 20 is not limited, but in general, if the impurity is too high, the mobility of minority carriers is significantly deteriorated, so that it is preferably 5 × 10 19 cm −3 or less. However, the present invention is not limited to the gate length and the impurity concentration of the well region, and can be applied to any structure.
（ソース／ドレイン金属電極）
　ソース電極１６ａ及びドレイン電極１６ｂは、半導体基板とショットキー接触を形成する金属、又は、金属と半導体の化合物で構成されている。具体的な材料は、半導体基板１１にＳｉ基板を用いた例では、Ｎ型ＭＩＳＦＥＴには、ＥｒシリサイドやＹｂシリサイドが好ましい。Ｐ型ＭＩＳＦＥＴには、ＰｔシリサイドやＩｒシリサイドが好ましい。その他、Ｐｂシリサイド、Ｎｉシリサイド、Ｃｏシリサイド、Ｔｉシリサイド、Ｗシリサイドも適用可能である。また、上記のシリサイド材料に、Ａｕ、Ａｇ、Ａｌ、Ｒｕなどの金属を混ぜたものでもよい。 (Source / drain metal electrode)
The source electrode 16a and the drain electrode 16b are made of a metal that forms a Schottky contact with the semiconductor substrate or a compound of a metal and a semiconductor. Specifically, in an example in which a Si substrate is used as the semiconductor substrate 11, Er silicide or Yb silicide is preferable for the N-type MISFET. Pt silicide and Ir silicide are preferable for the P-type MISFET. In addition, Pb silicide, Ni silicide, Co silicide, Ti silicide, and W silicide are also applicable. Further, a material obtained by mixing a metal such as Au, Ag, Al, or Ru into the above-described silicide material may be used.
（短チャネル効果の抑制）
　短チャネル効果の抑制には、ウェル領域２０や、ウェル領域２０の内部の特にゲート絶縁膜の下部のチャネル領域の不純物濃度を高めることが好ましい。上記実施形態では、ソース及びドレイン電極のショットキー接合における接合リーク電流を低減するために、ソース及びドレイン電極の底部の低濃度領域１９の不純物濃度を低くする。また、それ以外のウェル領域２０の不純物濃度を十分に高く設定することで、短チャネル効果を抑制する。さらに、短チャネル効果の抑制を強めるため、チャネル領域の不純物濃度を部分的に高濃度化することも可能である。 (Suppression of short channel effect)
In order to suppress the short channel effect, it is preferable to increase the impurity concentration in the well region 20 and in the channel region inside the well region 20, particularly below the gate insulating film. In the above embodiment, in order to reduce the junction leakage current in the Schottky junction of the source and drain electrodes, the impurity concentration of the low concentration region 19 at the bottom of the source and drain electrodes is lowered. Further, the short channel effect is suppressed by setting the impurity concentration of the other well regions 20 sufficiently high. Furthermore, in order to strengthen the suppression of the short channel effect, it is possible to partially increase the impurity concentration of the channel region.
（低濃度領域の境界）
　低濃度領域１９は、その底部が、ソース電極１６ａ及びドレイン電極１６ｂの下方において、ウェル領域２０と接するように形成する。低濃度領域１９の深さ方向の境界は、他の半導体素子との絶縁性を保つため、最も深い場合でも、素子分離領域１２の底部を超えない位置とすることが望ましい。 (Boundary of low concentration area)
The low concentration region 19 is formed so that the bottom thereof is in contact with the well region 20 below the source electrode 16a and the drain electrode 16b. The boundary in the depth direction of the low-concentration region 19 is desirably a position that does not exceed the bottom of the element isolation region 12 even in the deepest case in order to maintain insulation with other semiconductor elements.
（半導体基板）
　本実施形態に係る半導体装置の製造に際しては、半導体基板として、ＳＯＩ基板や、ＳＧＯＩ（SiGe-on-Insulator）基板ではなく、基板の製造コストが低いバルク基板を用いることを主に想定している。しかし、ＳＯＩ基板やＳＧＯＩ基板であってもよい。例えば、素子構造として、ショットキー・ソース及びドレイン電極の底部が、絶縁膜(Ｉｎｓｕｌａｔｏｒ)ではなく、半導体基板と接触しているものでは、低濃度領域１９を設けることで、本発明による効果が顕著に得られる。 (Semiconductor substrate)
In manufacturing the semiconductor device according to the present embodiment, it is mainly assumed that a bulk substrate having a low substrate manufacturing cost is used as a semiconductor substrate, not an SOI substrate or an SGOI (SiGe-on-Insulator) substrate. . However, it may be an SOI substrate or an SGOI substrate. For example, if the bottom of the Schottky source and drain electrodes is in contact with the semiconductor substrate instead of the insulating film (insulator) as the element structure, the effect of the present invention is remarkable by providing the low concentration region 19. Is obtained.
　次に、上記実施形態の半導体装置を製造する、本発明の第１の実施例に係る半導体装置の製造方法について説明する。第１の実施例では、低濃度領域１９の不純物濃度をウェル領域より低濃度化する手法として、ウェル領域２０への不純物導入後に、セルフアライン的に低濃度領域１９なる半導体基板を一度エッチングし、その後エピタキシャル成長技術を用いて、Ｓｉを結晶成長させる方法を用いる。 Next, a method for manufacturing a semiconductor device according to the first example of the present invention for manufacturing the semiconductor device of the above embodiment will be described. In the first embodiment, as a method of reducing the impurity concentration of the low concentration region 19 from that of the well region, the semiconductor substrate which is the low concentration region 19 is etched once in a self-aligned manner after the impurities are introduced into the well region 20. Thereafter, a method of crystal growth of Si using an epitaxial growth technique is used.
（第１の実施例）
　第１の実施例の製造方法について図２（ａ）から図２（ｅ）を参照して説明する。Ｓｉ基板１１上で、フォトリソグラフィー技術を用いて、素子領域をレジスト膜にパターニングし、垂直性の高いエッチング技術を用いて、深さ３００ｎｍの溝を形成する。次いで、その溝内にシリコン酸化膜を埋め込み、トレンチ型の素子分離領域１２を形成する。 (First embodiment)
The manufacturing method of the first embodiment will be described with reference to FIGS. 2 (a) to 2 (e). On the Si substrate 11, the element region is patterned into a resist film using a photolithography technique, and a groove having a depth of 300 nm is formed using an etching technique with high perpendicularity. Next, a silicon oxide film is buried in the trench to form a trench type element isolation region 12.
　次に、Ｓｉ基板１１の表面から５００ｎｍまでの深さに、イオン注入技術を用いて、第１導電型の不純物を導入し、不純物の活性化の熱処理を行うことで、ウェル領域２０を形成する。この状態を図２（ａ）に示した。ウェル領域２０の不純物分布はほぼ均一で、その不純物濃度は平均値で５×１０１７ｃｍ－３とする。 Next, a well region 20 is formed by introducing a first conductivity type impurity at a depth of 500 nm from the surface of the Si substrate 11 by using an ion implantation technique and performing a heat treatment for activating the impurity. . This state is shown in FIG. The impurity distribution in the well region 20 is substantially uniform, and the impurity concentration is 5 × 10 17 cm −3 on average.
　次に、図２（ｂ）に示すように、ゲート絶縁膜１３を成膜する。ゲート絶縁膜１３としては、シリコン酸化膜、又は、シリコン酸窒化膜、又は、Ｈｉｇｈ－ｋ膜の適用が可能であるが、ここでは、シリコン酸化膜を用いた例を述べる。シリコン酸化膜は、熱酸化法を用いて成膜し、厚さは１０ｎｍ以下で、例えば３ｎｍとする。 Next, as shown in FIG. 2B, a gate insulating film 13 is formed. As the gate insulating film 13, a silicon oxide film, a silicon oxynitride film, or a high-k film can be used. Here, an example using a silicon oxide film will be described. The silicon oxide film is formed using a thermal oxidation method and has a thickness of 10 nm or less, for example, 3 nm.
　続いて、ゲート絶縁膜１３上にゲート電極１４を形成する。ゲート電極１４の材料には、多結晶シリコン、又は、金属材料の採用が可能である。多結晶シリコンを用いた例について述べると、ゲート電極１４の形成では、まず、減圧化学気相成長（ＬＰＣＶＤ）法を用いて、例えば１５０ｎｍの多結晶シリコンを堆積する。 Subsequently, a gate electrode 14 is formed on the gate insulating film 13. As the material of the gate electrode 14, polycrystalline silicon or a metal material can be used. An example using polycrystalline silicon will be described. In forming the gate electrode 14, first, for example, 150 nm polycrystalline silicon is deposited by using a low pressure chemical vapor deposition (LPCVD) method.
　次に、ゲート電極１４の仕事関数制御のため、多結晶シリコン膜にイオン注入技術を用いて不純物を導入する。その後、ＬＰＣＶＤ法を用いてシリコン酸化膜の保護膜２１を成膜する。この膜は、後で説明する低濃度領域１９の形成において必要となる。保護膜２１の厚さは１５ｎｍとする。 Next, in order to control the work function of the gate electrode 14, impurities are introduced into the polycrystalline silicon film by using an ion implantation technique. Thereafter, a protective film 21 of a silicon oxide film is formed using LPCVD. This film is necessary for forming the low concentration region 19 described later. The thickness of the protective film 21 is 15 nm.
　続いて、フォトリソグラフィー技術を用いて、ゲート電極のパターンをレジスト膜に転写し、ドライエッチング技術を用いて、保護膜２１と多結晶シリコン膜とをエッチングする。以上の工程を経て、ゲート電極１４が形成される。ゲート長は５０ｎｍとする。 Subsequently, the pattern of the gate electrode is transferred to the resist film using a photolithography technique, and the protective film 21 and the polycrystalline silicon film are etched using a dry etching technique. The gate electrode 14 is formed through the above steps. The gate length is 50 nm.
　次に、必要に応じて、短チャネル効果を抑制するため、ゲート電極をマスクとして、イオン注入技術を用いて、第１導電型の不純物を注入し、不純物活性化の熱処理を施す。この注入は、いわゆるポケット注入と呼ばれるもので、この注入により、チャネル領域の実効的な不純物濃度は、例えば５×１０１８ｃｍ－３となる。 Next, as necessary, in order to suppress the short channel effect, using the gate electrode as a mask, an impurity of the first conductivity type is implanted using an ion implantation technique, and a heat treatment for impurity activation is performed. This implantation is called so-called pocket implantation, and the effective impurity concentration of the channel region becomes, for example, 5 × 10 18 cm −3 by this implantation.
　次に、ゲート電極１４の側面に側壁膜１５を形成する。側壁膜１５は、ＬＰＣＶＤ法で例えば１５ｎｍシリコン酸化膜を成膜後、異方性の高いドライエッチングを施すことで形成する。 Next, a sidewall film 15 is formed on the side surface of the gate electrode 14. The sidewall film 15 is formed by performing highly anisotropic dry etching after forming a 15 nm silicon oxide film, for example, by LPCVD.
　次に、図２（ｃ）に示すように、低濃度領域１９を形成する前工程として、ドライエッチング成長技術を用いて、シリコン基板を表面から例えば１５０ｎｍの深さまでエッチングする。このとき、ゲート電極１４がエッチングされないように、シリコン基板のエッチングレートが、シリコン酸化膜（保護膜２１）のエッチングレートに対して十分高い条件を用いる。 Next, as shown in FIG. 2C, as a pre-process for forming the low-concentration region 19, the silicon substrate is etched from the surface to a depth of, for example, 150 nm using a dry etching growth technique. At this time, a condition that the etching rate of the silicon substrate is sufficiently higher than the etching rate of the silicon oxide film (protective film 21) is used so that the gate electrode 14 is not etched.
　次に、図２（ｄ）に示すように、エッチングしたＳｉ基板１１に対し、エピタキシャル成長技術を用いて、シリコン結晶を成長させ、低濃度領域１９を形成する。結晶成長は表面状態に敏感であるため、本工程の直前に酸洗浄やＡＰＭ洗浄やＤＨＦ洗浄を行うことが好ましい。この洗浄によって側壁膜１５や保護膜２１はエッチングされ、厚さが１０ｎｍ程度となる。結晶成長の条件としては、真性シリコン結晶を成長させる条件、または、不純物を導入する条件を用いてもよい。このとき、不純物濃度がウェル領域２０よりも低くなる条件を採用する。結晶成長したシリコン結晶の上面の高さは、ゲート絶縁膜１３の下面の高さとほぼ一致させることが好ましい。結晶成長したシリコン結晶の上面の方がゲート絶縁膜１３の下面よりも低い場合には、短チャネル効果が現れやすくなり、一方、高すぎる場合には、後述のソース電極及びドレイン電極がゲート電極下まで届かないため、寄生抵抗が増大し、ドレイン電流の駆動性能が低くなる。 Next, as shown in FIG. 2D, a silicon crystal is grown on the etched Si substrate 11 using an epitaxial growth technique to form a low concentration region 19. Since crystal growth is sensitive to the surface state, it is preferable to perform acid cleaning, APM cleaning, or DHF cleaning immediately before this step. By this cleaning, the sidewall film 15 and the protective film 21 are etched to a thickness of about 10 nm. As a crystal growth condition, a condition for growing an intrinsic silicon crystal or a condition for introducing an impurity may be used. At this time, a condition is adopted in which the impurity concentration is lower than that of the well region 20. The height of the upper surface of the crystal-grown silicon crystal is preferably substantially the same as the height of the lower surface of the gate insulating film 13. When the upper surface of the crystal-grown silicon crystal is lower than the lower surface of the gate insulating film 13, a short channel effect tends to appear. On the other hand, when it is too high, a source electrode and a drain electrode described later are below the gate electrode. Therefore, the parasitic resistance increases and the driving performance of the drain current decreases.
　次に、必要に応じて、保護膜２１を除去する。保護膜２１の除去のため、例えばＤＨＦ洗浄を施す。このとき、側壁膜１５も完全に除去されるが、後述のソース電極１６ａ及びドレイン電極１６ｂの形成において、ゲート電極１４に対する絶縁性を維持するために必要となる。このため、前述した方法と同様の方法を用いて、側壁膜１５を改めて形成する。このとき、側壁膜１５の厚さは例えば１０ｎｍとする。 Next, the protective film 21 is removed if necessary. In order to remove the protective film 21, for example, DHF cleaning is performed. At this time, the side wall film 15 is also completely removed, but it is necessary to maintain insulation with respect to the gate electrode 14 in the formation of a source electrode 16a and a drain electrode 16b described later. For this reason, the sidewall film 15 is formed again by using the same method as described above. At this time, the thickness of the sidewall film 15 is, for example, 10 nm.
　次に、ソース電極１６ａ及びドレイン電極１６ｂを形成するための前処理として、ＤＨＦ洗浄などの洗浄を施し、Ｓｉ基板表面を清浄化し、露出させる。この清浄化では、側壁膜１５が完全に除去されないようにする。この前処理後の側壁膜１５の厚さは、例えば５ｎｍとする。 Next, as a pretreatment for forming the source electrode 16a and the drain electrode 16b, cleaning such as DHF cleaning is performed to clean and expose the surface of the Si substrate. In this cleaning, the sidewall film 15 is not completely removed. The thickness of the sidewall film 15 after this pretreatment is, for example, 5 nm.
　次に、物理気相成長（ＰＶＤ）法を用い、後にソース電極及びドレイン電極となる金属膜を１０ｎｍ厚みに堆積する。金属膜には、例えば、Ｎ型ＭＩＳＦＥＴではＥｒを、Ｐ型ＭＩＳＦＥＴではＰｔを用いる。必要に応じて、高真空度に保ったまま連続で、更にＴｉＮ膜を１０ｎｍ程度スパッタしてもよい。金属膜の材料には、Ｅｒ、Ｙｂ、Ｐｔ、Ｉｒ、Ｐｂ、Ｎｉ、Ｃｏ、Ｔｉ、Ｗの群から選択される１以上の金属を用いることが出来る。 Next, a physical vapor deposition (PVD) method is used to deposit a metal film that will later become a source electrode and a drain electrode to a thickness of 10 nm. For example, Er is used for the N-type MISFET and Pt is used for the P-type MISFET. If necessary, a TiN film may be further sputtered by about 10 nm continuously while maintaining a high degree of vacuum. As the material of the metal film, one or more metals selected from the group of Er, Yb, Pt, Ir, Pb, Ni, Co, Ti, and W can be used.
　次に、シリサイド化反応を起こす熱処理を行い、金属膜とシリコンとが反応することで、およそ２０ｎｍのシリサイド膜が形成される。このシリサイド化反応のための熱処理は、１５０℃以上で７００℃以下の温度が好ましい。本実施例では、この熱処理は、例えば窒素雰囲気下で、５００℃の基板温度で、５分間行う。その後、未反応の余剰金属物を酸洗浄で除去することで、ソース電極１６ａとドレイン電極１６ｂとが形成される。酸洗浄では、例えば、Ｐｔに対して王水を、エルビウムに対して硝酸を用いる。このとき、同時にゲート電極の上部もシリサイド化されてもよい。ソース電極１６ａとドレイン電極１６ｂのシリサイド膜は、側壁膜１５の下まで潜って成長が進むため、ソース及びドレイン電極がゲート電極下の一部にまで到達する。この状態は寄生抵抗低減の観点で好ましい。 Next, a heat treatment for causing a silicidation reaction is performed, and a metal film and silicon react to form a silicide film of approximately 20 nm. The heat treatment for the silicidation reaction is preferably performed at a temperature of 150 ° C. or higher and 700 ° C. or lower. In this embodiment, this heat treatment is performed for 5 minutes at a substrate temperature of 500 ° C., for example, in a nitrogen atmosphere. Thereafter, the unreacted surplus metal is removed by acid cleaning, whereby the source electrode 16a and the drain electrode 16b are formed. In the acid cleaning, for example, aqua regia is used for Pt and nitric acid is used for erbium. At this time, the upper portion of the gate electrode may be silicided at the same time. Since the silicide films of the source electrode 16a and the drain electrode 16b are grown under the sidewall film 15, the source and drain electrodes reach a part below the gate electrode. This state is preferable from the viewpoint of reducing parasitic resistance.
　最後に、図２（ｅ）に示すように、プラズマＣＶＤ法または常圧ＣＶＤ法を用い、４５０℃以下の低温でシリコン酸化膜を成膜し、層間絶縁膜１７を形成する。次に、フォトリソグラフィー技術を用いて、コンタクトホールパターンをレジスト膜に転写し、ドライエッチング技術を用いて層間絶縁膜１７をエッチングし、コンタクトホールを形成する。 Finally, as shown in FIG. 2E, a silicon oxide film is formed at a low temperature of 450 ° C. or lower by using a plasma CVD method or an atmospheric pressure CVD method to form an interlayer insulating film 17. Next, the contact hole pattern is transferred to the resist film using a photolithography technique, and the interlayer insulating film 17 is etched using a dry etching technique to form a contact hole.
　その後、レジスト膜を剥離し、層間絶縁膜１７上及びコンタクトホール内に、例えばＴｉＮ／Ａｌ膜を順次ＰＶＤ法で堆積する。次いで、リソグラフィー技術を用いて、配線パターンをレジスト膜にパターニングし、堆積したＴｉＮ／Ａｌ膜をドライエッチングすることで、配線／コンタクト１８を形成する。 Thereafter, the resist film is peeled off, and a TiN / Al film, for example, is sequentially deposited on the interlayer insulating film 17 and in the contact hole by the PVD method. Next, using a lithography technique, the wiring pattern is patterned into a resist film, and the deposited TiN / Al film is dry-etched to form the wiring / contact 18.
　第１の実施例の製造方法により、低コストで、消費電力が低く、短チャネル特性に優れ、高性能なＳＳＤ－ＭＩＳＦＥＴが実現される。また、第１の実施例の製造方法では、エピタキシャル成長技術を用いて、基板に対してショットキー障壁を成すソース及びドレイン電極の底部に低濃度領域１９を設けることで、ショットキー接合内部の電界を緩和し、微細なＭＩＳＦＥＴ構造においても、接合リーク電流の低減を達成している。同時に、ウェル領域２０やチャネル領域の不純物濃度を高め、短チャネル効果の抑制も可能とした。 The manufacturing method of the first embodiment realizes a high-performance SSD-MISFET with low cost, low power consumption, excellent short channel characteristics. Further, in the manufacturing method of the first embodiment, by using the epitaxial growth technique, the low concentration region 19 is provided at the bottom of the source and drain electrodes forming the Schottky barrier with respect to the substrate, so that the electric field inside the Schottky junction can be increased. Relaxing and achieving a reduction in junction leakage current even in a fine MISFET structure. At the same time, the impurity concentration of the well region 20 and the channel region is increased, and the short channel effect can be suppressed.
　第１の実施例の製造方法で実際にＳＳＤ－ＭＩＳＦＥＴを製造したところ、上記効果が確認され、特に、ゲート長が３００ｎｍ以下である５０ｎｍで、短チャネル効果の影響を大幅に軽減するという顕著な効果が得られた。なお、ゲート長は、３００ｎｍ以下に限定されるものではない。 When the SSD-MISFET was actually manufactured by the manufacturing method of the first embodiment, the above-mentioned effect was confirmed, and in particular, when the gate length is 50 nm which is 300 nm or less, the influence of the short channel effect is significantly reduced. The effect was obtained. Note that the gate length is not limited to 300 nm or less.
（第２の実施例）
　次に第２の実施例の製造方法について説明する。第２の実施例の製造方法は、低濃度領域１９の形成にイオン注入技術を用いる点で、第１の実施例の製造方法と異なる。具体的には、低濃度領域１９を第１導電型に維持しつつ、正味の不純物濃度を下げるために、イオン注入前の不純物濃度を超えない範囲で、第２導電型の不純物を導入する手法が用いられる。その他の製造工程は、第１の実施例と共通する部分が多く、以下では相違する工程部分について主に説明をする。 (Second embodiment)
Next, the manufacturing method of the second embodiment will be described. The manufacturing method of the second embodiment differs from the manufacturing method of the first embodiment in that an ion implantation technique is used to form the low concentration region 19. Specifically, in order to reduce the net impurity concentration while maintaining the low concentration region 19 in the first conductivity type, a method of introducing the second conductivity type impurity within a range not exceeding the impurity concentration before ion implantation. Is used. The other manufacturing steps have many parts in common with the first embodiment, and the different process parts will be mainly described below.
　第２の実施例の製造方法を、図３（ａ）から図３（ｃ）を参照して説明する。図３（ａ）では、第１の実施例と同様の工程で、Ｓｉ基板１１の表面部分に素子分離領域１２を形成する工程から、側壁膜１５を形成する工程までを実施する。ただし、第２の実施例では、ゲート電極上に保護膜２１を形成することは必要ではなく、保護膜２１を形成する工程と保護膜２１をエッチングする工程とは実施しなくても良い。 The manufacturing method of the second embodiment will be described with reference to FIGS. 3 (a) to 3 (c). In FIG. 3A, the steps from forming the element isolation region 12 on the surface portion of the Si substrate 11 to the step of forming the sidewall film 15 are performed in the same steps as in the first embodiment. However, in the second embodiment, it is not necessary to form the protective film 21 on the gate electrode, and the process of forming the protective film 21 and the process of etching the protective film 21 may not be performed.
　続いて、図３（ｂ）に示すように、ゲート電極１４及び側壁膜１５をマスクとして、シリコン基板表面から深さ１５０ｎｍの領域に、イオン注入技術を用いて、第２導電型の不純物を注入する。この注入では、イオン注入前に存在する第１導電型の不純物濃度を超えない範囲の濃度で注入し、熱処理により不純物を活性化することで、正味の不純物濃度を低くした、第１導電型の低濃度領域１９を形成する。 Subsequently, as shown in FIG. 3B, using the gate electrode 14 and the sidewall film 15 as a mask, an impurity of the second conductivity type is implanted into a region having a depth of 150 nm from the surface of the silicon substrate using an ion implantation technique. To do. In this implantation, the impurity concentration of the first conductivity type that is not exceeded the concentration of the first conductivity type existing before the ion implantation is activated, and the impurity is activated by heat treatment to reduce the net impurity concentration. A low concentration region 19 is formed.
　次に、図３（ｃ）に示すように、第１の実施例と同様の工程で、低濃度領域１９上にソース電極１６ａ及びドレイン電極１６ｂを形成する工程から、配線／コンタクト１８を形成する工程までを実施する。 Next, as shown in FIG. 3C, the wiring / contact 18 is formed from the step of forming the source electrode 16a and the drain electrode 16b on the low concentration region 19 in the same process as in the first embodiment. Perform up to the process.
　第２の実施例の製造方法では、第１の実施例と同様に、低コストで、消費電力が低く、短チャネル特性が優れ、高性能なＳＳＤ－ＭＩＳＦＥＴの製造が実現される。また、第２の実施例では、イオン注入技術を用いて、基板に対してショットキー障壁を成すソース及びドレイン電極の底部に低濃度領域１９を設けている。これにより、ショットキー接合内部の電界を緩和し、微細なＭＩＳＦＥＴ構造においても、接合リーク電流の低減を達成している。同時に、ウェル領域２０やチャネル領域の不純物濃度を高め、短チャネル効果を抑制も可能とした。 In the manufacturing method of the second embodiment, as in the first embodiment, a low-cost, low power consumption, excellent short channel characteristic and high-performance SSD-MISFET can be manufactured. In the second embodiment, an ion implantation technique is used to provide the low concentration region 19 at the bottom of the source and drain electrodes forming a Schottky barrier with respect to the substrate. As a result, the electric field inside the Schottky junction is relaxed, and the junction leakage current is reduced even in a fine MISFET structure. At the same time, the impurity concentration of the well region 20 and the channel region is increased, and the short channel effect can be suppressed.
　第２の実施例の製造方法で実際にＳＳＤ－ＭＩＳＦＥＴを製造したところ、上記効果が確認され、特に、ゲート長が３００ｎｍ以下である５０ｎｍで、短チャネル効果の影響を大幅に軽減するという顕著な効果が得られた。なお、本実施例でも、ゲート長は、３００ｎｍ以下に限定されるものではない。 When the SSD-MISFET was actually manufactured by the manufacturing method of the second embodiment, the above-mentioned effect was confirmed. In particular, when the gate length is 50 nm which is 300 nm or less, the influence of the short channel effect is significantly reduced. The effect was obtained. Also in this embodiment, the gate length is not limited to 300 nm or less.
　本発明を特別に示し且つ例示的な実施形態を参照して説明したが、本発明は、その実施形態及びその変形に限定されるものではない。当業者に明らかなように、本発明は、添付のクレームに規定される本発明の精神及び範囲を逸脱することなく、種々の変更が可能である。 Although the invention has been particularly shown and described with reference to illustrative embodiments, the invention is not limited to these embodiments and variations thereof. It will be apparent to those skilled in the art that various modifications can be made to the present invention without departing from the spirit and scope of the invention as defined in the appended claims.
　本出願は、２００８年１月１６日出願に係る日本特許出願２００８－００６４５１号を基礎とし且つその優先権を主張するものであり、引用によってその開示の内容の全てを本出願の明細書中に加入する。 This application is based on and claims the priority of Japanese Patent Application No. 2008-006451 filed on Jan. 16, 2008, the entire disclosure of which is incorporated herein by reference. join.

Claims (10)

  1. 　半導体基板の表面部分に形成された第１導電型のウェル領域と、
    　前記ウェル領域上に形成されたゲート絶縁膜と、
    　前記ゲート絶縁膜上に形成されたゲート電極と、
    　前記ゲート電極を挟んだ前記ウェル領域の表面部分に形成され、不純物濃度が前記ウェル領域の不純物濃度よりも低い一対の第１導電型の低濃度拡散領域と、
    　前記一対の低濃度拡散領域の表面部分にそれぞれ形成され、金属又は金属と半導体との化合物からなり、前記半導体基板とショットキー接合を形成するソース電極及びドレイン電極と、を備えることを特徴とする半導体装置。     A first conductivity type well region formed in a surface portion of a semiconductor substrate;
    A gate insulating film formed on the well region;
    A gate electrode formed on the gate insulating film;
    A pair of first-conductivity-type low-concentration diffusion regions formed on a surface portion of the well region sandwiching the gate electrode and having an impurity concentration lower than the impurity concentration of the well region;
    A source electrode and a drain electrode, which are formed on the surface portions of the pair of low-concentration diffusion regions, are made of metal or a compound of a metal and a semiconductor, and form a Schottky junction with the semiconductor substrate. Semiconductor device.
  2. 　前記ゲート電極のゲート長が３００ｎｍ以下である、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein a gate length of the gate electrode is 300 nm or less.
  3. 　前記ウェル領域の不純物濃度が、５×１０１６ｃｍ－３以上で、５×１０１９ｃｍ－３以下である、請求項１又は２に記載の半導体装置。 3. The semiconductor device according to claim 1, wherein an impurity concentration of the well region is 5 × 10 16 cm −3 or more and 5 × 10 19 cm −3 or less.
  4. 　前記低濃度拡散領域がエピタキシャル成長層で形成されている、請求項１～３の何れか一に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 3, wherein the low concentration diffusion region is formed of an epitaxial growth layer.
  5. 　前記低濃度拡散領域がイオン注入層で形成されている、請求項１～３の何れか一に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 3, wherein the low concentration diffusion region is formed of an ion implantation layer.
  6. 　半導体基板の表面部分に不純物を導入し、ウェル領域を形成する工程と、
    　前記ウェル領域の表面に、ゲート絶縁膜及びゲート電極を形成する工程と、
    　前記ゲート電極を挟んだ前記ウェル領域の表面部分に、前記ウェル領域よりも不純物濃度が低い一対の低濃度拡散領域を形成する工程と、
    　前記一対の低濃度拡散領域の表面に、前記半導体基板とショットキー接合を形成するソース電極及びドレイン電極を形成する工程と、を有することを特徴とする半導体装置の製造方法。     Introducing impurities into the surface portion of the semiconductor substrate to form a well region;
    Forming a gate insulating film and a gate electrode on the surface of the well region;
    Forming a pair of low-concentration diffusion regions having an impurity concentration lower than that of the well region in a surface portion of the well region sandwiching the gate electrode;
    Forming a source electrode and a drain electrode for forming a Schottky junction with the semiconductor substrate, on a surface of the pair of low-concentration diffusion regions.
  7. 　前記低濃度拡散領域を形成する工程が、
    　前記ウェル領域の表面部分を除去する工程と、
    　前記除去されたウェル領域の表面部分に、半導体層をエピタキシャル成長する工程とを有する、請求項６に記載の半導体装置の製造方法。     Forming the low concentration diffusion region comprises:
    Removing a surface portion of the well region;
    The method of manufacturing a semiconductor device according to claim 6, further comprising a step of epitaxially growing a semiconductor layer on the surface portion of the removed well region.
  8. 　前記低濃度拡散領域を形成する工程が、前記ウェル領域の表面部分に不純物イオンを注入する工程を有する、請求項６に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 6, wherein the step of forming the low concentration diffusion region includes a step of implanting impurity ions into a surface portion of the well region.
  9. 　前記ソース電極及びドレイン電極を形成する工程が、 
    　少なくとも前記一対の低濃度拡散領域の表面を洗浄する工程と、
    　前記洗浄された一対の低濃度拡散領域の表面に、Ｅｒ、Ｙｂ、Ｐｔ、Ｉｒ、Ｐｂ、Ｎｉ、Ｃｏ、Ｔｉ、Ｗの群から選択される１つ以上の金属を堆積する工程と、を有する請求項６～８の何れか一に記載の半導体装置の製造方法。     Forming the source and drain electrodes;
    Cleaning at least the surfaces of the pair of low concentration diffusion regions;
    Depositing one or more metals selected from the group consisting of Er, Yb, Pt, Ir, Pb, Ni, Co, Ti, and W on the surface of the cleaned pair of low-concentration diffusion regions. The method for manufacturing a semiconductor device according to any one of claims 6 to 8.
  10. 　前記ソース電極及びドレイン電極を形成する工程が、前記金属を堆積する工程に後続して、１５０℃以上で７００℃以下の温度で前記堆積した金属を熱処理する工程を更に有する、請求項９に記載の半導体装置の製造方法。 The step of forming the source electrode and the drain electrode further includes a step of heat-treating the deposited metal at a temperature of 150 ° C. or more and 700 ° C. or less subsequent to the step of depositing the metal. Semiconductor device manufacturing method.
PCT/JP2009/050417 2008-01-16 2009-01-15 Semiconductor device and method for manufacturing the same WO2009090974A1 (en)

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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09102619A (en) * 1995-07-21 1997-04-15 Deutsche Itt Ind Gmbh Semiconductor device
JPH10116983A (en) * 1996-10-11 1998-05-06 Sanyo Electric Co Ltd Semiconductor device and its manufacture
JPH1168096A (en) * 1997-08-12 1999-03-09 Nec Corp Semiconductor device and manufacture thereof
JPH11289089A (en) * 1998-02-06 1999-10-19 Toshiba Corp Semiconductor device and its manufacture
JP2000133819A (en) * 1998-10-27 2000-05-12 Fuji Electric Co Ltd Silicon carbide schottky barrier diode and manufacture thereof
JP2000299462A (en) * 1999-04-15 2000-10-24 Toshiba Corp Semiconductor device and its manufacture
JP2001068689A (en) * 1999-08-26 2001-03-16 Fuji Electric Co Ltd Manufacture of schottky barrier diode
JP2003023099A (en) * 2001-07-10 2003-01-24 Nissan Motor Co Ltd Field effect transistor
JP2004039982A (en) * 2002-07-05 2004-02-05 Mitsubishi Electric Corp Semiconductor device
JP2006100403A (en) * 2004-09-28 2006-04-13 Fujitsu Ltd Field effect transistor and its manufacturing method

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09102619A (en) * 1995-07-21 1997-04-15 Deutsche Itt Ind Gmbh Semiconductor device
JPH10116983A (en) * 1996-10-11 1998-05-06 Sanyo Electric Co Ltd Semiconductor device and its manufacture
JPH1168096A (en) * 1997-08-12 1999-03-09 Nec Corp Semiconductor device and manufacture thereof
JPH11289089A (en) * 1998-02-06 1999-10-19 Toshiba Corp Semiconductor device and its manufacture
JP2000133819A (en) * 1998-10-27 2000-05-12 Fuji Electric Co Ltd Silicon carbide schottky barrier diode and manufacture thereof
JP2000299462A (en) * 1999-04-15 2000-10-24 Toshiba Corp Semiconductor device and its manufacture
JP2001068689A (en) * 1999-08-26 2001-03-16 Fuji Electric Co Ltd Manufacture of schottky barrier diode
JP2003023099A (en) * 2001-07-10 2003-01-24 Nissan Motor Co Ltd Field effect transistor
JP2004039982A (en) * 2002-07-05 2004-02-05 Mitsubishi Electric Corp Semiconductor device
JP2006100403A (en) * 2004-09-28 2006-04-13 Fujitsu Ltd Field effect transistor and its manufacturing method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
WANG C. ET AL.: "Sub-40nm PtSi Schottky source/ drain metal-oxide-semiconductor field-effect transistors", APPLIED PHYSICS LETTERS, vol. 74, no. 8, 22 February 1999 (1999-02-22), pages 1174 - 1176 *

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