JP2000133801A - High breakdown voltage semiconductor element - Google Patents

High breakdown voltage semiconductor element

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Publication number
JP2000133801A
JP2000133801A JP10305368A JP30536898A JP2000133801A JP 2000133801 A JP2000133801 A JP 2000133801A JP 10305368 A JP10305368 A JP 10305368A JP 30536898 A JP30536898 A JP 30536898A JP 2000133801 A JP2000133801 A JP 2000133801A
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JP
Japan
Prior art keywords
type
low
layer
layers
potential side
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10305368A
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Japanese (ja)
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JP3943732B2 (en
JP2000133801A5 (en
Inventor
Akio Nakagawa
明夫 中川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
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Priority to JP30536898A priority Critical patent/JP3943732B2/en
Publication of JP2000133801A publication Critical patent/JP2000133801A/en
Publication of JP2000133801A5 publication Critical patent/JP2000133801A5/ja
Application granted granted Critical
Publication of JP3943732B2 publication Critical patent/JP3943732B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a high breakdown voltage semiconductor element whose ON-resistance is low. SOLUTION: This high breakdown voltage semiconductor element has a part where N-type layers and P-type layers are alternately and regularly repeated and arranged between a low resistance layer 11 on the high potential side and a low resistance layer 13 on the low potential side. The N-type P-type layers stretch and exist in the direction connecting the low resistance layer on the high potential side with the low resistance layer on the low potential side. When a high voltage is applied, the alternating N-type P-type layers are turned into depletion and support the high voltage. This semiconductor element has a part where heavily-doped N-type layers 16 and heavily-doped P-type layers 15 are repeatedly in contact with each other. At least between the heavily-doped N-type layers or between the heavily-doped P-type layers, semiconductor layers 10 of lightly-doped or insulating layers 14 are interposed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は高耐圧半導体素子に
係わり、特に高耐圧のＭＯＳＦＥＴにおいてオン抵抗を
小さくした素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high withstand voltage semiconductor device, and more particularly to a high withstand voltage MOSFET having a reduced on-resistance.

【０００２】[0002]

【従来の技術】従来、高耐圧を得る構造として図１のよ
うに薄いｐ型とｎ型の層を交互に並べたダイオード構造
が知られている。図２はかかる従来例の不純物分布を示
す特性図である。この薄い層の不純物量（ドーズ量）は
層の厚みにほとんど依存しないので、厚み方向に積分し
た値をｎ、ｐ層とも２×１０12／ｃｍ2 とするのがよ
い。2. Description of the Related Art Conventionally, a diode structure in which thin p-type and n-type layers are alternately arranged as shown in FIG. FIG. 2 is a characteristic diagram showing the impurity distribution of such a conventional example. Since the impurity amount (dose amount) of this thin layer hardly depends on the thickness of the layer, the value integrated in the thickness direction is preferably 2 × 10 12 / cm 2 for both the n and p layers.

【０００３】この構造にＭＯＳＦＥＴ等の半導体素子を
形成した場合、この薄い層の不純物量が当該半導体素子
の抵抗を決めるので、半導体素子の低抵抗化を図るため
には、この不純物量の値をできるだけ大きくするのがよ
い。When a semiconductor element such as a MOSFET is formed in this structure, the amount of impurities in this thin layer determines the resistance of the semiconductor element. Therefore, in order to reduce the resistance of the semiconductor element, the value of the amount of impurities must be reduced. It is better to make it as large as possible.

【０００４】[0004]

【発明が解決しようとする課題】本発明は、上記した高
耐圧を得る構造において、ｎ、ｐ層の不純物量が大きな
半導体素子を提供することを目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device having a high withstand voltage as described above, in which the amount of impurities in the n and p layers is large.

【０００５】[0005]

【課題を解決するための手段】本発明は、高電位側の低
抵抗層と低電位側の低抵抗層の間にｎ型の層とｐ型の層
が交互に規則的に繰り返されて存在する部分を有する高
耐圧半導体素子であって、このｎ型ｐ型層は高電位側の
低抵抗層と低電位側の低抵抗層を結ぶ方向に延在して存
在し、高耐圧引加時にこの交互のｎ，ｐ層が空乏化して
高電圧を支え、高濃度のｎ型と高濃度のｐ型の層が繰り
返し接する部分を有し、少なくとも高濃度のｎ型層同
士、または高濃度のｐ型層同士の間にはそれより低濃度
の半導体層または絶縁層が介在していることを特徴とす
る高耐圧半導体素子を提供する。According to the present invention, an n-type layer and a p-type layer are alternately and regularly repeated between a low-resistance layer on the high potential side and a low-resistance layer on the low potential side. The n-type p-type layer has a portion to be extended, and the n-type p-type layer extends in a direction connecting the low-resistance layer on the high-potential side and the low-resistance layer on the low-potential side. The alternate n and p layers are depleted to support a high voltage, and have a portion where a high concentration n-type layer and a high concentration p-type layer are repeatedly in contact with each other. Provided is a high-breakdown-voltage semiconductor element characterized in that a semiconductor layer or an insulating layer having a lower concentration is interposed between p-type layers.

【０００６】かかる高耐圧半導体素子では、高電位側の
低抵抗層と低電位側の低抵抗層が基板の同一表面に存在
する横型半導体素子において、前記繰り返し存在するｐ
型、ｎ型層のうち、高濃度のｎ型、ｐ型層が接する部分
は、基板表面に形成されかつ規則的に繰り返された溝の
表面より反対導電型の不純物を２重に拡散して形成する
ことが望ましい。In such a high breakdown voltage semiconductor element, in a lateral semiconductor element in which a low-resistance layer on the high potential side and a low-resistance layer on the low potential side are present on the same surface of the substrate, the above-described p-type semiconductor element is repeatedly provided.
Of the n-type and n-type layers, the portion in contact with the high-concentration n-type and p-type layers is formed on the substrate surface and diffuses impurities of the opposite conductivity type more than twice from the surface of the regularly repeated groove. It is desirable to form.

【０００７】本発明者は、ｎ，ｐ層の不純物をできるだ
け近接させておいた場合、不純物量を２×１０12／ｃｍ
2 より大きくできることを見出した。すなわち、図３に
示すようにｎ，ｐ層の接する部分の不純物濃度を高く
し、内部は低不純物濃度で高抵抗とすると、各層の不純
物量は約２倍の４×１０12／ｃｍ2 まで大きくすること
が可能となる。The present inventor has found that when the impurities in the n and p layers are made as close as possible, the impurity amount is 2 × 10 12 / cm.
I found that I can make it bigger than 2 . That is, as shown in FIG. 3, when the impurity concentration at the portion where the n and p layers are in contact is made high and the inside is made to have a low impurity concentration and a high resistance, the impurity amount of each layer is approximately doubled to 4 × 10 12 / cm 2. It is possible to increase it.

【０００８】一般に、ｎ，ｐ層にかかる電圧は、当該
ｎ，ｐ層のドーズ量（不純物量）と厚みの積に比例す
る。ｎ，ｐ層にかかる電圧を所定範囲に維持しつつ、こ
れらの層のドーズ量を高めて素子の低抵抗化を達成する
ためには、上記ｎ，ｐ層の厚みを薄くして互いに近接さ
せて配置することが効果的であることに本発明者は注目
したのである。In general, the voltage applied to the n and p layers is proportional to the product of the dose (impurity) and the thickness of the n and p layers. In order to increase the dose of these layers and achieve a low resistance of the element while maintaining the voltage applied to the n and p layers within a predetermined range, the thicknesses of the n and p layers are reduced to make them close to each other. The inventor has noted that it is effective to dispose them in such a manner.

【０００９】本発明の高耐圧半導体素子によれば、図３
に示すような不純物分布を持つｎ，ｐ層を交互に持つ基
板にＭＯＳＦＥＴを形成した場合、従来構造に比べてオ
ン抵抗を約１／２に低減することが可能となる。According to the high breakdown voltage semiconductor device of the present invention, FIG.
In the case where a MOSFET is formed on a substrate having n and p layers alternately having an impurity distribution as shown in (1), the on-resistance can be reduced to about 約 as compared with the conventional structure.

【００１０】[0010]

【発明の実施の形態】（第１の実施形態）第１の実施形
態を図４に示す。図３の不純物分布を持つ図４の構造の
トレンチＭＯＳＦＥＴを作成することで図２の不純物分
布を持つ場合と比較してオン抵抗は約１／２になる。(First Embodiment) FIG. 4 shows a first embodiment. By forming a trench MOSFET having the structure of FIG. 4 having the impurity distribution of FIG. 3, the on-resistance is reduced to about 比較 as compared with the case of having the impurity distribution of FIG.

【００１１】ここで、実施例の具体的寸法を図３に示
す。ｐ，ｎ層の厚みａ，ｂはそれぞれ１０μｍ以下、高
濃度層の厚みｃ，ｄは２μｍ以下、好ましくは１μｍ以
下に設定する。FIG. 3 shows specific dimensions of the embodiment. The thicknesses a and b of the p and n layers are each set to 10 μm or less, and the thicknesses c and d of the high concentration layer are set to 2 μm or less, preferably 1 μm or less.

【００１２】（第２の実施形態）第２の実施形態を図５
に示す。この素子は横型ＭＯＳＦＥＴであり、ソース側
のｐウエル拡散層とドレインｎ層との間にソース・ドレ
イン方向にトレンチ溝を掘り、この溝からｎ型とｐ型の
２重拡散を行い、この溝は溝の表面を酸化することによ
り酸化膜で埋め込んで作成される。(Second Embodiment) A second embodiment is shown in FIG.
Shown in This device is a lateral MOSFET. A trench is dug in the source / drain direction between a source side p-well diffusion layer and a drain n-layer, and n-type and p-type double diffusions are performed from this trench. Is formed by oxidizing the surface of the groove and embedding it with an oxide film.

【００１３】トレンチ溝の図５のＡ−Ａ´に示す部分で
の断面図を図６に示す。図６のＢ−Ｂ´の断面での不純
物分布を図７に示す。図３のａ，ｂに対応する部分を図
７にもａ，ｂ，ｃ，ｄで示した。FIG. 6 is a sectional view of the trench groove taken along the line AA 'in FIG. FIG. 7 shows the impurity distribution in the section taken along the line BB 'in FIG. Portions corresponding to a and b in FIG. 3 are also indicated by a, b, c, and d in FIG.

【００１４】基板ｐ−の代わりにｎ−基板を使い、ま
た、トレンチを酸化膜でなくｐ−層で埋め込めば図７は
図２と同じになることが理解されよう。ｎ（１６）、ｐ
（１５）はそれぞれ２×１０12／ｃｍ2 のドーズ量を持
つのでａ，ｂの部分のｎ型、ｐ型のドーズ量の和は４×
１０12／ｃｍ2 となり、横型ＭＯＳＦＥＴのオン抵抗を
低減できる。It will be understood that FIG. 7 is the same as FIG. 2 if an n − substrate is used instead of the substrate p − and the trench is buried with a p − layer instead of an oxide film. n (16), p
Since (15) has a dose of 2 × 10 12 / cm 2 , the sum of the n-type and p-type doses of the portions a and b is 4 × 10 12 / cm 2.
10 12 / cm 2 , and the on-resistance of the lateral MOSFET can be reduced.

【００１５】ちなみに、トレンチの長さを５０μｍ、ト
レンチの幅０．４μｍ、トレンチトレンチ間隔０．５μ
ｍとすれば５００Ｖ耐圧の横型ＭＯＳＦＥＴが実現でき
る。Incidentally, the length of the trench is 50 μm, the width of the trench is 0.4 μm, and the interval between the trenches is 0.5 μm.
If m, a lateral MOSFET with a withstand voltage of 500 V can be realized.

【００１６】（第３の実施形態）第３の実施形態を図８
に示す。図５の構造で基板をｐ−基板としてこの基板上
にｎエピ層を設けたものに変えたものである。この構造
でｎ型拡散層を深くしたものは図９に示す不純物分布と
なる。(Third Embodiment) A third embodiment will be described with reference to FIG.
Shown in This is a modification of the structure of FIG. 5 in which the substrate is a p - substrate and an n-epi layer is provided on the substrate. When the n-type diffusion layer is deepened in this structure, the impurity distribution is as shown in FIG.

【００１７】さらに酸化膜でなくｎ型高抵抗層で溝を埋
め込んでもよく、この場合、不純物分布は図１０のよう
になる。Further, the trench may be filled with an n-type high resistance layer instead of an oxide film. In this case, the impurity distribution is as shown in FIG.

【００１８】これ以外に基板を酸化膜が埋め込まれたＳ
ＯＩ基板としても良い。また、トレンチをｎ型またはｐ
型の高抵抗シリコン層で埋め込んでも良い。これ以外に
も当該技術者が容易に考え得る変形はすべて適用可能で
ある。In addition to this, the substrate is made of S having an oxide film embedded therein.
An OI substrate may be used. Also, the trench is made n-type or p-type.
It may be embedded with a high-resistance silicon layer. In addition to this, all modifications that can be easily conceived by those skilled in the art are applicable.

【００１９】[0019]

【発明の効果】本発明によれば、オン抵抗の低い高耐圧
半導体素子を提供することが可能となる。According to the present invention, it is possible to provide a high breakdown voltage semiconductor device having a low on-resistance.

【図面の簡単な説明】[Brief description of the drawings]

【図１】従来例を示す図。FIG. 1 is a diagram showing a conventional example.

【図２】従来例の不純物分布を示す特性図。FIG. 2 is a characteristic diagram showing an impurity distribution of a conventional example.

【図３】本発明の第１の実施形態の不純物分布を示す特
性図。FIG. 3 is a characteristic diagram showing an impurity distribution according to the first embodiment of the present invention.

【図４】本発明を適用する縦型ＭＯＳＦＥＴの構成を示
す斜視図。FIG. 4 is a perspective view showing a configuration of a vertical MOSFET to which the present invention is applied.

【図５】本発明の第２の実施形態を示す斜視図。FIG. 5 is a perspective view showing a second embodiment of the present invention.

【図６】本発明の第２の実施形態を示す部分断面図。FIG. 6 is a partial cross-sectional view showing a second embodiment of the present invention.

【図７】本発明の第２の実施形態の不純物分布を示す特
性図。FIG. 7 is a characteristic diagram showing an impurity distribution according to a second embodiment of the present invention.

【図８】本発明の第３の実施形態を示す斜視図。FIG. 8 is a perspective view showing a third embodiment of the present invention.

【図９】本発明の第３の実施形態の不純物分布を示す特
性図。FIG. 9 is a characteristic diagram showing an impurity distribution according to a third embodiment of the present invention.

【図１０】本発明の第３の実施形態の変形例の不純物分
布を示す特性図。FIG. 10 is a characteristic diagram showing an impurity distribution according to a modification of the third embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１０ ｐ−基板 １１ ｐウエル １２ ｎ＋ソース １３ ｎ＋ドレイン １４ 酸化膜 １５ ｐ型層 １６ ｎ型層 ２０ ｎエピ層Reference Signs List 10 p − substrate 11 p well 12 n + source 13 n + drain 14 oxide film 15 p-type layer 16 n-type layer 20 n epi-layer

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 高電位側の低抵抗層と低電位側の低抵抗
層の間にｎ型の層とｐ型の層が交互に規則的に繰り返さ
れて存在する部分を有する高耐圧半導体素子であって、
このｎ型ｐ型層は高電位側の低抵抗層と低電位側の低抵
抗層を結ぶ方向に延在して存在し、高耐圧引加時にこの
交互のｎ，ｐ層が空乏化して高電圧を支え、高濃度のｎ
型と高濃度のｐ型の層が繰り返し接する部分を有し、少
なくとも高濃度のｎ型層同士、または高濃度のｐ型層同
士の間にはそれより低濃度の半導体層または絶縁層が介
在していることを特徴とする高耐圧半導体素子。1. A high breakdown voltage semiconductor element having a portion in which an n-type layer and a p-type layer are alternately and regularly repeated between a low-resistance layer on a high potential side and a low-resistance layer on a low potential side. And
The n-type p-type layer extends in a direction connecting the low-resistance layer on the high-potential side and the low-resistance layer on the low-potential side, and when the high withstand voltage is applied, the alternate n and p layers are depleted and become high. Support voltage, high concentration of n
A portion in which the mold and the high-concentration p-type layer repeatedly contact each other, and at least between the high-concentration n-type layers or the high-concentration p-type layers, a lower-concentration semiconductor layer or insulating layer is interposed A high-breakdown-voltage semiconductor element characterized in that: 【請求項２】 高電位側の低抵抗層と低電位側の低抵抗
層が基板の同一表面に存在する横型半導体素子におい
て、前記繰り返し存在するｐ型、ｎ型層のうち、高濃度
のｎ型、ｐ型層が接する部分は、基板表面に形成されか
つ規則的に繰り返された溝の表面より反対導電型の不純
物を２重に拡散して形成したことを特徴とする請求項１
記載の高耐圧半導体素子。2. A lateral semiconductor device in which a low-resistance layer on a high potential side and a low-resistance layer on a low potential side are present on the same surface of a substrate. 2. A portion where the mold and p-type layers are in contact with each other is formed by doubly diffusing an impurity of the opposite conductivity type from the surface of the regularly formed groove formed on the substrate surface.
The high breakdown voltage semiconductor device according to the above.
JP30536898A 1998-10-27 1998-10-27 High voltage semiconductor element Expired - Fee Related JP3943732B2 (en)

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JP2000133801A5 JP2000133801A5 (en) 2005-07-28
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