JP2000133801A - 高耐圧半導体素子 - Google Patents

高耐圧半導体素子

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Publication number
JP2000133801A
JP2000133801A JP10305368A JP30536898A JP2000133801A JP 2000133801 A JP2000133801 A JP 2000133801A JP 10305368 A JP10305368 A JP 10305368A JP 30536898 A JP30536898 A JP 30536898A JP 2000133801 A JP2000133801 A JP 2000133801A
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low
layer
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potential side
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JP2000133801A5 (ja
JP3943732B2 (ja
Inventor
Akio Nakagawa
明夫 中川
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

(57)【要約】 【課題】 オン抵抗の低い高耐圧半導体素子を提供する
こと。 【解決手段】 高電位側の低抵抗層１１と低電位側の低
抵抗層１３の間にｎ型の層とｐ型の層が交互に規則的に
繰り返されて存在する部分を有する高耐圧半導体素子で
あって、このｎ型ｐ型層は高電位側の低抵抗層と低電位
側の低抵抗層を結ぶ方向に延在して存在し、高耐圧引加
時にこの交互のｎ，ｐ層が空乏化して高電圧を支え、高
濃度のｎ型１６と高濃度のｐ型の層１５が繰り返し接す
る部分を有し、少なくとも高濃度のｎ型層同士、または
高濃度のｐ型層同士の間はそれより低濃度の半導体層１
０または絶縁層１４が介在していることを特徴とする高
耐圧半導体素子。

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は高耐圧半導体素子に
係わり、特に高耐圧のＭＯＳＦＥＴにおいてオン抵抗を
小さくした素子に関する。
【０００２】
【従来の技術】従来、高耐圧を得る構造として図１のよ
うに薄いｐ型とｎ型の層を交互に並べたダイオード構造
が知られている。図２はかかる従来例の不純物分布を示
す特性図である。この薄い層の不純物量（ドーズ量）は
層の厚みにほとんど依存しないので、厚み方向に積分し
た値をｎ、ｐ層とも２×１０12／ｃｍ2 とするのがよ
い。
【０００３】この構造にＭＯＳＦＥＴ等の半導体素子を
形成した場合、この薄い層の不純物量が当該半導体素子
の抵抗を決めるので、半導体素子の低抵抗化を図るため
には、この不純物量の値をできるだけ大きくするのがよ
い。
【０００４】
【発明が解決しようとする課題】本発明は、上記した高
耐圧を得る構造において、ｎ、ｐ層の不純物量が大きな
半導体素子を提供することを目的とする。
【０００５】
【課題を解決するための手段】本発明は、高電位側の低
抵抗層と低電位側の低抵抗層の間にｎ型の層とｐ型の層
が交互に規則的に繰り返されて存在する部分を有する高
耐圧半導体素子であって、このｎ型ｐ型層は高電位側の
低抵抗層と低電位側の低抵抗層を結ぶ方向に延在して存
在し、高耐圧引加時にこの交互のｎ，ｐ層が空乏化して
高電圧を支え、高濃度のｎ型と高濃度のｐ型の層が繰り
返し接する部分を有し、少なくとも高濃度のｎ型層同
士、または高濃度のｐ型層同士の間にはそれより低濃度
の半導体層または絶縁層が介在していることを特徴とす
る高耐圧半導体素子を提供する。
【０００６】かかる高耐圧半導体素子では、高電位側の
低抵抗層と低電位側の低抵抗層が基板の同一表面に存在
する横型半導体素子において、前記繰り返し存在するｐ
型、ｎ型層のうち、高濃度のｎ型、ｐ型層が接する部分
は、基板表面に形成されかつ規則的に繰り返された溝の
表面より反対導電型の不純物を２重に拡散して形成する
ことが望ましい。
【０００７】本発明者は、ｎ，ｐ層の不純物をできるだ
け近接させておいた場合、不純物量を２×１０12／ｃｍ
2 より大きくできることを見出した。すなわち、図３に
示すようにｎ，ｐ層の接する部分の不純物濃度を高く
し、内部は低不純物濃度で高抵抗とすると、各層の不純
物量は約２倍の４×１０12／ｃｍ2 まで大きくすること
が可能となる。
【０００８】一般に、ｎ，ｐ層にかかる電圧は、当該
ｎ，ｐ層のドーズ量（不純物量）と厚みの積に比例す
る。ｎ，ｐ層にかかる電圧を所定範囲に維持しつつ、こ
れらの層のドーズ量を高めて素子の低抵抗化を達成する
ためには、上記ｎ，ｐ層の厚みを薄くして互いに近接さ
せて配置することが効果的であることに本発明者は注目
したのである。
【０００９】本発明の高耐圧半導体素子によれば、図３
に示すような不純物分布を持つｎ，ｐ層を交互に持つ基
板にＭＯＳＦＥＴを形成した場合、従来構造に比べてオ
ン抵抗を約１／２に低減することが可能となる。
【００１０】
【発明の実施の形態】（第１の実施形態）第１の実施形
態を図４に示す。図３の不純物分布を持つ図４の構造の
トレンチＭＯＳＦＥＴを作成することで図２の不純物分
布を持つ場合と比較してオン抵抗は約１／２になる。
【００１１】ここで、実施例の具体的寸法を図３に示
す。ｐ，ｎ層の厚みａ，ｂはそれぞれ１０μｍ以下、高
濃度層の厚みｃ，ｄは２μｍ以下、好ましくは１μｍ以
下に設定する。
【００１２】（第２の実施形態）第２の実施形態を図５
に示す。この素子は横型ＭＯＳＦＥＴであり、ソース側
のｐウエル拡散層とドレインｎ層との間にソース・ドレ
イン方向にトレンチ溝を掘り、この溝からｎ型とｐ型の
２重拡散を行い、この溝は溝の表面を酸化することによ
り酸化膜で埋め込んで作成される。
【００１３】トレンチ溝の図５のＡ−Ａ´に示す部分で
の断面図を図６に示す。図６のＢ−Ｂ´の断面での不純
物分布を図７に示す。図３のａ，ｂに対応する部分を図
７にもａ，ｂ，ｃ，ｄで示した。
【００１４】基板ｐ−の代わりにｎ−基板を使い、ま
た、トレンチを酸化膜でなくｐ−層で埋め込めば図７は
図２と同じになることが理解されよう。ｎ（１６）、ｐ
（１５）はそれぞれ２×１０12／ｃｍ2 のドーズ量を持
つのでａ，ｂの部分のｎ型、ｐ型のドーズ量の和は４×
１０12／ｃｍ2 となり、横型ＭＯＳＦＥＴのオン抵抗を
低減できる。
【００１５】ちなみに、トレンチの長さを５０μｍ、ト
レンチの幅０．４μｍ、トレンチトレンチ間隔０．５μ
ｍとすれば５００Ｖ耐圧の横型ＭＯＳＦＥＴが実現でき
る。
【００１６】（第３の実施形態）第３の実施形態を図８
に示す。図５の構造で基板をｐ−基板としてこの基板上
にｎエピ層を設けたものに変えたものである。この構造
でｎ型拡散層を深くしたものは図９に示す不純物分布と
なる。
【００１７】さらに酸化膜でなくｎ型高抵抗層で溝を埋
め込んでもよく、この場合、不純物分布は図１０のよう
になる。
【００１８】これ以外に基板を酸化膜が埋め込まれたＳ
ＯＩ基板としても良い。また、トレンチをｎ型またはｐ
型の高抵抗シリコン層で埋め込んでも良い。これ以外に
も当該技術者が容易に考え得る変形はすべて適用可能で
ある。
【００１９】
【発明の効果】本発明によれば、オン抵抗の低い高耐圧
半導体素子を提供することが可能となる。
【図面の簡単な説明】
【図１】従来例を示す図。
【図２】従来例の不純物分布を示す特性図。
【図３】本発明の第１の実施形態の不純物分布を示す特
性図。
【図４】本発明を適用する縦型ＭＯＳＦＥＴの構成を示
す斜視図。
【図５】本発明の第２の実施形態を示す斜視図。
【図６】本発明の第２の実施形態を示す部分断面図。
【図７】本発明の第２の実施形態の不純物分布を示す特
性図。
【図８】本発明の第３の実施形態を示す斜視図。
【図９】本発明の第３の実施形態の不純物分布を示す特
性図。
【図１０】本発明の第３の実施形態の変形例の不純物分
布を示す特性図。
【符号の説明】
１０ ｐ−基板 １１ ｐウエル １２ ｎ＋ソース １３ ｎ＋ドレイン １４ 酸化膜 １５ ｐ型層 １６ ｎ型層 ２０ ｎエピ層

Claims (2)

    【特許請求の範囲】
  1. 【請求項１】 高電位側の低抵抗層と低電位側の低抵抗
    層の間にｎ型の層とｐ型の層が交互に規則的に繰り返さ
    れて存在する部分を有する高耐圧半導体素子であって、
    このｎ型ｐ型層は高電位側の低抵抗層と低電位側の低抵
    抗層を結ぶ方向に延在して存在し、高耐圧引加時にこの
    交互のｎ，ｐ層が空乏化して高電圧を支え、高濃度のｎ
    型と高濃度のｐ型の層が繰り返し接する部分を有し、少
    なくとも高濃度のｎ型層同士、または高濃度のｐ型層同
    士の間にはそれより低濃度の半導体層または絶縁層が介
    在していることを特徴とする高耐圧半導体素子。
  2. 【請求項２】 高電位側の低抵抗層と低電位側の低抵抗
    層が基板の同一表面に存在する横型半導体素子におい
    て、前記繰り返し存在するｐ型、ｎ型層のうち、高濃度
    のｎ型、ｐ型層が接する部分は、基板表面に形成されか
    つ規則的に繰り返された溝の表面より反対導電型の不純
    物を２重に拡散して形成したことを特徴とする請求項１
    記載の高耐圧半導体素子。
JP30536898A 1998-10-27 1998-10-27 高耐圧半導体素子 Expired - Fee Related JP3943732B2 (ja)

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JP2000133801A true JP2000133801A (ja) 2000-05-12
JP2000133801A5 JP2000133801A5 (ja) 2005-07-28
JP3943732B2 JP3943732B2 (ja) 2007-07-11

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Cited By (9)

* Cited by examiner, † Cited by third party
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WO2001003202A1 (en) * 1999-07-02 2001-01-11 Kabushiki Kaisha Toyota Chuo Kenkyusho Vertical semiconductor device and method for producing the same
JP2006245082A (ja) * 2005-03-01 2006-09-14 Toshiba Corp 半導体装置
JP2006324432A (ja) * 2005-05-18 2006-11-30 Fuji Electric Holdings Co Ltd 半導体装置およびその製造方法
JP2007266505A (ja) * 2006-03-29 2007-10-11 Toshiba Corp 電力用半導体素子
JP2008283151A (ja) * 2007-05-14 2008-11-20 Denso Corp 半導体装置およびその製造方法
KR101023079B1 (ko) 2008-11-04 2011-03-25 주식회사 동부하이텍 반도체 소자 및 그의 제조 방법
US8106447B2 (en) 2008-08-08 2012-01-31 Sony Corporation Semiconductor device and method of manufacturing the same
WO2019186224A1 (ja) * 2018-03-26 2019-10-03 日産自動車株式会社 半導体装置及びその製造方法
CN117766588A (zh) * 2024-02-22 2024-03-26 南京邮电大学 具有延伸漏结构的超结双soi-ldmos器件及制造方法

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