CN117766588B - Super-junction double SOI-LDMOS device with extended drain structure and manufacturing method - Google Patents
Super-junction double SOI-LDMOS device with extended drain structure and manufacturing method Download PDFInfo
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- CN117766588B CN117766588B CN202410196269.5A CN202410196269A CN117766588B CN 117766588 B CN117766588 B CN 117766588B CN 202410196269 A CN202410196269 A CN 202410196269A CN 117766588 B CN117766588 B CN 117766588B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 175
- 239000002184 metal Substances 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 15
- 238000009826 distribution Methods 0.000 abstract description 10
- 239000000969 carrier Substances 0.000 abstract description 4
- 230000009977 dual effect Effects 0.000 description 14
- 230000005684 electric field Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
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- 229910052710 silicon Inorganic materials 0.000 description 2
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Abstract
The invention provides a super junction double SOI-LDMOS device with an extended drain structure and a manufacturing method thereof, wherein the device comprises the following components: a second SOI layer on the second buried oxide layer, comprising a semiconductor region and a semiconductor extension drain contact region; the first SOI layer is positioned on the first buried oxide layer and comprises a body contact region, a source region, a drain region and a drift region; a drain metal, wherein a first portion of the drain metal is in contact with the first buried oxide layer parallel to a side surface of the device in a longitudinal direction, and a lower surface thereof is in contact with an upper surface of the semiconductor extension drain contact region; a second portion of the drain metal is in contact with an upper surface of the semiconductor drain region. When the device is conducted, the first semiconductor region, the second semiconductor region and the extended drain structure which are alternately arranged in the second SOI layer are utilized, so that majority carriers are induced on the surface of the drift region of the first SOI layer, and the specific on-resistance is reduced; the potential field distribution of the drift region is also improved when the device is turned off, thereby increasing the breakdown voltage.
Description
Technical Field
The invention belongs to the field of semiconductor devices, and particularly relates to a super-junction double-SOI-LDMOS device with an extended drain structure and a manufacturing method thereof.
Background
Double SOI devices have an additional SOI layer, an intermediate silicon layer below the conventional buried oxide layer. It can act as an independent electrode, applying both positive and negative bias voltages in the circuit, which widens the flexibility of the integrated circuit design. In addition, the electrode can further optimize speed, power consumption, threshold voltage drift, and leakage current. Due to its unique structure, the dual SOI device is very promising in three-dimensional fin waveguide fabrication, high resolution detector, and even in situ sensing applications.
In the long-term development process of the power device, the requirement for the power double-SOI structure is always developed towards the directions of high withstand voltage and low specific on-resistance, meanwhile, due to the 'silicon limit' relation, namely, the specific on-resistance of the device is in direct proportion to the power of 2.5 of breakdown voltage, and the increase of the breakdown voltage also leads to the increase of the specific on-resistance. The reciprocal relationship between decreasing the specific on-resistance and increasing the breakdown voltage limits the device development.
Disclosure of Invention
The invention aims to provide a super-junction double-SOI-LDMOS device with an extended drain structure and a manufacturing method thereof, wherein when the device is conducted, a first semiconductor region, a second semiconductor region and an extended drain structure (namely drain metal 13) which are alternately arranged in a second SOI layer are utilized, so that majority carriers are induced on the surface of a drift region of the first SOI layer, and the specific on resistance is reduced; the potential field distribution of the drift region is also improved at the time of turn-off to thereby increase the breakdown voltage, so that a larger FOM value (square of breakdown voltage/specific on-resistance) can be obtained.
A superjunction dual SOI-LDMOS device having an extended drain structure, comprising:
A substrate 1;
A second buried oxide layer 2 on the substrate 1;
a second SOI layer located on the second buried oxide layer 2, comprising:
A semiconductor region including a first semiconductor region 4 and a second semiconductor region 5 which are arranged in parallel and have different doping types; the first semiconductor region 4 is parallel to one lateral surface of the device transverse direction and is contacted with one lateral surface of the second semiconductor region 5 parallel to the device transverse direction;
a semiconductor extended drain contact region 3 which is parallel to one side of the device longitudinal direction and is in contact with one side of the semiconductor region parallel to the device longitudinal direction;
A first buried oxide layer 6 on the second SOI layer;
A first SOI layer on the first buried oxide layer 6, comprising a semiconductor body contact region 7, a semiconductor source region 8, a semiconductor drain region 9, and a drift region between the semiconductor body contact region 7 and the semiconductor drain region 9;
the semiconductor drain region 9 is arranged close to the semiconductor body contact region 7; a side surface of the semiconductor source region 8 parallel to the longitudinal direction of the device is in contact with the semiconductor body contact region 7;
The drift region comprises a third semiconductor region 15 and a fourth semiconductor region 16 arranged in parallel;
wherein the third semiconductor region 15 is parallel to one lateral surface of the device transverse direction and is contacted with one lateral surface of the fourth semiconductor region 16 parallel to the device transverse direction;
The doping type of the third semiconductor region 15 is the same as that of the first semiconductor region 4; the doping type of the fourth semiconductor region 16 is the same as that of the second semiconductor region 5;
A drain metal 13, wherein a first part of the drain metal 13 is in contact with the first buried oxide layer 6 parallel to one side of the longitudinal direction of the device, and the lower surface of the drain metal 13 is in contact with the upper surface of the semiconductor extension drain contact region 3; a second portion of the drain metal 13 is in contact with the upper surface of the semiconductor drain region 9;
An insulating dielectric layer 14 interposed between the first portion and the second portion of the drain metal 13 and in contact with the semiconductor drain region 9;
A source metal 10 in contact with the upper surface of the semiconductor source region 8;
And a gate metal 11, forming a gap with the source metal 10, which is disposed on the gate oxide layer 12, wherein the gate oxide layer 12 is simultaneously in contact with the upper surfaces of the semiconductor body contact region 7, the semiconductor source region 8 and the drift region.
Preferably, the first semiconductor region 4 is disposed directly below the fourth semiconductor region 16; the second semiconductor region 5 is disposed directly below the third semiconductor region 15.
Preferably, the doping type of the first semiconductor region 4 is P-type or N-type.
Preferably, the doping concentration C1 of the first semiconductor region 4 is lower than the doping concentration C3 of the third semiconductor region 15;
The doping concentration C2 of the second semiconductor region 5 is lower than the doping concentration C4 of the fourth semiconductor region 16.
A method for manufacturing a super junction double SOI-LDMOS device with an extended drain structure comprises the following steps:
step 1, growing an oxide layer on a substrate 1 to form a second buried oxide layer 2;
step 2, forming a semiconductor region and a semiconductor extension drain contact region 3 on the second buried oxide layer 2 by ion implantation;
Step 3, growing an oxide layer on the second SOI layer to form a first buried oxide layer 6;
Step 4, depositing oxide to form an insulating medium layer 14;
Step 5, etching oxide at a preset position;
step 6, ion implantation is performed on the first oxygen-buried layer 6 to form a semiconductor source region 8, a semiconductor body contact region 7, a drift region and a semiconductor drain region 9 respectively;
step 7, growing oxide layers on the semiconductor body contact region 7, the semiconductor source region 8 and the drift region to form a gate oxide layer 12;
Step 8, disposing the gate metal 11 on the gate oxide layer 12, disposing the source metal 10 on the semiconductor source region 8, disposing the second portion of the drain metal 13 on the semiconductor drain region 9, and disposing the first portion of the drain metal 13 on the semiconductor extended drain contact region 3.
Compared with the prior art, the invention has the advantages that:
1. The device utilizes the first semiconductor region, the second semiconductor region and the extended drain structure which are alternately arranged in the second SOI layer when the device is conducted, so that majority carriers are induced on the surface of the drift region of the first SOI layer, and the specific on-resistance is reduced.
2. The electric field and potential distribution of the drift region are improved and the breakdown voltage is increased when the device is turned off, so that a larger FOM value can be obtained.
Drawings
FIG. 1 is a perspective view of a superjunction dual SOI-LDMOS device having an extended drain structure;
FIG. 2 is a two-dimensional potential distribution diagram of a superjunction dual SOI-LDMOS device having an extended drain structure;
FIG. 3 is a two-dimensional potential distribution diagram of a conventional double SOI structure;
FIG. 4 is a impact ionization rate profile of a superjunction dual SOI-LDMOS device having an extended drain structure;
FIG. 5 is a graph of impact ionization rate distribution for a conventional dual SOI structure;
FIG. 6 is a three-dimensional electric field distribution diagram of a superjunction dual SOI-LDMOS device having an extended drain structure;
FIG. 7 is a three-dimensional electric field distribution diagram of a conventional SOI structure;
FIG. 8 is a graph showing the breakdown voltage of a super-junction dual-SOI-LDMOS device having an extended drain structure and a conventional dual-SOI structure as a function of the concentration of a drift region, with a drift region length of 4 μm;
FIG. 9 is a plot of breakdown voltage and specific on-resistance as a function of drift region length for a super-junction dual SOI-LDMOS device having an extended drain structure and a conventional dual SOI structure;
fig. 10 is a cross-sectional view of fig. 1.
The semiconductor device comprises a 1-substrate, a 2-second oxygen-buried layer, a 3-semiconductor extension drain contact region, a 4-first semiconductor region, a 5-second semiconductor region, a 6-first oxygen-buried layer, a 7-semiconductor body contact region, an 8-semiconductor source region, a 9-semiconductor drain region, a 10-source metal, an 11-gate metal, a 12-gate oxide layer, a 13-drain metal, a 14-insulating dielectric layer, a 15-third semiconductor region and a 16-fourth semiconductor region.
Detailed Description
The present invention will now be described in more detail with reference to the drawings wherein preferred embodiments of the present invention are shown, and a method of fabricating a superjunction dual SOI-LDMOS device having an extended drain structure, it being understood that one skilled in the art can modify the invention as described herein while still achieving the advantageous effects of the invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.
Referring to fig. 1 and 10, a super junction dual-SOI-LDMOS device with an extended drain structure includes:
A substrate 1;
A second buried oxide layer 2 on the substrate 1;
a second SOI layer located on the second buried oxide layer 2, comprising:
A semiconductor region including a first semiconductor region 4 and a second semiconductor region 5 which are arranged in parallel and have different doping types; the first semiconductor region 4 is parallel to one lateral surface of the device transverse direction and is contacted with one lateral surface of the second semiconductor region 5 parallel to the device transverse direction;
a semiconductor extended drain contact region 3 which is parallel to one side of the device longitudinal direction and is in contact with one side of the semiconductor region parallel to the device longitudinal direction;
A first buried oxide layer 6 on the second SOI layer;
A first SOI layer on the first buried oxide layer 6, comprising a semiconductor body contact region 7, a semiconductor source region 8, a semiconductor drain region 9, and a drift region between the semiconductor body contact region 7 and the semiconductor drain region 9;
A semiconductor drain region 9 disposed adjacent to the semiconductor body contact region 7 with respect to the semiconductor source region 8; a semiconductor source region 8 is in contact with the semiconductor body contact region 7 on a side parallel to the longitudinal direction of the device;
the drift region comprises a third semiconductor region 15 and a fourth semiconductor region 16 arranged in parallel;
wherein the third semiconductor region 15 is parallel to one side of the device lateral direction and is in contact with one side of the fourth semiconductor region 16 parallel to the device lateral direction;
The third semiconductor region 15 is of the same doping type as the first semiconductor region 4; the doping type of the fourth semiconductor region 16 is the same as that of the second semiconductor region 5;
A drain metal 13 (corresponding to voltage V d), wherein a first part of the drain metal 13 is parallel to one side surface of the longitudinal direction of the device and is in contact with the first buried oxide layer 6, and the lower surface of the first part is in contact with the upper surface of the semiconductor extension drain contact region 3; a second portion of the drain metal 13 is in contact with the upper surface of the semiconductor drain region 9;
the first and second portions of the drain metal 13 are wired.
An insulating dielectric layer 14 interposed between the first portion and the second portion of the drain metal 13 and in contact with the semiconductor drain region 9;
A source metal 10 in contact with the upper surface of the semiconductor source region 8;
And a gate metal 11 (corresponding to voltage V g) forming a gap with the source metal 10, which is disposed on the gate oxide layer 12, the gate oxide layer 12 being in contact with the upper surfaces of the semiconductor body contact region 7, the semiconductor source region 8 and the drift region at the same time.
Wherein the first semiconductor region 4 is disposed directly below the fourth semiconductor region 16; the second semiconductor region 5 is disposed directly below the third semiconductor region 15.
The doping type of the first semiconductor region 4 is P-type or N-type. That is, when the doping type of the first semiconductor region 4 is P-type, the third semiconductor region 15 is P-type, the doping type of the second semiconductor region 5 is N-type, and the fourth semiconductor region 16 is N-type.
The doping concentration C1 of the first semiconductor region 4 is lower than the doping concentration C3 of the third semiconductor region 15;
The doping concentration C2 of the second semiconductor region 5 is lower than the doping concentration C4 of the fourth semiconductor region 16.
In a dual SOI LDMOS device, a concentration gradient, i.e., concentration difference, needs to be formed between the p-type semiconductor and the n-type semiconductor in order to achieve better electrical performance. Such concentration differences may allow electrons and holes to diffuse more easily in the device, thereby improving the efficiency and performance of the device. Meanwhile, the concentration difference can also reduce carrier recombination in the device, so that reverse leakage current is reduced. Thus, the concentration difference is one of the important factors that dual SOI-LDMOS devices can achieve high breakdown voltages.
A manufacturing method of a super junction double SOI-LDMOS device with an extended drain structure comprises the following steps:
step 1, growing an oxide layer on a substrate 1 to form a second buried oxide layer 2;
step 2, forming a semiconductor region and a semiconductor extension drain contact region 3 on the second buried oxide layer 2 by ion implantation;
Step 3, growing an oxide layer on the second SOI layer to form a first buried oxide layer 6;
Step 4, depositing oxide to form an insulating medium layer 14;
Step 5, etching oxide at a preset position;
And 6, performing ion implantation on the first oxygen-buried layer 6 to form a semiconductor source region 8, a semiconductor body contact region 7, a drift region and a semiconductor drain region 9 respectively.
And 7, growing an oxide layer on the semiconductor body contact region 7, the semiconductor source region 8 and the drift region to form a gate oxide layer 12.
Step 8, disposing the gate metal 11 on the gate oxide layer 12, disposing the source metal 10 on the semiconductor source region 8, disposing the second portion of the drain metal 13 on the semiconductor drain region 9, and disposing the first portion of the drain metal 13 on the semiconductor extended drain contact region 3.
To demonstrate the beneficial effects of embodiments of the present invention, FIGS. 2-7 analyze the structure of the present invention and the conventional structure from potential, impact ionization rate, and electric field.
Wherein the view in fig. 2 is a front view of the present device.
Fig. 2 and 3 show two-dimensional potential profiles of a super-junction dual-SOI-LDMOS device with an extended drain structure and a conventional dual-SOI structure, respectively. It can be seen from the figure that the potential lines of the conventional double SOI structure are concentrated at the drain electrode of the device, the capability of bearing voltage is limited, and the potential lines of the drift region of the structure are uniformly distributed in the drift region, and the whole drift region can uniformly bear the applied voltage, so that the breakdown voltage is higher.
Fig. 4 and 5 are impact ionization rate profiles for a super-junction dual-SOI-LDMOS device having an extended drain structure and a conventional dual-SOI structure, respectively. It can be seen from the figure that the highest point (i.e. the maximum value) of the impact ionization rate of the traditional structure is far higher than that of the structure of the invention, and the structure of the invention is more easy to break down, so that the pressure resistance of the structure of the invention is stronger.
Fig. 6 and 7 show three-dimensional electric field profiles of a super-junction dual-SOI-LDMOS device with an extended drain structure and a conventional dual-SOI structure, respectively. As can be seen from the figure, the electric field peak of the conventional structure is at the highest point of the impact ionization rate of the device, namely the drain end (drain metal 13) of the device, the electric field is not uniformly distributed, but the electric field of the structure of the invention is uniformly distributed, so that the device can bear higher voltage. In fig. 6 to 7, E is the electric field strength.
To demonstrate the beneficial effects of embodiments of the present invention, FIGS. 8-9 compare the structure of the present invention with that of a conventional structure.
Fig. 8 is a graph showing the breakdown voltage of the super-junction double-SOI-LDMOS device with an extended drain structure and the conventional double-SOI structure as a function of the drift region concentration for a drift region length (i.e., a dimension parallel to the device lateral direction) of 4 μm, and it can be seen from the graph that the breakdown voltage of the structure of the present invention is higher than that of the conventional structure due to the improved potential field distribution of the drift region when the device is turned off, and reaches a maximum value of 72V for a drift region concentration of 10 18cm-3.
Fig. 9 is a graph of breakdown voltage and specific on-resistance as a function of drift region length for a superjunction dual SOI-LDMOS device having an extended drain structure and a conventional dual SOI structure.
As can be seen from the left-hand axis of fig. 9, the inventive structure has a higher breakdown voltage than that of the conventional structure, which reaches a maximum of 72V at a drift region length of 4 μm and then remains unchanged, due to the improved potential field distribution of the drift region when the device is turned off, and reaches a maximum of 33V at a drift region length of 2 μm and then remains unchanged;
As can be seen from the right axis in fig. 9, the specific on-resistance of the structure of the present invention is lower than that of the conventional structure because the first and second semiconductor regions and the extended drain structure alternately arranged in the second SOI layer are utilized when the device is turned on, so that majority carriers are induced at the surface of the drift region of the first SOI layer.
Table 1 shows that the FOM values of the super-junction double SOI-LDMOS device with the extended drain structure and the conventional double SOI structure change along with the length of the drift region, and it can be seen from Table 1 that the FOM value of the structure of the invention reaches the maximum value of 23.23 MW.cm -2 when the length of the drift region is 3 μm, and the FOM value of the conventional structure reaches the maximum value of 5.3 MW.cm -2 when the length of the drift region is 1 μm, and decreases along with the increment of the length of the drift region, and the FOM value of the structure of the invention is improved by 338% compared with that of the conventional double SOI structure.
TABLE 1
| Drift region length/μm | FOM value/MW.cm of the inventive Structure -2 | FOM value/MW.cm of conventional Structure -2 |
| 1 | 7.4 | 5.3 |
| 2 | 18.51 | 4.94 |
| 3 | 23.23 | 3.42 |
| 4 | 22.17 | 2.71 |
| 5 | 18.83 | 2.27 |
| 6 | 16.2 | 1.95 |
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.
Claims (5)
1. A superjunction double-SOI-LDMOS device having an extended drain structure, comprising:
a substrate (1);
The second oxygen-buried layer (2) is positioned on the substrate (1);
a second SOI layer on the second buried oxide layer (2), comprising:
A semiconductor region comprising a first semiconductor region (4) and a second semiconductor region (5) arranged in parallel and having different doping types; the first semiconductor region (4) is parallel to one lateral surface of the device and is contacted with one lateral surface of the second semiconductor region (5) parallel to the device lateral direction;
A semiconductor extended drain contact region (3) parallel to one side of the device longitudinal direction and in contact with one side of the semiconductor region parallel to the device longitudinal direction;
A first buried oxide layer (6) on the second SOI layer;
The first SOI layer is positioned on the first oxygen-buried layer (6) and comprises a semiconductor body contact region (7), a semiconductor source region (8), a semiconductor drain region (9) and a drift region between the semiconductor body contact region (7) and the semiconductor drain region (9);
the semiconductor drain region (9) is arranged close to the semiconductor body contact region (7); a side surface of the semiconductor source region (8) parallel to the longitudinal direction of the device is contacted with the semiconductor body contact region (7);
the drift region comprises a third semiconductor region (15) and a fourth semiconductor region (16) arranged in parallel;
Wherein the third semiconductor region (15) is parallel to one lateral surface of the device transverse direction and is contacted with one lateral surface of the fourth semiconductor region (16) parallel to the device transverse direction;
the doping type of the third semiconductor region (15) is the same as that of the first semiconductor region (4); the doping type of the fourth semiconductor region (16) is the same as that of the second semiconductor region (5);
A drain metal (13), wherein a first part of the drain metal (13) is parallel to one side surface of the longitudinal direction of the device and is in contact with the first oxygen-buried layer (6), and the lower surface of the first part of the drain metal is in contact with the upper surface of the semiconductor extension drain contact region (3); a second portion of the drain metal (13) is in contact with the upper surface of the semiconductor drain region (9);
an insulating dielectric layer (14) interposed between the first portion and the second portion of the drain metal (13) and in contact with the semiconductor drain region (9);
A source metal (10) in contact with the upper surface of the semiconductor source region (8);
And a gate metal (11) forming a gap with the source metal (10), which is disposed on the gate oxide layer (12), the gate oxide layer (12) being simultaneously in contact with the upper surfaces of the semiconductor body contact region (7), the semiconductor source region (8) and the drift region.
2. The super-junction double-SOI-LDMOS device with extended drain structure of claim 1, wherein the first semiconductor region (4) is placed directly under a fourth semiconductor region (16); the second semiconductor region (5) is disposed directly below the third semiconductor region (15).
3. The super-junction double-SOI-LDMOS device with extended drain structure according to claim 1, wherein the doping type of the first semiconductor region (4) is P-type or N-type.
4. The super-junction double-SOI-LDMOS device with extended drain structure according to claim 1, wherein the doping concentration C1 of the first semiconductor region (4) is lower than the doping concentration C3 of the third semiconductor region (15);
the doping concentration C2 of the second semiconductor region (5) is lower than the doping concentration C4 of the fourth semiconductor region (16).
5. A method for manufacturing a super-junction double-SOI-LDMOS device with an extended drain structure according to any of claims 1 to 4, characterized in that it comprises the steps of:
Step 1, growing an oxide layer on a substrate (1) to form a second buried oxide layer (2);
step 2, forming a semiconductor region and a semiconductor extension drain contact region (3) on the second oxygen-buried layer (2) by ion implantation;
step 3, growing an oxide layer on the second SOI layer to form a first buried oxide layer (6);
Step 4, depositing oxide to form an insulating medium layer (14);
Step 5, etching oxide at a preset position;
Step 6, ion implantation is performed on the first oxygen-buried layer (6) to form a semiconductor source region (8), a semiconductor body contact region (7), a drift region and a semiconductor drain region (9) respectively;
step 7, growing an oxide layer on the semiconductor body contact region (7), the semiconductor source region (8) and the drift region to form a gate oxide layer (12);
Step 8, disposing a gate metal (11) on the gate oxide layer (12), disposing a source metal (10) on the semiconductor source region (8), disposing a second portion of a drain metal (13) on the semiconductor drain region (9), and disposing a first portion of the drain metal (13) on the semiconductor extended drain contact region (3).
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000133801A (en) * | 1998-10-27 | 2000-05-12 | Toshiba Corp | High breakdown voltage semiconductor element |
| CN101916780A (en) * | 2010-07-22 | 2010-12-15 | 中国科学院上海微***与信息技术研究所 | LDMOS device with multilayer super-junction structure |
| CN111293163A (en) * | 2018-12-06 | 2020-06-16 | 上海新微技术研发中心有限公司 | Lateral diffusion metal oxide semiconductor field effect transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP3944461B2 (en) * | 2002-03-27 | 2007-07-11 | 株式会社東芝 | Field effect transistor and its application device |
| US7023050B2 (en) * | 2003-07-11 | 2006-04-04 | Salama C Andre T | Super junction / resurf LDMOST (SJR-LDMOST) |
| US7476591B2 (en) * | 2006-10-13 | 2009-01-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lateral power MOSFET with high breakdown voltage and low on-resistance |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000133801A (en) * | 1998-10-27 | 2000-05-12 | Toshiba Corp | High breakdown voltage semiconductor element |
| CN101916780A (en) * | 2010-07-22 | 2010-12-15 | 中国科学院上海微***与信息技术研究所 | LDMOS device with multilayer super-junction structure |
| CN111293163A (en) * | 2018-12-06 | 2020-06-16 | 上海新微技术研发中心有限公司 | Lateral diffusion metal oxide semiconductor field effect transistor |
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