JP2006324432A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2006324432A
JP2006324432A JP2005145851A JP2005145851A JP2006324432A JP 2006324432 A JP2006324432 A JP 2006324432A JP 2005145851 A JP2005145851 A JP 2005145851A JP 2005145851 A JP2005145851 A JP 2005145851A JP 2006324432 A JP2006324432 A JP 2006324432A
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semiconductor device
impurity concentration
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JP4997715B2 (en
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Susumu Iwamoto
進 岩本
Kouta Takahashi
孝太 高橋
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Fuji Electric Co Ltd
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which comprises a fine strip parallel pn layer by a trench embedding method, in which an avalanche breakdown occurs in an active region earlier than a breakdown strength structure, and a tolerable amount of avalanche is high to provide breakdown strength characteristics with high reliability. <P>SOLUTION: This semiconductor device comprises a plurality of second conductive semiconductor epitaxial layers which are formed in a depth to a low resistive substrate layer, in a first conductive drift layer laminated on the first conductive low resistive substrate layer with the plane embedding a parallel trench of a fine strip shape; and the fine strip parallel pn layer which is composed of an aggregate of the first conductive semiconductor layer between the parallel trenches and the second conductive semiconductor epitaxial layers. An impurity concentration of the second conductive semiconductor epitaxial layer is 1.15 times that of the first conductive semiconductor layer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、ＭＯＳＦＥＴ（絶縁ゲート型電界効果トランジスタ）、ＩＧＢＴ（伝導度変調型ＭＯＳＦＥＴ）、バイポーラトンラジスタ等に適用可能で、高耐圧化と大電流容量化が可能な半導体装置およびその製造方法に関する。   The present invention is applicable to MOSFETs (insulated gate field effect transistors), IGBTs (conductivity modulation MOSFETs), bipolar ton transistors, and the like, and a semiconductor device capable of increasing the breakdown voltage and increasing the current capacity, and a method for manufacturing the same. About.

半導体基板の両主面間、すなわち基板の厚さ（縦）方向に主電流が流れる縦型半導体装置は、オン状態のときにドリフト電流が流れる方向と、オフ状態のときにｐｎ接合への逆バイアス電圧による空乏層が伸びる方向とが同じである。このため、通常のプレーナ型のｎチャネル縦型ＭＯＳＦＥＴ（絶縁ゲート型電界効果トランジスタ）では、オン状態のときに半導体基板の厚さ（縦）方向に流れる電流は、前記基板中で相対的に最も高抵抗のドリフト層の厚さによってオン抵抗が決まるので、ドリフト層を薄くすれば、ドリフト抵抗が低くなって縦型ＭＯＳＦＥＴの実質的なオン抵抗が下がり、ドリフト層を厚くすれば、オン抵抗は大きくなる。
その一方で、縦型ＭＯＳＦＥＴは、オフ状態でｐｎ主接合の逆バイアス電圧（耐圧）ににより拡がる空乏層幅を許容するドリフト層幅（厚さ）を必要とするので、高耐圧にするにはドリフト層をさらに厚くする必要がある。しかし、前述のようにドリフト層を厚くするとオン抵抗は大きくなり、損失が増加するので、同時に前記両特性を改良できないという問題を有することになる。この現象は、ＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）やバイポーラトランジスタやダイオード等の半導体装置においても同様に成立することが知られている。オン抵抗と耐圧間の前述のような関係をトレードオフ関係と称している。このようなトレードオフ関係を解消して両方の特性を同時に改善することは容易ではないが、改善への要望も強い。 A vertical semiconductor device in which a main current flows between both main surfaces of a semiconductor substrate, that is, in the thickness (vertical) direction of the substrate, has a direction in which a drift current flows in an on state and a reverse to a pn junction in an off state. The direction in which the depletion layer extends due to the bias voltage is the same. For this reason, in a normal planar type n-channel vertical MOSFET (insulated gate field effect transistor), the current flowing in the thickness (vertical) direction of the semiconductor substrate in the on state is relatively the largest in the substrate. Since the on-resistance is determined by the thickness of the high-resistance drift layer, if the drift layer is made thinner, the drift resistance is lowered and the substantial on-resistance of the vertical MOSFET is lowered, and if the drift layer is made thick, the on-resistance is growing.
On the other hand, the vertical MOSFET requires a drift layer width (thickness) that allows the depletion layer width to be expanded by the reverse bias voltage (breakdown voltage) of the pn main junction in the off state. It is necessary to make the drift layer thicker. However, as described above, when the drift layer is thickened, the on-resistance is increased and the loss is increased. Therefore, there is a problem in that both characteristics cannot be improved at the same time. This phenomenon is also known to hold in semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors), bipolar transistors and diodes. The above-described relationship between on-resistance and breakdown voltage is referred to as a trade-off relationship. It is not easy to eliminate such a trade-off relationship and improve both characteristics at the same time, but there is a strong demand for improvement.

上述したトレードオフ関係を解消する一案として、ドリフト層を、不純物濃度を高めた薄板状のｎ型半導体層とｐ型半導体層とを交互に繰り返し密着配置してなる並列ｐｎ接合集合体を電流経路に平行となるように複数並べた細条並列ｐｎ層により構成されるようにした超接合半導体装置が公知である。このような構造の超接合半導体装置は、オン状態では高不純物濃度の細条並列ｐｎ層により、低オン抵抗が得られ、オフ状態では、空乏層が、細条並列ｐｎ層の縦方向に伸びる各ｐｎ接合から細条の幅方向に容易に広がりきり、厚いドリフト層全体を容易に空乏化するため、高耐圧化を図ることができる。すなわち、この超接合半導体装置によれば、低オン抵抗と高耐圧の両特性を改善できるので、前記トレードオフ関係を解消できる。
従来、前述した細条並列ｐｎ層を備える前記超接合半導体装置の具体的な製造方法として、基板上へのｎ型半導体層のエピタキシャル成長とｐ型不純物の選択イオン注入を繰り返し行って細条並列ｐｎ層を形成する方法（以下、多段エピタキシャル成長法とする）が公知である（たとえば、特許文献１、特許文献２参照。）。また、別の製造方法として、ｎ型半導体層に並列トレンチを形成し、その並列トレンチをｐ型半導体のエピタキシャル成長層で埋めて細条並列ｐｎ層を形成する方法（以下、トレンチ埋め込み法とする）が提案されている（たとえば、特許文献３参照。）。 As a proposal for eliminating the trade-off relationship described above, a parallel pn junction assembly in which a drift layer is formed by alternately and closely arranging thin n-type semiconductor layers and p-type semiconductor layers with an increased impurity concentration is used as a current. A super-junction semiconductor device configured by a plurality of strip parallel pn layers arranged in parallel to a path is known. In the super junction semiconductor device having such a structure, a low on-resistance is obtained by the high impurity concentration strip parallel pn layer in the on state, and a depletion layer extends in the vertical direction of the strip parallel pn layer in the off state. Since each pn junction can easily spread in the width direction of the strip and the entire thick drift layer is easily depleted, a high breakdown voltage can be achieved. That is, according to this superjunction semiconductor device, both the low on-resistance and the high breakdown voltage characteristics can be improved, so that the trade-off relationship can be eliminated.
Conventionally, as a specific method for manufacturing the superjunction semiconductor device having the above-described strip parallel pn layer, the strip parallel pn is formed by repeatedly performing epitaxial growth of an n-type semiconductor layer on a substrate and selective ion implantation of p-type impurities. A method of forming a layer (hereinafter referred to as a multi-stage epitaxial growth method) is known (see, for example, Patent Document 1 and Patent Document 2). As another manufacturing method, a parallel trench is formed in an n-type semiconductor layer, and the parallel trench is filled with an epitaxial growth layer of a p-type semiconductor to form a strip parallel pn layer (hereinafter referred to as a trench filling method). Has been proposed (see, for example, Patent Document 3).

前記トレンチ埋め込み法は、前記多段エピタキシャル成長法よりもエピタキシャル成長回数が少ないので、コストを低く抑えることができるという利点がある。しかし、トレンチ埋め込み法で作製した超接合半導体装置では、耐圧を確保するために、活性領域だけでなくエッジ構造部に設けられる周辺耐圧構造についても、トレンチ埋め込み法で作製する必要があるので、従来の多段エピタキシャル成長法では可能であった活性領域と周辺耐圧構造とで、不純物濃度に差を設けて耐圧を向上させる構造または方法を採用することは容易ではない。
この点について、以下、詳細に説明する。以下の説明では、ＭＯＳＦＥＴは、すべてｎチャネル型とする。また、ドリフト層中の細条並列ｐｎ層は、基板の厚さ方向に薄板状に伸びる細条形状のｎ半導体層とｐ半導体層とが交互に面を接した並列形状（基板の表面側から見ると並列ストライプという言い方が適切）の集合体を有する。なお、本明細書では、細条並列ｐｎ層のｎ半導体層（または、ｐ半導体層）の深さ方向に伸びる方向を細条並列ｐｎ層のストライプに平行な方向と言い、それに直交する方向を細条並列ｐｎ層のストライプに垂直な方向と言うこととする。 The trench embedding method has an advantage that the cost can be reduced because the number of times of epitaxial growth is smaller than that of the multi-stage epitaxial growth method. However, in the superjunction semiconductor device manufactured by the trench embedding method, in order to ensure the withstand voltage, not only the active region but also the peripheral withstand voltage structure provided in the edge structure portion needs to be manufactured by the trench embedding method. It is not easy to adopt a structure or method for improving the breakdown voltage by providing a difference in impurity concentration between the active region and the peripheral breakdown voltage structure, which is possible in the multi-stage epitaxial growth method.
This point will be described in detail below. In the following description, the MOSFETs are all n-channel type. Further, the strip parallel pn layer in the drift layer has a parallel shape in which strip-shaped n semiconductor layers and p semiconductor layers extending in a thin plate shape in the thickness direction of the substrate alternately contact each other (from the surface side of the substrate). It has a collection of parallel stripes as appropriate. In this specification, the direction extending in the depth direction of the n semiconductor layer (or p semiconductor layer) of the strip parallel pn layer is referred to as a direction parallel to the stripe of the strip parallel pn layer, and the direction orthogonal thereto The direction is perpendicular to the stripes of the strip parallel pn layer.

下記特許文献１には、エッジ構造部の細条並列ｐｎ層において、活性領域よりも不純物濃度を低くしたり、ストライプのピッチを狭くしたり、ピッチを狭くするとともに不純物濃度を低くしたり、ピッチを広げるとともに不純物濃度を低くした構造が開示されている。さらに、特許文献１に開示された構造では、活性領域における細条並列ｐｎ層のｐ半導体層とｎ半導体層の総不純物量は互いに等しく、かつエッジ構造部、すなわち非活性領域における細条並列ｐｎ層のｐ半導体層とｎ半導体層の総不純物量も互いに等しい構造が示されている。
また、上記特許文献２には、エッジ構造部の細条並列ｐｎ層を上層部と下層部の２層に分割し、上層部の細条並列ｐｎ層についてのみ、不純物濃度を低くしたり、ストライプのピッチを狭くしたり、ピッチを狭くするとともに不純物濃度を低くしたり、ピッチを広げるとともに不純物濃度を低くした構造が開示されている。これら特許文献１および特許文献２に開示された超接合半導体装置は多段エピタキシャル成長法により作製されることができる。なぜなら、多段エピタキシャル成長法では、選択イオン注入時のドーズ量や、イオン打ち込み時の窓幅の比などを変えることによって、不純物濃度を変化させることができるので、エッジ構造部の細条並列ｐｎ層の不純物濃度だけを他に比べて相対的に低くすることは容易となるからである。 In Patent Document 1 below, in the strip parallel pn layer of the edge structure portion, the impurity concentration is made lower than that of the active region, the stripe pitch is made narrow, the pitch is made narrow and the impurity concentration is made low, And a structure in which the impurity concentration is lowered. Furthermore, in the structure disclosed in Patent Document 1, the total impurity amounts of the p semiconductor layer and the n semiconductor layer of the strip parallel pn layer in the active region are equal to each other, and the strip parallel pn in the edge structure portion, that is, the inactive region A structure in which the total impurity amounts of the p semiconductor layer and the n semiconductor layer of the layers are also equal to each other is shown.
Further, in Patent Document 2, the strip parallel pn layer of the edge structure portion is divided into two layers of an upper layer portion and a lower layer portion, and the impurity concentration is reduced or striped only for the upper strip parallel pn layer. A structure in which the pitch is narrowed, the pitch is narrowed and the impurity concentration is lowered, or the pitch is widened and the impurity concentration is lowered is disclosed. These superjunction semiconductor devices disclosed in Patent Document 1 and Patent Document 2 can be manufactured by a multistage epitaxial growth method. This is because in the multi-stage epitaxial growth method, the impurity concentration can be changed by changing the dose amount during selective ion implantation, the ratio of the window width during ion implantation, and the like. This is because it is easy to make only the impurity concentration relatively lower than others.

一般に、半導体装置において、安定した耐圧を確保するためには、必ず、周辺耐圧構造を設ける必要がある。前記特許文献１，２に記載の多段エピタキシャル法により前記安定した耐圧を確保する周辺耐圧構造を形成すると、コストがかかりすぎるという問題がある。そこで、本発明者らは、特許文献３に開示されていてコスト面では有利と思われるトレンチ埋め込み法により、特許文献１に開示されているような周辺耐圧構造を形成できるようにするための技術について検討した。その結果、活性領域と非活性領域の細条並列ｐｎ層の幅については、形成するトレンチの幅と配置間隔（ピッチ）を変えることで制御可能であるが、不純物濃度に差を設けることは一回の埋め込みでは不可能であり、埋め込み回数を増やすことはコスト的に問題がある。
特開２００１−２９８１９０号公報 特開２００３−２２４２７３号公報 特開２００１−１９６５７３号公報 Generally, in a semiconductor device, in order to ensure a stable breakdown voltage, it is always necessary to provide a peripheral breakdown voltage structure. If the peripheral withstand voltage structure that secures the stable withstand voltage is formed by the multistage epitaxial method described in Patent Documents 1 and 2, there is a problem that the cost is excessive. Therefore, the present inventors have disclosed a technique for forming a peripheral withstand voltage structure as disclosed in Patent Document 1 by a trench filling method disclosed in Patent Document 3 and considered to be advantageous in terms of cost. Was examined. As a result, the width of the strip parallel pn layer of the active region and the non-active region can be controlled by changing the width of the trench to be formed and the arrangement interval (pitch). It is impossible to embed once, and increasing the number of embeds is problematic in terms of cost.
JP 2001-298190 A JP 2003-224273 A JP 2001-196573 A

しかしながら、トレンチ幅の制御に関しても、非活性領域のトレンチ幅が過度に狭くなると、非活性領域のｐ半導体層の不純物濃度が低くなり過ぎるため、ｐ半導体層の外側に空乏層を広げる効果が弱くなってしまう。そのため、空乏層の伸びが悪く、耐圧を確保しにくいという不都合が生じる。また、非活性領域のトレンチ幅が過度に狭くなると、トレンチの形成が困難になるとともに、トレンチのアスペクト比が高くなり過ぎるため、エピタキシャル成長によりトレンチを埋め込むことが困難になるという新たな問題が発生する。
また、特許文献２に開示されているような周辺耐圧構造を、トレンチ埋め込み法で形成する技術について検討した結果、非活性領域の細条並列ｐｎ層を上下に二分した上層部のｐ半導体層およびｎ半導体層のみの不純物濃度を変えることは、１回のトレンチ形成と１回のエピタキシャル成長による埋め込みでは不可能である。これは、トレンチ形成前の基板濃度が一様であることと、トレンチ埋め込み時の濃度が一様になってしまうことが原因である。 However, regarding the control of the trench width, if the trench width in the inactive region becomes excessively narrow, the impurity concentration of the p semiconductor layer in the inactive region becomes too low, so the effect of spreading the depletion layer outside the p semiconductor layer is weak. turn into. For this reason, the depletion layer does not grow well, and it is difficult to ensure a withstand voltage. In addition, if the trench width of the inactive region becomes excessively narrow, it becomes difficult to form the trench, and the aspect ratio of the trench becomes too high, which causes a new problem that it becomes difficult to fill the trench by epitaxial growth. .
Further, as a result of examining a technique for forming a peripheral withstand voltage structure as disclosed in Patent Document 2 by a trench embedding method, an upper p semiconductor layer obtained by vertically dividing a strip parallel pn layer in an inactive region into an upper and lower parts and It is impossible to change the impurity concentration of only the n semiconductor layer by one trench formation and one epitaxial growth filling. This is because the substrate concentration before trench formation is uniform and the concentration at the time of trench filling is uniform.

本発明は、上述した事情に鑑みなされたものであり、本発明の目的は、ドリフト層にトレンチ埋め込み法により形成される細条並列ｐｎ層を活性領域と共に耐圧構造部にも備える半導体装置において、逆バイアスによる電界を緩和する耐圧構造部とすることにより、耐圧構造部よりも活性領域で先にアバランシェ降伏が発生し、アバランシェ耐量が高く、高信頼性の耐圧特性を有する半導体装置を提供することである。   The present invention has been made in view of the above-described circumstances, and an object of the present invention is a semiconductor device including a strip parallel pn layer formed in a drift layer by a trench embedding method as well as an active region in a breakdown voltage structure portion. By providing a withstand voltage structure that relaxes the electric field due to reverse bias, an avalanche breakdown occurs in the active region earlier than the withstand voltage structure, and a semiconductor device having high avalanche resistance and high reliability withstand voltage characteristics is provided. It is.

特許請求の範囲の請求項１記載の本発明によれば、前記発明の目的は、第１導電型の低抵抗基板層上に積層された第１導電型半導体層に、前記低抵抗基板層に達する深さに複数形成され平面が細条形状の並列トレンチと、該並列トレンチを埋める第２導電型半導体エピタキシャル層とを有し、前記並列トレンチ間の前記第１導電型半導体層と前記第２導電型半導体エピタキシャル層との集合体により細条並列ｐｎ層を構成してなる半導体装置において、前記第２導電型半導体エピタキシャル層の不純物濃度が前記第１導電型半導体層の不純物濃度よりも１．１５倍以上である半導体装置とすることにより、達成される。
特許請求の範囲の請求項２記載の本発明によれば、前記第２導電型半導体エピタキシャル層の不純物濃度が前記第１導電型半導体層の不純物濃度よりも１．１５倍以上、１．２４倍以下である特許請求の範囲の請求項１に記載の半導体装置とすることが好ましい。 According to the present invention as set forth in claim 1, the object of the invention is to provide a first conductive type semiconductor layer laminated on a first conductive type low resistance substrate layer, and to the low resistance substrate layer. A plurality of parallel trenches having a strip-like shape and a second conductivity type semiconductor epitaxial layer filling the parallel trenches, the first conductivity type semiconductor layer between the parallel trenches and the second In a semiconductor device in which a strip parallel pn layer is formed by an aggregate with a conductive semiconductor epitaxial layer, the impurity concentration of the second conductive semiconductor epitaxial layer is 1. more than the impurity concentration of the first conductive semiconductor layer. This is achieved by making the semiconductor device 15 times or more.
According to the second aspect of the present invention, the impurity concentration of the second conductive semiconductor epitaxial layer is 1.15 times or more and 1.24 times higher than the impurity concentration of the first conductive semiconductor layer. Preferably, the semiconductor device according to claim 1 is the following.

特許請求の範囲の請求項３記載の本発明によれば、第１導電型半導体層がエピタキシャル成長により形成される特許請求の範囲の請求項１または２記載の半導体装置とすることが望ましい。
特許請求の範囲の請求項４記載の本発明によれば、前記細条並列ｐｎ層が中心部に活性領域、該中心部を取り囲む外周部に耐圧構造部を備える特許請求の範囲の請求項１乃至３のいずれか一項に記載の半導体装置とすることが好適である。
特許請求の範囲の請求項５記載の本発明によれば、前記細条並列ｐｎ層の表面にゲートとソースを有するＭＯＳゲート構造を備え、前記第１導電型の低抵抗基板層をドレインとする特許請求の範囲の請求項４記載の半導体装置とすることがいっそう好ましい。
特許請求の範囲の請求項６記載の本発明によれば、第１導電型の低抵抗基板層上に第１導電型半導体エピタキシャル層を堆積形成し、該層の表面から前記低抵抗基板層に達する深さに平面が細条形状の並列トレンチを複数形成し、該並列トレンチを埋める第２導電型半導体エピタキシャル層を堆積させ、前記並列トレンチ間の第１導電型半導体エピタキシャル層と前記第２導電型半導体エピタキシャル層との集合体によりなる細条並列ｐｎ層を構成してなる半導体装置の製造方法において、前記第２導電型半導体エピタキシャル層の不純物濃度が前記第１導電型半導体エピタキシャル層の不純物濃度よりも１．１５倍以上にした半導体装置の製造方法とすることにより、前記発明の目的は達成される。 According to the third aspect of the present invention, it is desirable that the first conductivity type semiconductor layer be formed by epitaxial growth to be the semiconductor device according to the first or second aspect.
According to the present invention as set forth in claim 4, the strip parallel pn layer includes an active region in a central portion and a pressure-resistant structure portion in an outer peripheral portion surrounding the central portion. It is preferable to use the semiconductor device according to any one of Items 1 to 3.
According to the present invention as set forth in claim 5, a MOS gate structure having a gate and a source is provided on the surface of the strip parallel pn layer, and the low-resistance substrate layer of the first conductivity type is a drain. The semiconductor device according to claim 4 is more preferable.
According to the sixth aspect of the present invention, the first conductive type semiconductor epitaxial layer is deposited on the first conductive type low resistance substrate layer, and the surface of the layer is applied to the low resistance substrate layer. A plurality of parallel trenches having a strip-like shape are formed to reach the depth, a second conductivity type semiconductor epitaxial layer filling the parallel trenches is deposited, and the first conductivity type semiconductor epitaxial layer and the second conductivity between the parallel trenches are deposited. In the method of manufacturing a semiconductor device comprising a strip parallel pn layer composed of an aggregate with a type semiconductor epitaxial layer, the impurity concentration of the second conductive type semiconductor epitaxial layer is the impurity concentration of the first conductive type semiconductor epitaxial layer The object of the present invention is achieved by using a method for manufacturing a semiconductor device that is 1.15 times or more than that.

本発明によれば、ドリフト層にトレンチ埋め込み法により形成された細条並列ｐｎ層を活性領域と共に耐圧構造部にも備える半導体装置において、逆バイアスによる電界を緩和する耐圧構造部とすることにより、耐圧構造部よりも活性領域で先にアバランシェ降伏が発生し、アバランシェ耐量が高く、高信頼性の耐圧特性を有する半導体装置を提供することができる   According to the present invention, in a semiconductor device including a strip parallel pn layer formed in a drift layer by a trench embedding method in an active region as well as a withstand voltage structure portion, by forming a withstand voltage structure portion that relaxes an electric field due to a reverse bias, An avalanche breakdown occurs in the active region earlier than the breakdown voltage structure, and a semiconductor device having a high avalanche resistance and having a high breakdown voltage characteristic can be provided.

以下に添付図面を参照して、本発明の好適な実施例を詳細に説明する。以下の説明および添付図面において、ｎまたはｐを冠記した層や領域は、それぞれ電子または正孔が多数キャリアであることを意味する。また、ｎやｐに付す＋は、それぞれ同基板内の同導電型の層より相対的に高不純物濃度であることを表す。＋＋はさらに高濃度であることを表す。
なお、すべての添付図面において同様の構成には同一の符号を付し、重複する説明を省略する。また、以下の説明では、細条並列ｐｎ層のストライプに垂直な方向に伸びる辺に沿う部分を、単に「ストライプに垂直な部分」と表現し、細条並列ｐｎ層のストライプに平行な方向に伸びる辺に沿う部分を、単に「ストライプに平行な部分」と表現する。
（実施例１）
本発明の半導体装置にかかる最良の実施の形態として縦形ＭＯＳＦＥＴを挙げて実施例１として説明する。図１（ａ）は、活性領域及び耐圧構造部（非活性領域）を示す基板の部分平面図、図１（ｂ）は図１（ａ）中のＡ−Ａ線に沿って切断した半導体基板の断面図である。なお、図１（ａ）では活性領域及び耐圧構造部全体の四分の一を斜線部分で表し、また、見やすくするため、図１（ａ）では表面構造を除いた細条並列ｐｎ層のみを示している。ちなみに、図１（ｂ）では、その除いた表面構造を含めた断面図としている。 Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description and the accompanying drawings, the layers and regions with n or p are the meaning that electrons or holes are majority carriers, respectively. Further, + attached to n and p represents that the impurity concentration is relatively higher than that of the same conductivity type layer in the same substrate. ++ represents a higher concentration.
Note that the same reference numerals are given to the same components in all the attached drawings, and redundant description is omitted. Further, in the following description, a portion along a side extending in a direction perpendicular to the stripe of the strip parallel pn layer is simply expressed as a “portion perpendicular to the stripe”, and in a direction parallel to the stripe of the strip parallel pn layer. A portion along the extending side is simply expressed as “a portion parallel to the stripe”.
Example 1
As a best mode for carrying out the semiconductor device according to the present invention, a vertical MOSFET will be described as a first embodiment. FIG. 1A is a partial plan view of a substrate showing an active region and a breakdown voltage structure (inactive region), and FIG. 1B is a semiconductor substrate cut along line AA in FIG. FIG. In FIG. 1A, a quarter of the entire active region and breakdown voltage structure is represented by a hatched portion, and for the sake of clarity, only the strip parallel pn layer excluding the surface structure is shown in FIG. Show. Incidentally, FIG. 1B is a cross-sectional view including the removed surface structure.

本実施例１のｎチャネル縦形ＭＯＳＦＥＴは、基板裏側のドレイン電極１８が導電接触した低抵抗のｎ＋＋ドレイン層１１と、そのｎ＋＋ドレイン層１１上全面に積層され、ドリフト層となるｎ半導体エピタキシャル層とその表面からのエッチングにより形成される並列トレンチに埋め込まれた並列ｐ半導体エピタキシャル層２０ｂ、２２ｂと、このｐ半導体エピタキシャル層２０ｂと前記トレンチ間に残された並列ｎ半導体エピタキシャル層２０ａ、２２ａとの集合体から形成される細条並列ｐｎ層２０、２２を備え、この細条並列ｐｎ層２０、２２のうち、中心部の活性領域の細条並列ｐｎ層部分２２の表面層には、選択的に形成されるｐベース領域（ｐウェル）１３と、そのｐベース領域１３内の表面側に選択的に形成された高不純物濃度のｎ＋ソース領域１４と、該ｎ＋ソース領域１４と前記細条ｎ半導体エピタキシャル層２２ａ表面とに挟まれたｐベース領域１３の表面上にゲート絶縁膜１５を介して設けられたドープドポリシリコン等のゲート電極層１６と、表面側に設けられる電極間を絶縁するための層間絶縁膜１９に開けたコンタクト孔を介してｐベース領域１３及びｎ＋ソース領域１４に跨って導電接触するソース電極１７とからなる２重拡散型ＭＯＳゲート構造が形成され、前記中心部の活性領域２２を取り囲む外周に位置する耐圧構造部の細条並列ｐｎ層部分２０の表面上には、表面保護及び安定化のために、熱酸化膜（絶縁膜）２３が成膜されている。なお、前記ゲート電極層１６には図示しない部分で金属膜のゲート配線が導電接触している。また、ソース電極１７は層間絶縁膜１９を挟んでゲート電極層１６を覆い、酸化膜２３上に延長されており、耐圧構造部におけるフィールドプレートとしても機能している。 The n-channel vertical MOSFET according to the first embodiment has a low resistance n ++ drain layer 11 in conductive contact with a drain electrode 18 on the back side of the substrate, and an n semiconductor epitaxial layer which is stacked on the entire surface of the n ++ drain layer 11 and becomes a drift layer. A parallel p-semiconductor epitaxial layer 20b, 22b embedded in a parallel trench formed by etching from the layer and its surface, and a parallel n-semiconductor epitaxial layer 20a, 22a left between the p-semiconductor epitaxial layer 20b and the trench The parallel striped pn layers 20 and 22 formed from the aggregate of the thin strip parallel pn layers 20 and 22 are selected as the surface layer of the strip parallel pn layer portion 22 of the central active region. P base region (p well) 13 formed on the surface, and a high impurity selectively formed on the surface side in the p base region 13 And n + source region 14 of the concentration, provided via a gate insulating film 15 on the surface of the n + source region 14 and the strip n sandwiched between the semiconductor epitaxial layer 22a surface p base region 13 doped Conductive contact is made across the p base region 13 and the n + source region 14 through a contact hole opened in the interlayer insulating film 19 for insulating the gate electrode layer 16 such as polysilicon and the electrodes provided on the surface side. A double diffusion MOS gate structure composed of the source electrode 17 is formed, and on the surface of the strip parallel pn layer portion 20 of the breakdown voltage structure portion located on the outer periphery surrounding the active region 22 in the center portion, surface protection and A thermal oxide film (insulating film) 23 is formed for stabilization. The gate electrode layer 16 is in conductive contact with a gate wiring of a metal film at a portion not shown. Further, the source electrode 17 covers the gate electrode layer 16 with the interlayer insulating film 19 interposed therebetween, is extended on the oxide film 23, and also functions as a field plate in the breakdown voltage structure portion.

ドリフト層を構成する細条並列ｐｎ層２０、２２は、明確にするために再度説明すると、活性領域では、半導体基板の厚み方向に薄板状縦形の細条ｎドリフト電流路領域２２ａと基板の厚み方向に薄板状縦形のドリフトｐ型領域２２ｂとを交互に繰り返して細条並列ｐｎ層の集合体が形成されるようにした構造である。本実施例１では、細条ｎドリフト電流路領域２２ａは、その上端が基板表面に達し、その下端がｎ＋＋ドレイン層１１に接している。また、ドリフトｐ型領域２２ｂは、その上端がｐベース領域１３のウェル底面に接し、その下端がｎ＋＋ドレイン層１１に接している。また、本実施例１では、ドリフトｐ型領域２２ｂの不純物濃度が細条ｎドリフト電流路領域２２ａの不純物濃度より高くされていることが特徴のひとつである。なお、細条ｎドリフト電流路領域２２ａ及びドリフトｐ型領域２２ｂとの間に１つのｐｎ接合を有する部分（矢印Ｐ１）を更に薄い細条並列ｐｎ層でそれぞれ分割形成しても構わない。 The strip parallel pn layers 20 and 22 constituting the drift layer will be described again for the sake of clarity. In the active region, the strip-shaped vertical strip n drift current path region 22a in the thickness direction of the semiconductor substrate and the thickness of the substrate are formed. This is a structure in which thin plate-like vertical drift p-type regions 22b are alternately repeated in the direction to form an aggregate of strip parallel pn layers. In the first embodiment, the strip n drift current path region 22 a has an upper end that reaches the substrate surface and a lower end that is in contact with the n ++ drain layer 11. The drift p-type region 22 b has an upper end in contact with the well bottom surface of the p base region 13 and a lower end in contact with the n + + drain layer 11. In addition, the first embodiment is characterized in that the impurity concentration of the drift p-type region 22b is higher than the impurity concentration of the narrow n-drift current path region 22a. Note that a portion (arrow P1) having one pn junction between the strip n drift current path region 22a and the drift p-type region 22b may be divided and formed by a further thin strip parallel pn layer.

一方非活性領域である耐圧構造部（素子外周部）でも、前記と同様の形状を有する細条並列ｐｎ層が形成されている。さらに、活性領域と同様に耐圧構造部でも、ドリフトｐ型領域２０ｂの不純物濃度が細条ｎドリフト電流路領域２０ａの不純物濃度より高くされている。また、耐圧構造部の細条並列ｐｎ層２０のｐｎ繰り返しピッチ（矢印Ｐ２）は前記ピッチ（矢印Ｐ１）と同じであるが、耐圧構造部の不純物量を活性領域の不純物量よりも少なく、高抵抗とすることも耐圧構造部における電界集中の緩和の観点から好ましい。なお、耐圧構造部の細条並列ｐｎ層部分２０の薄板面は活性領域の細条並列ｐｎ層部分２２の薄板面と略平行となっているが、直交又は斜交していても構わない。
耐圧構造部の細条並列ｐｎ層部分２０の外側は、基板の厚み方向に配置される薄板状縦形のｎ型低抵抗チャネルストッパ領域２４が取り囲んでいるので、図１（ａ）に示すように、最外側のｐ型領域２０ｂの薄板面に接する２辺と、細条並列ｐｎ層２０外側端面２０Ｂに直交する２辺とを有する。またｎ型低抵抗チャネルストッパ領域２４は、上端がチャネルストッパ電極２５に接し、その下端がドレイン層１１に接し、同電位に接続されている。 On the other hand, a strip parallel pn layer having the same shape as described above is also formed in the breakdown voltage structure portion (element outer peripheral portion) which is an inactive region. Further, in the breakdown voltage structure as in the active region, the impurity concentration of the drift p-type region 20b is set higher than the impurity concentration of the narrow n drift current path region 20a. Further, the pn repetition pitch (arrow P2) of the strip parallel pn layer 20 of the breakdown voltage structure portion is the same as the pitch (arrow P1), but the impurity amount of the breakdown voltage structure portion is less than the impurity amount of the active region, A resistance is also preferable from the viewpoint of alleviating electric field concentration in the pressure-resistant structure. The thin plate surface of the strip parallel pn layer portion 20 of the breakdown voltage structure portion is substantially parallel to the thin plate surface of the strip parallel pn layer portion 22 of the active region, but may be orthogonal or oblique.
Since the outer side of the strip parallel pn layer portion 20 of the breakdown voltage structure portion is surrounded by a thin plate-like vertical n-type low resistance channel stopper region 24 arranged in the thickness direction of the substrate, as shown in FIG. And two sides in contact with the thin plate surface of the outermost p-type region 20b, and two sides orthogonal to the strip parallel pn layer 20 outer end surface 20B. The n-type low resistance channel stopper region 24 has an upper end in contact with the channel stopper electrode 25 and a lower end in contact with the drain layer 11 and is connected to the same potential.

次に本実施例１の動作について説明する。ゲート電極層１６に所定の正の電位を印加すると、ゲート電極層１６直下のｐベース領域１３の表面層に誘起されるｎ反転層を通ってソース領域１４から電子が細条ｎドリフト電流路領域２２ａに注入され、ｎ＋＋ドレイン層１１に達するとドレイン電極１８とソース電極１７との間が導通してオン状態となる。
ゲート電極層１６への正の電位を取り去ると、ｐベース領域１３の表面層に誘起される前記ｎ反転層が消滅し、ドレイン電極１８とソース電極１７との間の電流が遮断されるので、ＭＯＳＦＥＴはオフ状態となる。更に、このオフ状態の際、逆バイアス電圧（ドレインに正、ソースに負の電圧）が印加されると、ｐベース領域１３と細条ｎドリフト電流路領域２２ａとの間のｐｎ接合Ｊａからそれぞれｐベース領域１３と細条ｎドリフト電流路領域２２ａに空乏層が広がって空乏化すると共に、細条ドリフトｐ領域２２ｂはｐベース領域１３を介してソース電極１７に電気的に接続し、細条ｎドリフト電流路領域２２ａはｎ＋＋ドレイン層１１を介してドレイン電極１８に電気的に接続しているため、細条ドリフトｐ領域２２ｂと細条ｎドリフト電流路領域２２ａとの間のｐｎ接合Ｊｂからの空乏層が細条ドリフトｐ領域２２ｂと細条ｎドリフト電流路領域２２ａの双方に拡張するので、ドリフト層の空乏化が早まる。特に本実施例１では、前述のように、ドリフトｐ型領域２２ｂ、２２ｂの不純物濃度が細条ｎドリフト電流路領域２０ａ、２２ａの不純物濃度より所定の範囲で高くされているので、耐圧構造部での電界集中が活性領域よりも緩和される結果、活性領域でアバランシェ降伏が発生するようになり、耐圧の安定化、アバランシェ耐量の向上効果が得られるようになる。従って、活性化領域におけるドリフト層の細条並列ｐｎ層２２の高耐圧の信頼性が十分確保されるので、ドリフト層の不純物濃度を高く設定でき、大電流化も確保できる。 Next, the operation of the first embodiment will be described. When a predetermined positive potential is applied to the gate electrode layer 16, electrons pass from the source region 14 through the n inversion layer induced in the surface layer of the p base region 13 immediately below the gate electrode layer 16, and the strip n drift current path region When the n ++ drain layer 11 is implanted, the drain electrode 18 and the source electrode 17 are brought into conduction and turned on.
When the positive potential to the gate electrode layer 16 is removed, the n inversion layer induced in the surface layer of the p base region 13 disappears, and the current between the drain electrode 18 and the source electrode 17 is blocked. The MOSFET is turned off. Furthermore, when a reverse bias voltage (a positive voltage at the drain and a negative voltage at the source) is applied in the OFF state, the pn junction Ja between the p base region 13 and the strip n drift current path region 22a A depletion layer spreads in the p base region 13 and the strip n drift current path region 22a to be depleted, and the strip drift p region 22b is electrically connected to the source electrode 17 through the p base region 13, Since n drift current path region 22a is electrically connected to drain electrode 18 via n ++ drain layer 11, pn junction Jb between narrow drift p region 22b and narrow n drift current path region 22a. Since the depletion layer from is expanded to both the strip drift p region 22b and the strip n drift current path region 22a, the depletion of the drift layer is accelerated. In particular, in the first embodiment, as described above, the impurity concentration of the drift p-type regions 22b and 22b is set higher than the impurity concentration of the narrow n-drift current path regions 20a and 22a within a predetermined range. As a result, the avalanche breakdown occurs in the active region, and the effect of stabilizing the breakdown voltage and improving the avalanche resistance can be obtained. Therefore, since the high breakdown voltage reliability of the strip parallel pn layer 22 of the drift layer in the activation region is sufficiently ensured, the impurity concentration of the drift layer can be set high, and a large current can be secured.

本実施例１では活性領域と同様に耐圧構造部にも細条並列ｐｎ層部分２０が形成されている。この耐圧構造部のｐ型領域２０ｂのうち、活性領域の細条ドリフトｐ領域２２ｂから延長した領域２０ｂはｐベース領域１３を介してソース電極１７に電気的に接続し、細条ドリフトｐ領域２２ｂとは接続しないｐ型領域２０ｂは浮遊状態であって言わば深部ガードリングとして機能し、また耐圧構造部の各ｎ型領域２０ａはｎ＋＋ドレイン層１１を介してドレイン電極１８に電気的に接続しているため、耐圧構造部２０のｐｎ接合Ｊｂから拡張した空乏層によって、基板厚み全長に亘り概ね空乏化される。このため、表面ガードリング構造やフィールドプレート構造のように耐圧構造部２０の表面側を空乏化させるだけではなく、基板深部までも空乏化させることができるので、耐圧構造部２０の電界強度を大幅緩和でき、高耐圧を確保できる。それ故、超接合半導体素子の高耐圧化を実現できる。 In the first embodiment, the strip parallel pn layer portion 20 is formed in the breakdown voltage structure portion as well as the active region. Of the p-type region 20b of the breakdown voltage structure portion, the region 20b extending from the strip drift p region 22b of the active region is electrically connected to the source electrode 17 through the p base region 13, and the strip drift p region 22b. The p-type region 20b that is not connected to the floating region is in a floating state and functions as a deep guard ring, and each n-type region 20a of the breakdown voltage structure portion is electrically connected to the drain electrode 18 via the n ++ drain layer 11. Therefore, the depletion layer extended from the pn junction Jb of the breakdown voltage structure portion 20 is substantially depleted over the entire thickness of the substrate. For this reason, not only can the surface side of the pressure-resistant structure portion 20 be depleted as in the surface guard ring structure or the field plate structure, but also the substrate deep portion can be depleted, so that the electric field strength of the pressure-resistant structure portion 20 is greatly increased. It can be relaxed and high breakdown voltage can be secured. Therefore, a high breakdown voltage of the super junction semiconductor element can be realized.

特に、本実施例１では、耐圧構造部と活性領域共の細条並列ｐｎ層のうち、トレンチに埋め込まれたｐ型半導体エピタキシャル層の不純物濃度が、トレンチ形成前にドリフト層として形成されたｎ型半導体エピタキシャル層の不純物濃度よりも１．１５倍以上としたことに特徴がある。このようにすることにより、耐圧構造部での逆バイアス印加による電界集中を緩和することができ、非活性領域よりも活性領域で先にアバランシェ降伏を発生させることにより、高信頼性の耐圧特性を有する半導体装置を可能にする。
この点に関して行った実験について、下記図２、３、４を用いて説明する。図２は前記細条並列ｐｎ層について、ｐ半導体エピタキシャル層に対するｎ半導体エピタキシャル層の不純物濃度比と耐圧との関係を示す図である。図３は、図２の拡大図であり、図４は耐圧構造部の表面にフィールド酸化膜２３を介して負電荷（マイナスチャージ）の影響を受ける場合の、ｐ半導体エピタキシャル層に対するｎ半導体エピタキシャル層の不純物濃度比と耐圧との関係を示す図である。この場合、前記図２、３、４の縦軸の耐圧は、ドリフト層における活性領域（■で示す）と非活性領域（耐圧構造部）（●で示す）とで、それぞれアバランシェ降伏の発生する電圧（すなわち、半導体材料固有のバンドギャップ幅で決まるアバランシェ降伏を起こす臨界電界強度）を示し、耐圧の低い方の領域の耐圧が素子の耐圧を決定するので、この低い方の耐圧が高い方が良く、さらに、低い方のアバランシェ降伏の発生する領域が耐圧構造部よりも活性領域である方が電界の集中度が低くや熱の放散も良いので、アバランシェ耐量、耐圧の信頼性の点から好ましいことを前提としている。この観点から、図２を見ると、ｐ層濃度（ｐ半導体エピタキシャル層の不純物濃度）のｎ層濃度（ｎ半導体エピタキシャル層の不純物濃度）に対する比が１．１５未満では非活性領域（耐圧構造部）の耐圧で素子耐圧が決まるので、好ましくなく、前記不純物濃度比が１．１５以上で、図３の拡大図を見ると、活性領域の耐圧が非活性領域（耐圧構造部）の耐圧よりも低くなって好ましいことが判る。図４は前記不純物濃度比の上限を示す図であり、前記不純物濃度比が１．２５を超えると、非活性領域（耐圧構造部）の表面のフィールド酸化膜２３を介して影響を及ぼす負電荷（マイナスチャージ）によって空乏層がチャネルストッパ領域に達し、その近傍で電界集中が生じて耐圧が再び非活性領域（耐圧構造部）側で決まるようになり、本発明の目的である耐圧安定性向上の観点から外れることを示している。 In particular, in Example 1, the impurity concentration of the p-type semiconductor epitaxial layer embedded in the trench among the strip parallel pn layers of the breakdown voltage structure portion and the active region is n which is formed as a drift layer before the trench formation. It is characterized by being 1.15 times or more than the impurity concentration of the type semiconductor epitaxial layer. In this way, electric field concentration due to reverse bias application in the breakdown voltage structure can be mitigated, and by generating avalanche breakdown earlier in the active region than in the inactive region, a highly reliable breakdown voltage characteristic can be obtained. The semiconductor device which has is enabled.
Experiments conducted in this regard will be described with reference to FIGS. FIG. 2 is a diagram showing the relationship between the impurity concentration ratio of the n semiconductor epitaxial layer to the p semiconductor epitaxial layer and the breakdown voltage of the strip parallel pn layer. FIG. 3 is an enlarged view of FIG. 2, and FIG. 4 shows an n semiconductor epitaxial layer with respect to the p semiconductor epitaxial layer when the surface of the breakdown voltage structure is affected by a negative charge (minus charge) via the field oxide film 23. It is a figure which shows the relationship between the impurity concentration ratio of this, and a proof pressure. In this case, the breakdown voltage on the vertical axis in FIGS. 2, 3 and 4 causes avalanche breakdown in the active region (shown by ■) and inactive region (withstand voltage structure) (shown by ●) in the drift layer. Indicates the voltage (that is, the critical electric field strength that causes avalanche breakdown determined by the band gap width unique to the semiconductor material), and the breakdown voltage of the lower breakdown voltage region determines the breakdown voltage of the element. In addition, the region where the lower avalanche breakdown occurs is the active region rather than the breakdown voltage structure, which is preferable in terms of avalanche resistance and breakdown voltage reliability because the electric field concentration is low and heat dissipation is good. It is assumed that. From this point of view, referring to FIG. 2, when the ratio of the p layer concentration (impurity concentration of the p semiconductor epitaxial layer) to the n layer concentration (impurity concentration of the n semiconductor epitaxial layer) is less than 1.15, the inactive region (breakdown voltage structure portion) ) Is not preferable, and the impurity concentration ratio is 1.15 or more, and when the enlarged view of FIG. 3 is seen, the breakdown voltage of the active region is higher than the breakdown voltage of the inactive region (breakdown voltage structure portion). It turns out that it becomes low and preferable. FIG. 4 is a diagram showing the upper limit of the impurity concentration ratio. When the impurity concentration ratio exceeds 1.25, negative charges that influence through the field oxide film 23 on the surface of the inactive region (breakdown voltage structure portion). Due to (minus charge), the depletion layer reaches the channel stopper region, electric field concentration occurs in the vicinity thereof, and the breakdown voltage is determined again on the inactive region (breakdown voltage structure) side, which improves the breakdown voltage stability, which is the object of the present invention It shows that it is out of the point of view.

なお、この際、同時に耐圧構造部の細条並列ｐｎ層の不純物量を活性領域の細条並列ｐｎ層の不純物量よりも不純物量（不純物濃度）が少なく、高抵抗とすることも好ましい。
また本実施例１では、耐圧構造部の細条並列ｐｎ層２０の外周には薄板状縦形のｎ型低抵抗チャネルストッパ領域２４が配置されていることから、耐圧構造部の細条並列ｐｎ層２０の外側のｐｎ繰り返し端面（横断面）２０Ｂを覆っているので、ｐｎ接合縦断面がチップのダイシング面として露出せず、漏れ電流を抑制し、耐圧を確保する機能を有する。
次に、上記実施例１の製造方法を説明する。図５に示すように、ｎ＋＋ドレイン層１１として、不純物濃度２×１０１８ｃｍ−３のｎ型低抵抗半導体基板の（１００）面上にドリフト層として、厚さが約５０μｍで、不純物濃度は、６．０×１０１５ｃｍ−３程度のｎ型高抵抗のエピタキシャル成長層３１を積層する。 At this time, it is also preferable that the amount of impurities (impurity concentration) in the strip parallel pn layer of the breakdown voltage structure portion is smaller than the amount of impurities in the strip parallel pn layer of the active region, and the resistance is high.
In the first embodiment, since the thin plate-like vertical n-type low resistance channel stopper region 24 is disposed on the outer periphery of the strip parallel pn layer 20 of the breakdown voltage structure portion, the strip parallel pn layer of the breakdown voltage structure portion. Since the pn repeating end face (cross section) 20B outside 20 is covered, the pn junction longitudinal section is not exposed as the dicing face of the chip, and has a function of suppressing leakage current and ensuring a withstand voltage.
Next, the manufacturing method of Example 1 will be described. As shown in FIG. 5, the n ++ drain layer 11 has a thickness of about 50 μm as a drift layer on the (100) plane of an n-type low-resistance semiconductor substrate having an impurity concentration of 2 × 10 18 cm −3. Is an n-type high resistance epitaxial growth layer 31 of about 6.0 × 10 15 cm −3 .

ついで、ｎ型半導体エピタキシャル成長層３１の表面に、トレンチ形成用のエッチングマスクとして酸化膜（または窒化膜などの絶縁膜）３２を厚さ２．４μｍで形成する。
ついで、フォトリソグラフィーにより酸化膜３２のパターニングを行い、ストライプ状（細条）の酸化膜マスクパターンを形成する。酸化膜３２の開口幅をたとえば５μｍとし、かつマスク部の酸化膜３２の幅をたとえば５μｍとする。つまり、５μｍおきに５μｍ幅の平行なストライプ状の酸化膜マスクと開口部が並列に配置されるパターンとなる。
ついで、トレンチエッチングをよく知られたＲＩＥ法を用いて行い、図６に示すように、ｎ型半導体エピタキシャル成長層３１に、たとえば、約５０μｍの深さで、開口幅が５μｍのトレンチ３３を形成する。その際、形成されたトレンチ側面の面方位が、（０１０）面またはこれと等価な面となるように、トレンチ３３を形成する。 Next, an oxide film (or an insulating film such as a nitride film) 32 is formed on the surface of the n-type semiconductor epitaxial growth layer 31 with a thickness of 2.4 μm as an etching mask for forming a trench.
Next, the oxide film 32 is patterned by photolithography to form a striped (striped) oxide film mask pattern. The opening width of oxide film 32 is set to 5 μm, for example, and the width of oxide film 32 in the mask portion is set to 5 μm, for example. That is, a pattern is formed in which parallel stripe-shaped oxide film masks having a width of 5 μm and openings are arranged in parallel every 5 μm.
Next, trench etching is performed using a well-known RIE method, and as shown in FIG. 6, a trench 33 having a depth of about 50 μm and an opening width of 5 μm is formed in the n-type semiconductor epitaxial growth layer 31, for example. . At this time, the trench 33 is formed so that the surface orientation of the formed trench side surface is the (010) plane or a plane equivalent thereto.

ついで、図７に示すように、このような面方位を有するトレンチ３３の内部にボロンドープのｐ型半導体エピタキシャル成長層３４を埋め込む。ｐ型半導体エピタキシャル成長層３４の不純物濃度は、たとえば７．０×１０１５ｃｍ−３程度である。さらに、トレンチ形成後の酸化膜３２の表面よりも上になるまでｐ型エピタキシャル成長層３４を成長させる。その後、図８に示すように、ＣＭＰ（化学機械研磨）などの研磨工程により酸化膜３２をストップ膜としてｐ型エピタキシャル成長層３４を研摩する。
研磨を行う際には、まず、トレンチのマスクとした酸化膜３２を研磨ストッパとして利用して研磨を行い、酸化膜３２の表面よりも上まで成長したｐ型半導体エピタキシャル成長層３４部分を除去する。
ついで、図９に示すように、酸化膜３２をエッチングにより除去する。その後、図１０に示すように、表面のミラー研磨を行って、酸化膜３２の除去によりできた表面にできた凹凸をなくす。特に限定しないが、たとえば、研磨量は１．０μｍ程度である。これは、酸化膜３２を研磨ストッパとして研磨を行った後に残った酸化膜３２の厚さが０．５μｍ程度であるからである。したがって、最終的な細条並列ｐｎ層の深さ方向の長さは４９μｍ程度となる。 Next, as shown in FIG. 7, a boron-doped p-type semiconductor epitaxial growth layer 34 is embedded in the trench 33 having such a plane orientation. The impurity concentration of the p-type semiconductor epitaxial growth layer 34 is, for example, about 7.0 × 10 15 cm −3 . Further, the p-type epitaxial growth layer 34 is grown until it is above the surface of the oxide film 32 after the trench formation. Thereafter, as shown in FIG. 8, the p-type epitaxial growth layer 34 is polished by using a polishing process such as CMP (chemical mechanical polishing) with the oxide film 32 as a stop film.
When polishing, first, polishing is performed using the oxide film 32 as a trench mask as a polishing stopper, and the portion of the p-type semiconductor epitaxial growth layer 34 that has grown above the surface of the oxide film 32 is removed.
Next, as shown in FIG. 9, the oxide film 32 is removed by etching. Thereafter, as shown in FIG. 10, the surface is mirror-polished to remove the irregularities formed on the surface formed by removing the oxide film 32. Although not particularly limited, for example, the polishing amount is about 1.0 μm. This is because the thickness of the oxide film 32 remaining after polishing using the oxide film 32 as a polishing stopper is about 0.5 μm. Therefore, the length of the final strip parallel pn layer in the depth direction is about 49 μm.

このようにして、図１０に示すように、ｎ型半導体エピタキシャル成長層３１よりなるｎ半導体エピタクシャル層２と、ｐ型半導体エピタキシャル成長層３４よりなる細条並列ｐｎ層を有する超接合半導体用の半導体基板ができあがる。
この超接合半導体基板を用いて、ＭＯＳＦＥＴの素子表面構造や周辺耐圧構造およびドレイン電極などを形成する。なお、ＭＯＳＦＥＴの素子表面構造や周辺耐圧構造などを作製するプロセスについては、周知であるので、説明を省略する。
以上において、本発明は、上述した実施例に限らず、種々変更可能である。たとえば、厚さや幅などの寸法および濃度は一例であり、本発明はそれらの数値に限定されるものではない。また、細条並列ｐｎ層上に、ＭＯＳＦＥＴ以外の素子、たとえばＩＧＢＴやバイポーラトランジスタ等を作製してもよい。また、上述した実施例では、第１導電型をｎ型とし、第２導電型をｐ型としたが、本発明は第１導電型をｐ型とし、第２導電型をｎ型としても同様に成り立つ。 Thus, as shown in FIG. 10, a semiconductor substrate for a superjunction semiconductor having an n semiconductor epitaxial layer 2 made of an n type semiconductor epitaxial growth layer 31 and a strip parallel pn layer made of a p type semiconductor epitaxial growth layer 34 is obtained. It ’s done.
Using this super-junction semiconductor substrate, an element surface structure of MOSFET, a peripheral breakdown voltage structure, a drain electrode, and the like are formed. The process for fabricating the MOSFET element surface structure, peripheral breakdown voltage structure, and the like is well known and will not be described.
As described above, the present invention is not limited to the above-described embodiments, and various modifications can be made. For example, dimensions and concentrations such as thickness and width are examples, and the present invention is not limited to these numerical values. Further, an element other than a MOSFET, such as an IGBT or a bipolar transistor, may be formed on the strip parallel pn layer. In the above-described embodiments, the first conductivity type is n-type and the second conductivity type is p-type. However, the present invention is the same even if the first conductivity type is p-type and the second conductivity type is n-type. It holds.

以上のように、本発明は、大電力用半導体装置に有用であり、特に、細条並列ｐｎ層をドリフト層に有するＭＯＳＦＥＴやＩＧＢＴやバイポーラトランジスタ等の高耐圧化と大電流容量化を両立させることのできる半導体装置に適している。   As described above, the present invention is useful for high-power semiconductor devices, and in particular, achieves both high breakdown voltage and high current capacity for MOSFETs, IGBTs, bipolar transistors, etc. having a strip parallel pn layer as a drift layer. It is suitable for a semiconductor device that can be used.

本発明の実施例１の半導体装置にかかり、（ａ）は半導体装置の部分平面図、（ｂ）は（ａ）のＡ−Ａ線での部分断面図である。1A is a partial plan view of a semiconductor device according to Example 1 of the present invention, and FIG. 4B is a partial cross-sectional view taken along line AA in FIG. 本発明にかかる細条並列ｐｎ層の不純物濃度比と耐圧の関係図である。FIG. 6 is a diagram showing the relationship between the impurity concentration ratio of the strip parallel pn layer and the breakdown voltage according to the present invention. 図２の部分拡大図である。FIG. 3 is a partially enlarged view of FIG. 2. 本発明にかかり、耐圧構造部に負電荷の影響がある場合の不純物濃度比と耐圧の関係図である。FIG. 5 is a relationship diagram between an impurity concentration ratio and a breakdown voltage when the breakdown voltage structure is affected by a negative charge according to the present invention. 本発明の半導体装置の製造方法を示す半導体基板の製造工程段階図（その１）である。FIG. 6 is a first step of manufacturing a semiconductor substrate, illustrating a method for manufacturing a semiconductor device according to the present invention. 本発明の半導体装置の製造方法を示す半導体基板の製造工程段階図（その２）である。FIG. 6 is a second manufacturing process step diagram of a semiconductor substrate showing a method for manufacturing a semiconductor device of the present invention; 本発明の半導体装置の製造方法を示す半導体基板の製造工程段階図（その３）である。FIG. 6 is a step diagram (No. 3) for manufacturing a semiconductor substrate, illustrating the method for manufacturing a semiconductor device of the present invention; 本発明の半導体装置の製造方法を示す半導体基板の製造工程段階図（その４）である。FIG. 6 is a semiconductor substrate manufacturing process step diagram (Part 4) illustrating the method for manufacturing a semiconductor device of the present invention; 本発明の半導体装置の製造方法を示す半導体基板の製造工程段階図（その５）である。FIG. 6 is a step diagram (No. 5) for manufacturing a semiconductor substrate, illustrating the method for manufacturing a semiconductor device of the present invention; 本発明の半導体装置の製造方法を示す半導体基板の製造工程段階図（その６）である。FIG. 6 is a step diagram (No. 6) for manufacturing a semiconductor substrate, illustrating the method for manufacturing a semiconductor device according to the present invention;

符号の説明Explanation of symbols

１１ 第１導電型の低抵抗基板層（ｎ＋＋ドレイン層）
１３ ｐベース層
１４ ｎ＋ソース層
１５ ゲート絶縁膜
１６ ゲート電極
１７ ソース電極
１８ ドレイン電極
１９ 層間絶縁膜
２０ 耐圧構造部の細条並列ｐｎ層
２０ａ 第１導電型半導体層（ｎ型半導体エピタキシャル成長層）
２０ｂ 第２導電型半導体層（ｐ型半導体エピタキシャル成長層）
２２ 活性領域の細条並列ｐｎ層
２２ａ 第１導電型半導体層（ｎ型半導体エピタキシャル成長層）
２２ｂ 第２導電型半導体層（ｐ型半導体エピタキシャル成長層）
２３ フィールド酸化膜
２４ チャネルストッパ領域
２５ チャネルストッパ電極
３１ ドリフト層（第１導電型半導体層）
３２ マスク酸化膜
３３ トレンチ
３４ （ｐ型半導体エピタキシャル成長層） 11 Low resistance substrate layer of first conductivity type (n ++ drain layer)
13 p base layer 14 n + source layer 15 gate insulating film 16 gate electrode 17 source electrode 18 drain electrode 19 interlayer insulating film 20 strip parallel pn layer of breakdown voltage structure portion 20a first conductive type semiconductor layer (n-type semiconductor epitaxial growth layer)
20b Second conductivity type semiconductor layer (p-type semiconductor epitaxial growth layer)
22 Strip parallel pn layer of active region 22a First conductivity type semiconductor layer (n-type semiconductor epitaxial growth layer)
22b Second conductivity type semiconductor layer (p-type semiconductor epitaxial growth layer)
23 Field oxide film 24 Channel stopper region 25 Channel stopper electrode 31 Drift layer (first conductivity type semiconductor layer)
32 mask oxide film 33 trench 34 (p-type semiconductor epitaxial growth layer)

Claims (6)

第１導電型の低抵抗基板層上に積層された第１導電型半導体層に、前記低抵抗基板層に達する深さに複数形成され平面が細条形状の並列トレンチと、該並列トレンチを埋める第２導電型半導体エピタキシャル層とを有し、前記並列トレンチ間の第１導電型半導体層と前記第２導電型半導体エピタキシャル層との集合体により細条並列ｐｎ層を構成してなる半導体装置において、前記第２導電型半導体エピタキシャル層の不純物濃度が前記第１導電型半導体層の不純物濃度よりも１．１５倍以上であることを特徴とする半導体装置。 A plurality of first conductive type semiconductor layers stacked on the first conductive type low-resistance substrate layer are formed at a depth reaching the low-resistance substrate layer, and the parallel trenches having a strip-like shape are filled with the parallel trenches. In a semiconductor device comprising: a second conductive type semiconductor epitaxial layer, and a strip parallel pn layer configured by an aggregate of the first conductive type semiconductor layer and the second conductive type semiconductor epitaxial layer between the parallel trenches The semiconductor device is characterized in that the impurity concentration of the second conductive type semiconductor epitaxial layer is 1.15 times or more higher than the impurity concentration of the first conductive type semiconductor layer. 前記第２導電型半導体エピタキシャル層の不純物濃度が前記第１導電型半導体層の不純物濃度よりも１．１５倍以上、１．２４倍以下であることを特徴とする請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein an impurity concentration of the second conductivity type semiconductor epitaxial layer is 1.15 times or more and 1.24 times or less than an impurity concentration of the first conductivity type semiconductor layer. . 第１導電型半導体層がエピタキシャル成長により形成されることを特徴とする請求項１または２記載の半導体装置。 3. The semiconductor device according to claim 1, wherein the first conductivity type semiconductor layer is formed by epitaxial growth. 前記細条並列ｐｎ層が中心部に活性領域、該中心部を取り囲む外周部に耐圧構造部を備えることを特徴とする請求項１乃至３のいずれか一項に記載の半導体装置。 4. The semiconductor device according to claim 1, wherein the strip parallel pn layer includes an active region in a central portion and a pressure-resistant structure portion in an outer peripheral portion surrounding the central portion. 5. 前記細条並列ｐｎ層の表面にゲートとソースを有するＭＯＳゲート構造を備え、前記第１導電型の低抵抗基板層をドレインとすることを特徴とする請求項４記載の半導体装置。 5. The semiconductor device according to claim 4, further comprising a MOS gate structure having a gate and a source on a surface of the strip parallel pn layer, wherein the first conductive type low-resistance substrate layer is a drain. 第１導電型の低抵抗基板層上に第１導電型半導体エピタキシャル層を堆積形成し、該層の表面から前記低抵抗基板層に達する深さに平面が細条形状の並列トレンチを複数形成し、該並列トレンチを埋める第２導電型半導体エピタキシャル層を堆積させ、前記並列トレンチ間の第１導電型半導体エピタキシャル層と前記第２導電型半導体エピタキシャル層との集合体によりなる細条並列ｐｎ層を構成してなる半導体装置の製造方法において、前記第２導電型半導体エピタキシャル層の不純物濃度が前記第１導電型半導体エピタキシャル層の不純物濃度よりも１．１５倍以上にしたことを特徴とする半導体装置の製造方法。
A first conductive type semiconductor epitaxial layer is deposited and formed on the first conductive type low resistance substrate layer, and a plurality of parallel trenches having a strip shape in a plane extending from the surface of the layer to the low resistance substrate layer are formed. And depositing a second conductive type semiconductor epitaxial layer filling the parallel trench, and forming a strip parallel pn layer comprising an aggregate of the first conductive type semiconductor epitaxial layer and the second conductive type semiconductor epitaxial layer between the parallel trenches. In the semiconductor device manufacturing method, the semiconductor device is characterized in that the impurity concentration of the second conductive semiconductor epitaxial layer is 1.15 times or more higher than the impurity concentration of the first conductive semiconductor epitaxial layer. Manufacturing method.
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