IT8621918A0 - Circuito di ripasso per memoria dinamica utilizzante semiconduttori del tipo a gate array. - Google Patents

Circuito di ripasso per memoria dinamica utilizzante semiconduttori del tipo a gate array.

Info

Publication number: IT8621918A0
Authority: IT; Italy
Prior art keywords: gate array; dynamic memory; array type; type semiconductors; review circuit
Prior art date: 1985-10-18

Application number

IT8621918A

Other languages

English (en)

Other versions

IT1197359B (it

Inventor

Nataraj Bhadriraju

Original Assignee

Gte Communication Syst

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1985-10-18

Filing date

1986-10-07

Publication date

1986-10-07

1986-10-07 Application filed by Gte Communication Syst filed Critical Gte Communication Syst

1986-10-07 Publication of IT8621918A0 publication Critical patent/IT8621918A0/it

1988-11-30 Application granted granted Critical

1988-11-30 Publication of IT1197359B publication Critical patent/IT1197359B/it

Links

239000004065 semiconductor Substances 0.000 title 1

Classifications

- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

Engineering & Computer Science (AREA)
Microelectronics & Electronic Packaging (AREA)
Computer Hardware Design (AREA)
Dram (AREA)
Exchange Systems With Centralized Control (AREA)

IT21918/86A 1985-10-18 1986-10-07 Circuito di ripasso per memoria dinamica utilizzante semiconduttori del tipo a gate array IT1197359B (it)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
US06/789,214 US4754425A (en)	1985-10-18	1985-10-18	Dynamic random access memory refresh circuit selectively adapted to different clock frequencies

Publications (2)

Publication Number	Publication Date
IT8621918A0 true IT8621918A0 (it)	1986-10-07
IT1197359B IT1197359B (it)	1988-11-30

Family

ID=25146933

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
IT21918/86A IT1197359B (it)	1985-10-18	1986-10-07	Circuito di ripasso per memoria dinamica utilizzante semiconduttori del tipo a gate array

Country Status (4)

Country	Link
US (1)	US4754425A (it)
BE (1)	BE905611A (it)
CA (1)	CA1279730C (it)
IT (1)	IT1197359B (it)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4918645A (en) *	1987-09-17	1990-04-17	Wang Laboratories, Inc.	Computer bus having page mode memory access
JPH01124195A (ja) *	1987-11-09	1989-05-17	Sharp Corp	セルフリフレッシュ方式
US4887240A (en) *	1987-12-15	1989-12-12	National Semiconductor Corporation	Staggered refresh for dram array
GB8801472D0 (en) *	1988-01-22	1988-02-24	Int Computers Ltd	Dynamic random-access memory
JPH0276056A (ja) *	1988-09-13	1990-03-15	Toshiba Corp	情報処理装置
US6212089B1 (en)	1996-03-19	2001-04-03	Hitachi, Ltd.	Semiconductor memory device and defect remedying method thereof
KR0141495B1 (ko) *	1988-11-01	1998-07-15	미다 가쓰시게	반도체 기억장치 및 그 결함구제방법
US5142637A (en) *	1988-11-29	1992-08-25	Solbourne Computer, Inc.	Dynamic video RAM incorporating single clock random port control
USRE35680E (en) *	1988-11-29	1997-12-02	Matsushita Electric Industrial Co., Ltd.	Dynamic video RAM incorporating on chip vector/image mode line modification
JPH02260195A (ja) *	1989-03-30	1990-10-22	Mitsubishi Electric Corp	リフレッシュコントロール回路
JPH0390942A (ja) *	1989-09-01	1991-04-16	Oki Electric Ind Co Ltd	主記憶装置の制御方式
JPH04141886A (ja) *	1990-10-01	1992-05-15	Nec Corp	マイクロコンピュータ
US5077693A (en) *	1990-08-06	1991-12-31	Motorola, Inc.	Dynamic random access memory
JP3018498B2 (ja) *	1990-11-30	2000-03-13	日本電気株式会社	半導体記憶装置
US5325515A (en) *	1991-05-14	1994-06-28	Nec Electronics, Inc.	Single-component memory controller utilizing asynchronous state machines
US5598374A (en) *	1995-07-14	1997-01-28	Cirrus Logic, Inc.	Pipeland address memories, and systems and methods using the same
KR100372245B1 (ko) *	1995-08-24	2004-02-25	삼성전자주식회사	워드라인순차제어반도체메모리장치
US10373667B2 (en)	2013-08-28	2019-08-06	Hewlett Packard Enterprise Development Lp	Refresh rate adjust

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US3729722A (en) *	1971-09-17	1973-04-24	Gte Automatic Electric Lab Inc	Dynamic mode integrated circuit memory with self-initiating refresh means
US3760379A (en) *	1971-12-29	1973-09-18	Honeywell Inf Systems	Apparatus and method for memory refreshment control
JPS5255337A (en) *	1975-10-31	1977-05-06	Hitachi Ltd	Refresh control system
US4332008A (en) *	1976-03-09	1982-05-25	Zilog, Inc.	Microprocessor apparatus and method
US4249247A (en) *	1979-01-08	1981-02-03	Ncr Corporation	Refresh system for dynamic RAM memory
JPS58192148A (ja) *	1982-05-07	1983-11-09	Hitachi Ltd	演算処理装置
US4575826A (en) *	1984-02-27	1986-03-11	International Business Machines Corp.	Refresh generator system for a dynamic memory

1985
- 1985-10-18 US US06/789,214 patent/US4754425A/en not_active Expired - Fee Related
1986
- 1986-10-07 CA CA000519970A patent/CA1279730C/en not_active Expired - Fee Related
- 1986-10-07 IT IT21918/86A patent/IT1197359B/it active
- 1986-10-17 BE BE2/61072A patent/BE905611A/fr not_active IP Right Cessation

Also Published As

Publication number	Publication date
CA1279730C (en)	1991-01-29
BE905611A (fr)	1987-02-16
IT1197359B (it)	1988-11-30
US4754425A (en)	1988-06-28

Publication	Publication Date	Title
IT8621918A0 (it)	1986-10-07	Circuito di ripasso per memoria dinamica utilizzante semiconduttori del tipo a gate array.
DE3585711D1 (de)	1992-04-30	Halbleiterspeicheranordnung.
DE3687322D1 (de)	1993-02-04	Halbleiterspeicheranordnung.
DE3686994D1 (de)	1992-11-26	Halbleiterspeicher.
DE3671124D1 (de)	1990-06-13	Halbleiterspeicherzelle.
DE3583091D1 (de)	1991-07-11	Halbleiterspeicheranordnung.
DE3577944D1 (de)	1990-06-28	Halbleiterspeicheranordnung.
DE3582376D1 (de)	1991-05-08	Halbleiterspeicheranordnung.
DE3586377D1 (de)	1992-08-27	Halbleiterspeicheranordnung.
DE3680562D1 (de)	1991-09-05	Halbleiterspeicheranordnung.
DE3576236D1 (de)	1990-04-05	Halbleiterspeicheranordnung.
DE3577367D1 (de)	1990-05-31	Halbleiterspeicheranordnung.
DE3586556D1 (de)	1992-10-01	Halbleiterspeicheranordnung.
DE3575225D1 (de)	1990-02-08	Halbleiterspeicheranordnung.
DE3580993D1 (de)	1991-02-07	Halbleiterspeicheranordnung.
IT8621919A0 (it)	1986-10-07	Circuito di memoria ad accesso casuale a sovrapposizione utilizzante semiconduttori del tipo a gate array.
DE3686144D1 (de)	1992-08-27	Nichtfluechtiger halbleiterspeicher.
DE3576754D1 (de)	1990-04-26	Halbleiterspeicheranordnung.
DE3582960D1 (de)	1991-07-04	Halbleiterspeicheranordnung.
DE3578254D1 (de)	1990-07-19	Halbleiterspeicheranordnung.
DE3586675D1 (de)	1992-10-29	Halbleiterspeicheranordnung.
DE3587457D1 (de)	1993-08-19	Halbleiterspeichereinrichtung.
DE3687284D1 (de)	1993-01-28	Halbleiterspeicheranordnung.
DE3683783D1 (de)	1992-03-19	Halbleiterspeicheranordnung.
DE3682346D1 (de)	1991-12-12	Halbleiterspeicheranordnung.