IL73562A - Flat package for integrated circuit memory chips - Google Patents

Flat package for integrated circuit memory chips

Info

Publication number
IL73562A
IL73562A IL73562A IL7356284A IL73562A IL 73562 A IL73562 A IL 73562A IL 73562 A IL73562 A IL 73562A IL 7356284 A IL7356284 A IL 7356284A IL 73562 A IL73562 A IL 73562A
Authority
IL
Israel
Prior art keywords
integrated circuit
flat package
circuit board
printed circuit
circuit memory
Prior art date
Application number
IL73562A
Other languages
English (en)
Other versions
IL73562A0 (en
Original Assignee
Hughes Aircraft Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hughes Aircraft Co filed Critical Hughes Aircraft Co
Publication of IL73562A0 publication Critical patent/IL73562A0/xx
Publication of IL73562A publication Critical patent/IL73562A/xx

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Credit Cards Or The Like (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
IL73562A 1983-12-28 1984-11-20 Flat package for integrated circuit memory chips IL73562A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US56636483A 1983-12-28 1983-12-28

Publications (2)

Publication Number Publication Date
IL73562A0 IL73562A0 (en) 1985-02-28
IL73562A true IL73562A (en) 1988-07-31

Family

ID=24262576

Family Applications (1)

Application Number Title Priority Date Filing Date
IL73562A IL73562A (en) 1983-12-28 1984-11-20 Flat package for integrated circuit memory chips

Country Status (9)

Country Link
EP (1) EP0167538B1 (xx)
JP (1) JPS61500879A (xx)
KR (1) KR920007209B1 (xx)
AU (1) AU568416B2 (xx)
CA (1) CA1232082A (xx)
DE (1) DE3476297D1 (xx)
ES (1) ES295772Y (xx)
IL (1) IL73562A (xx)
WO (1) WO1985002941A1 (xx)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4676571A (en) * 1985-07-23 1987-06-30 Thomas & Betts Corporation Leaded chip carrier connector
GB2190555B (en) * 1986-05-03 1990-03-28 Burr Brown Ltd Surface mounted single package data acquisition system
US4961633A (en) * 1988-02-22 1990-10-09 Xerox Corporation VLSI optimized modulator
EP0538010A3 (en) * 1991-10-17 1993-05-19 Fujitsu Limited Semiconductor package, a holder, a method of production and testing for the same
KR100218291B1 (ko) * 1991-12-11 1999-09-01 구본준 세라믹 패들을 이용한 반도체 패키지 및 그 제작방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5471572A (en) * 1977-11-18 1979-06-08 Fujitsu Ltd Semiconductor device
NL8020334A (xx) * 1980-02-12 1982-01-04 Mostek Corporation Te Carrollton, Texas, Ver. St. V. Am.
US4296456A (en) * 1980-06-02 1981-10-20 Burroughs Corporation Electronic package for high density integrated circuits
JPS5923044Y2 (ja) * 1980-08-28 1984-07-10 栗山ゴム株式会社 覆工板における着脱調節式ストツパ−装置
US4371912A (en) * 1980-10-01 1983-02-01 Motorola, Inc. Method of mounting interrelated components

Also Published As

Publication number Publication date
AU3509084A (en) 1985-07-12
IL73562A0 (en) 1985-02-28
EP0167538B1 (en) 1989-01-18
KR850005150A (ko) 1985-08-21
DE3476297D1 (en) 1989-02-23
CA1232082A (en) 1988-01-26
WO1985002941A1 (en) 1985-07-04
AU568416B2 (en) 1987-12-24
EP0167538A1 (en) 1986-01-15
JPS61500879A (ja) 1986-05-01
ES295772U (es) 1987-11-01
KR920007209B1 (ko) 1992-08-27
ES295772Y (es) 1988-05-16

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Legal Events

Date Code Title Description
KB Patent renewed
HC Change of name of proprietor(s)
RH1 Patent not in force