IE50350B1

IE50350B1 - Monolithic integrated cmos circuit

Info

Publication number: IE50350B1
Application number: IE1530/80A
Authority: IE
Original assignee: Itt
Priority date: 1979-07-24
Filing date: 1980-07-23
Publication date: 1986-04-02
Also published as: FR2462025B1; DE2929869A1; IT8023632A0; GB2054955A; DE2929869C2; JPS5618459A; IE801530L; IT1193544B; FR2462025A1; GB2054955B; IT8023632A1

Abstract

In an integrated CMOS circuit including an adjacently disposed complementary pair of transistors, wherein one transistor is formed in an island of p-type semiconductor material in an n-type substrate suppression of the four layer thyristor effect appearing over the n-channel- source/p-island/n-substrate/p-channel source line of a CMOS inverter stage, which may cause destruction of the CMOS circuit, is prevented by the provision of a Schottky barrier contact (3) attached to the p-island (2) and connected to the transistor drain zones (5, 6). This contact has a lower threshold voltage than the pn-junction (7) between the p-island and the n drain zone (5). A further Schottky barrier contact (4) may be attached to the substrate (1) and connected to the transistor drain zones (5, 6).

Description

The invention relates to monolithic integrated CMOS circuits.

It has been noticed on monolithic integrated CMOS circuits that upon application of very steep voltage or interference pulses, a short circuit can occur which is likely to cause destruction. This phenomenon is noticed above all in the case of CMOS circuits including gate electrodes of aluminium with a high threshold voltage, and which are intended to be operated at high supply voltages.

It has been assumed that this was due to the overlap capacitancesbetween gate electrodes and the drain regions. In fact, in the case of the CMOS-inverter, the gate electrodes and the drain electrodes of the n-channel and of the p-channel transistor are in connection with one another via evaporated aluminium conductor patterns. During the switching process, therefore, a portion of the voltage variation at the gate electrode is transferred by the overlap capacitance of the gate electrode, capacitively to the drain region of the transistors.

An infinitely steep voltage steep ΔίΙθ at the gate electrode, therefore, causes on the drain electrode the voltage variation iUD * iUDroax = iUG ' /Ck Wherein C- is the overlap capacitance between the gate electrode and 2θ the drain region, and Ck is the entire nodal capacitance on the drain side including C.

S03S0 When considering now the case where the gate potential jumps from its most positive to its most negative value then, owing to a capacitive voltage division, the gate potential of the n-channel transistor will jump from to - aUd.

Considering that the island-shaped area in the stationary state is everywhere applied to zero, there is caused subsequently to the voltage step, via the drain junction, the voltage drop ΔΐΙθ which, according to one calculation, may amount to 2 V. The drain region becomes negative with respect to the island-shaped area and starts to draw a forward current when UD 0.7 V, that is, higher than the threshold voltage of the drain-pn-junction. When this is the case, a forward current will flow via this pn-junction and, as is well known, will lead to a charge carrier injection above all into the high ohmic side, that is, into the island-shaped area adjacent to the drain-pn-junction. Since the pn-juhction biased in the reverse direction is positioned in the close proximity between the island-shaped area and the substrate, said pn-junction will act like a collector junction upon the electrons injected by the drain region into tne p-doped island-shaped area. At a sufficiently strong injection, the voltage then breaks down across the pn-junction between the islandshaped area and the substrate. The latter loses its barrier effect and thus causes the switching through of the four-layer structure n-channel-source/p-island/n-substrate/p-channel-source region, with this generally being referred to as the thyristor effect.

The invention starts out from this recognition.

Decisive for the setting up of the thyristor effect is the condition AUnX0.7V.

L) λζ υθ will in practice, not quite reach its theoretical maximum value 5 *UDmax = iUG · Cu'/Ck because the resulting potential difference between the drain region and the source region of the n-channel field-effect transistor immediately starts to compensate itself by the current flow through the transistor which is at present still in the conducting state, with the parts source and drain being changed owing to the potential conditions during this compensating phase.

When ΔΐΙρ has not exceeded during this phase the critical value necessary for the firing, i.e. then the thyristor effect will not appear and the switching operation is performed normally; the p-channel transistor is rendered conductive, the n-channel transistor is rendered non-conductive and the drain potential (at the output of the inverter) reaches its most positive value Ug.

Of course, this thyristor effect can also be suppressed by a slower driving and applying flat voltage edges to the gate electrodes, by a highly resistive design of the driving stage (small W/L relationships), by enlarging the nodal capacity C^, for example, by enlarging the diffused drain region areas, or else, also by reducing the injection-effect drain region-island-substrate, though not without further ado and not without causing further drawbacks, such as a sacrifice in speed.

According to one aspect of the invention there is provided a CMOS integrated circuit, including an adjacently disposed complementary pair of transistors, wherein one transistor is formed in an island of semiconductor material of opposite conductivity type to the substrate, and wherein the drain of each said transistor is coupled to a Schottky barrier contact provided on said island.

According to another aspect of the invention there is provided an integrated circuit, including a pair of complementary insulated-gate field-effect transistors with the source region and the drain region of the one field-effect transistor being arranged superficially in an island-shaped area of the second conductivity type inserted into the surface side of a semiconducting substrate of the first conductivity type, with the source region as well as the drain region of the other field-effect transistor being Inserted into the surface side of the substrate and a connection between the two gate electrodes of the two field-effect transistors to which the input signal is applied, wherein the island-shaped area has a Schottky barrier contact having a lower threshold voltage than the pn-junction between said island-shaped area and the drain region of the field-effect transistor arranged within said island-shaped area and the drain region of the field-effect transistor is arranged within said island-shaped area, and wherein said Schottky barrier contact is in contact with the connection between the two drain regions.

In the case of a monolithic integrated CMOS circuit embedded in a silicon substrate it is possible to use, e.g. an Al-Si-contact which prevents the potential of the drain region from being capacitively lowered below that of the p-1 si and by more than the Schottky threshold 350 voltage. However, it is also possible to use other metals for establishing the Schottky barrier contact as is known, for example, from the technical journal Solid-State Electronics Vol. 14 (1971), pp. 71 to 75 and IEEE Transactions on Electron Devices Vol. ED-16, No. 1 (Jan. 1969) pp. 58 to 63. In this way it is safeguarded that the threshold voltage (threshold voltage in the forward direction) of the Schottky barrier contact remains below that of a pn-junction.

Since the Schottky threshold voltage is lower than that of the pnjunction of the drain region, the current not consisting of minority charge carriers and flowing across the Schottky barrier contact, leads to a discharge on the drain side, thus preventing a forward current flow with an injection via the pn-junction of the drain region.

Analogously it is also possible to provide a Schottky barrier contact between the drain region of the p-channel transistor and the substrate.

In many cases, however, one Schottky barrier contact on the side of the n-channel field-effect transistor will be sufficient, because there the danger of an injection into the pn-junction between the island-shaped area and the drain region is greater (higher a) than if it were to extend from the drain region of the p-channel field-effect transistor..

Embodiments of the invention will now be described with reference to Figures 1 to 4 of the accompanying drawings, in which: Figure 1 partly in a cross-sectional view taken almost vertically through a plate-shaped substrate, shows a conventional monolithic integrated CMOS-inverter circuit.

Figure 2 shows three equivalent circuit diagrams relating to the current path of the potential from zero to Ug extending via the islandshaped area and the substrate, S0350 Figure 3 shows a monolithic integrated CMOS inverter circuit including a Schottky barrier contact, and Figure 4 shows the two equivalent circuit diagrams relating to the Schottky barrier diodes on both the p-doped island-shaped area and the n-substrate.

Figure 1, in a sectional view, shows a monolithic integrated CMOS circuit, connected as an inverter. For establishing an n-channel fieldeffect transistor, an island-shaped p-conducting area 2 has been let into an n-type substrate; this can be carried out in the conventional way by employing a planar diffusion process. Let into this area 2 are the drain region 5 and the source region 10, whereas next to the area 2 forming a pn-junction 7 with the substrate 1, the drain region 6 and the source region 9 of the p-channel field-effect transistor are produced by planar diffusion. The input signal is applied at Ug to the connection between the two gate electrodes 11 and 12. The power supply with Ug>0 is applied between the substrate and the source region 9 on one hand, and the island-shaped area 2 at zero potential on the other hand.

Figure 2 shows the equivalent circuit diagram of Figure 1 including the three pn-diodes between the respective regions 1, 2, 6 and 10, the reference numerals of which being attached to the connections extending between the pn-diodes. Figure 2a relates to the ideal case where 0D Figure 2b relates to the case where the thyristor is fired by the parasitic pn-transistor, with the firing being effected through the drain region 5, which, so to speak, is to be considered as an auxiliary emitter region of a thyristor having the following succession of regions: source region 10/island-shaped area 2/substrate 1/source region 9. Accordingly, the drain region 5 is to be looked upon as the emitter zone of a parasitic equivalent circuit diagram transistor Tl to which there is temporarily applied a voltage UQ = aUq <-0.7 V.

Figure 2c refers to the case where a thyristor is filed by a parasitic pnp-transistor T2 using the drain region 6 as the emitter region. To this there is applied, for the firing the voltage UD = UB + iUD >UB + °·7 V provided that, as usual, silicon is used as the semiconducting material.

Figure 3 is a sectional view corresponding to Figure 1, illustrating a monolithic integrated CMOS-circuit employing a Schottky barrier contact 3 or 4 connected to the drain region 5 of the n-channel field-effect transistor or to the drain region 6 of the p-channel field-effect transistor respectively. In most cases, however, the Schottky barrier contact 4 on the substrate 2 may be omitted, because normally the drain region 5 of the n-channel field-effect transistor will be lying much closer to the pn-junction 7 acting as the collector junction of the aforementioned thyristor, i.e. between the island 2 and the substrate 1, than the drain region 6 of the p-channel field-effect transistor.

Figure 4a shows the equivalent circuit diagram relating to the Schottky barrier contact 3 on the island-shaped area 2, with a parasitic transistor Tl and the drain region 5 becoming effective, while Figure 4b shows the equivalent circuit diagram relating to the case where the Schottky barrier contact 4 is arranged on the substrate 1 with the parasitic transistor T2 respectively.

Claims

1. A CMOS integrated circuit, including an adjacently disposed complementary pair of transistors, wherein one transistor is formed in an island of semiconductor material of opposite conductivity type to the substrate, and wherein the drain of each said transistor is coupled to a Schottky barrier contact provided on said island.

2. An integrated circuit, including a pair of complementary insulatedgate field-effect transistors with the source region and the drain region of the one field-effect transistor being arranged superficially in an islandshaped area of the second conductivity type inserted into the surface side of a semiconducting substrate of the first conductivity type, with the source region as well as the drain region of the other field-effect transistor being inserted into the surface side of the substrate and a connection between the two gate electrodes of the two field-effect transistors to which the input signal is applied, wherein the island-shaped area has a Schottky barrier contact, having a lower threshold voltage than the pn-junction between said island-shaped area and the drain region of the field effect transistor, arranged within said island-shaped area, and wherein said Schottky barrier contact is connected with the connection between the two drain regions.

3. An integrated circuit as claimed in claim 2, wherein the substrate has a further Schottky barrier contact having a lower threshold voltage than the pn-junction between said drain region of the field-effect transistor arranged in the substrate, and said substrate, and that said further Schottky barrier contact is in contact with the connection between said two drain regions

4. An integrated circuit substantially as described herein with reference to Figure 3 and 4 of the accompanying drawings.

5. A method of four layer thyristor suppression in a CMOS integrated circuit, which method is substantially as described herein with reference to Figures 3 and 4 of the accompanying drawings.