GB2054955A - Monolithic integrated CMOS circuit - Google Patents
Monolithic integrated CMOS circuit Download PDFInfo
- Publication number
- GB2054955A GB2054955A GB8020110A GB8020110A GB2054955A GB 2054955 A GB2054955 A GB 2054955A GB 8020110 A GB8020110 A GB 8020110A GB 8020110 A GB8020110 A GB 8020110A GB 2054955 A GB2054955 A GB 2054955A
- Authority
- GB
- United Kingdom
- Prior art keywords
- island
- substrate
- schottky barrier
- drain
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 230000004888 barrier function Effects 0.000 claims abstract description 22
- 230000000295 complement effect Effects 0.000 claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims abstract description 3
- 230000001629 suppression Effects 0.000 claims abstract 2
- 230000005669 field effect Effects 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 6
- 230000006378 damage Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 5
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 238000010304 firing Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
- H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
In an integrated CMOS circuit including an adjacently disposed complementary pair of transistors, wherein one transistor is formed in an island of p-type semiconductor material in an n-type substrate suppression of the four layer thyristor effect appearing over the n-channel- source/p-island/n-substrate/p-channel source line of a CMOS inverter stage, which may cause destruction of the CMOS circuit, is prevented by the provision of a Schottky barrier contact (3) attached to the p-island (2) and connected to the transistor drain zones (5, 6). This contact has a lower threshold voltage than the pn-junction (7) between the p-island and the n drain zone (5). A further Schottky barrier contact (4) may be attached to the substrate (1) and connected to the transistor drain zones (5, 6). <IMAGE>
Description
SPECIFICATION
Monolithic integrated CMOS circuit
The invention relates to monolithic integrated
CMOS circuits.
It has been noticed on monolithic integrated
CMOS circuits that upon application of very steep voltage or interference pulses, a short circuit can occur which is likely to cause destruction. This phenomenon is noticed above all in the case of
CMOS circuits including gate electrodes of aluminium with a high threshold voltage, and which are intended to be operated at high supply voltages.
It has been assumed that this was due to the overlap capacitances between gate electrodes and the drain regions. In fact, in the case of the CMOSinverter, the gate electrodes and the drain electrodes of the n-channel and of the p-channel transistor are in connection with one another via evaporated aluminium conductor patterns. During the switching process, therefore, a portion of the voltage variation at the gate electrode is transferred by the overlap capacitance of the gate electrode, capacitively to the drain region of the transistors.
An infinitely steep voltage step AUG at the gate electrode, therefore, causes on the drain electrode the voltage variation
AUD = AU0max= XUG CÜ/Ck Wherein Cu is the overlap capacitance between the gate electrode and the drain region, and Ck is the entire nodal capacitance on the drain side including Cü When considering now the case where the gate potential jumps from its "most positive" to its "most negative" value then, owing to a capacitive voltage division, the gate potential of the n-channel transistor will jump from 0 to #AUD.
Considering that the island-shaped area in the stationary state is everywhere applied to zero, there is caused subsequently to the voltage step, via the drain junction, the voltage drop AUD which, according to one calculation, may amount to 2 V.
The drain region becomes negative with respect to the island-shaped area and starts to draw a forward current when UD > L 07V, L=L that is, higher than the threshold voltage of the drain-pn-junction. When this is the case, a forward current will flow via this junction and, as is well known, will lead to a charge carrier injection above all into the high-ohmic side, that is, into the islandshaped area adjacent to the drain-pn-junction.
Since the junction biased in the reverse direction is positioned in the close proximity between the island-shaped area and the substrate, said junction will act like a collector junction upon the electrons injected by the drain region into the p-doped island-shaped area. At a sufficiently strong injection, the voltage then breaks down across the junction between the island-shaped area and the substrate. The latter loses it barrier effect and thus causes the switching through of the four-layer structure n-channel-source/p-island/n-substrate/pchannel-source region, with this generally being referred to as the "thyristor" effect.
The invention starts out from this recognition.
Decisive for the setting up of the thyristor effect is the condition AU D#0#7" LL
UD will in practice not quite reach its theoretical maximum value AUDmax = AU6 CuiCk because the resulting potential difference between the drain region and the source region of the n-channel field-effect transistor immediately starts to compensate itself by the current flow through the transistor which is at present still in the conducting state, with the parts "source" and "drain" being changed owing to the potential conditions during this compensating phase.
When AUD has not exceeded during this phase the critical value necessary for the firing, i.e.
AUDcrit ~ 0.7 V then the thyristor effect will not appear and the switching operation is performed normally: the p-channel transistor is rendered conductive, the n-channel transistor is rendered non-conductive and the drain potential (at the output of the inverter) reaches its "most positive value" Ua.
Of course, this thyristor effect can also be suppressed by a slower driving and applying flat voltage edges to the gate electrodes, by a highly resistive design of the driving stage (small W/L relationships), by enlarging the nodal capacity Ck, for example, by enlarging the diffused drain region areas, or else also by reducing the injection-effect drain region-island-substrate, though not without further ado and not without causing further drawbacks, such as a sacrifice in speed.
According to one aspect of the invention there is provided a CMOS integrated circuit, including an adjacently disposed complementary pair of transistors, wherein one transistor is formed in an island of semiconductor material of opposite conductivity type to the substrate, and wherein the drain of each said transistor is coupled to a
Schottky barrier contact provided on said island.
According to another aspect of the invention there is provided an integrated circuit, including a pair of complementary insulated-gate field-effect transistors with the source region and the drain region of the one field-effect transistor being arranged superficially in an island-shaped area of the second conductivity type inserted into the surface side of a semiconducting substrate of the first conductivity type, with the source region as well as the drain region of the other field-effect transistor being inserted into the surface side of the substrate and a connection between the two drain electrodes of the two field-effect transistors to which the input signal is applied, wherein the island-shaped area has a Schottky barrier contact having a lower threshold voltage than the pnjunction between said island-shaped area and the drain region of the field-effect transistor arranged within said island-shaped area, and wherein said
Schottky barrier contact is in contact with the connection between the two drain regions.
In the case of a monolithic integrated CMOS circuit embedded in a silicon substrate it is possible to use, e.g. an Al-Si-contact which prevents the potential of the drain region from being capacitively lowered below that of the p-island by more than the Schottky threshold voltage. However, it is also possible to use other metals for establishing the Schottky barrier contact as is known, for example, from the technical journal "Solid-State Electronics", Vol. 14 (1971), pp. 71 to 75, and "IEEE Transactions on
Electron Devices", Vol. ED-16, No. 1 (Jan. 1969), pp. 58 to 63. In this way it is safeguarded that the threshold voltage (threshold voltage in the forward direction) of the Schottky barrier contact remains below that of a pn-junction.
Since the Schottky threshold voltage is lower than that of the junction of the drain region, the current not consisting of minority charge carriers and flowing across the Schottky barrier contact, leads to a discharge on the drain side, thus preventing a forward current flow with an injection via the junction of the drain region.
Analogously it is also possible to provide a
Schottky barrier contact between the drain region of the p-channel transistor and the substrate. In many cases, however, one Schottky barrier contact on the side of the n-channel field-effect transistor will be sufficient, because there the danger of an injection into the junction between the island-shaped area and the drain region is greater (higher cc) than if it were to extend from the drain region of the p-channel field-effect transistor.
Embodiments of the invention will now be described with reference to Figs. 1 to 4 of the accompanying drawings, in which:
Fig. 1 partly in a cross-sectional view taken almost vertically through a plate-shaped substrate, shows a monolithic integrated CMOSinverter circuit,
Fig. 2 shows three equivalent circuit diagrams relating to the current path of the potential from zero to UB extending via the island-shaped area and the substrate,
Fig. 3 shows the monolithic integrated CMOSinverter circuit including a Schottky barrier contact, and
Fig. 4 shows the two equivalent circuit diagrams relating to the Schottky barrier diodes on both the p-doped island-shaped area and the n-substrate.
Fig. 1, in a sectional view, shows a monolithic integrated CMOS circuit, connected as an inverter.
For establishing an n-channel field-effect transistor, an island-shaped p-conducting area 2 has been let into an n-type substrate; this can be carried out in the conventional way by employing a planar diffusion process. Let into this area 2 are the drain region 5 and the source region 10, whereas next to the area 2 forming a junction 7 with the substrate 1, the drain region 6 and the source region 9 of the p-channel field-effect transistor are produced by planar diffusion. The input signal is applied at U6 to the connection between the two gate electrodes 1 1 and 12. The power supply with UB > O is applied between the substrate and the source region 9 on one hand, and the island-shaped area 2 at zero potential on the other hand.
Fig. 2 shows the equivalent circuit diagram of
Fig. 1 including the three pn-diodes between the respective regions 1, 2, 6 and 10, the reference numerals of which being attached to the connections extending between the pn-diodes.
Fig. 2a relates to the ideal case where 0 < UD ( UB, with at least -0.7 < #U D < UB+O.7V applying in the utmost.
Fig. 2b relates to the case where the thyristor is "fired" by the parasitic pn-transistor, with the firing being effected through the drain region 5, which, so to speak, is to be considered as an auxiliary emitter region of a thyristor having the following succession of regions: source region 10/island-shaped area 2/substrate 1/source region 9. Accordingly, the drain region 5 is to be looked upon as the emitter zone of a parasitic equivalent circuit diagram transistor T1 to which there is temporarily applied a voltage
UD = LNUD < ~0-7 V.
Fig. 2c refers to the case where a thyristor is fired by a parasitic pnp-transistor T2 using the drain region 6 as the emitter region. To this there is applied, for the firing, the voltage UD=UB+AUD > UB+0.7V provided that, as usual, silicon is used as the semiconducting material.
Fig. 3 is a sectional view corresponding to
Fig. 1, illustrating a monolithic integrated CMOScircuit employing a Schottky barrier contact 3 or 4 connected to the drain region 5 of the n-channel field-effect transistor or to the drain region 6 of the p-channel field-effect transistor respectively.
In most cases, however, the Schottky barrier contact 4 on the substrate 2 may be omitted, because normally the drain region 5 of the n-channel field-effect transistor will be lying much closer to the junction 7 acting as the collector junction of the aforementioned thyristor, i.e.
between the island 2 and the substrate 1, than the drain region 6 of the p-channel field-effect transistor.
Fig. 4a shows the equivalent circuit diagram relating to the Schottky barrier contact 3 on the island-shaped area 2, with a parasitic transistor TI and the drain region 5 becoming effective, while
Fig. 4b shows the equivalent circuit diagram relating to the case where the Schottky barrier contact 4 is arranged on the substrate 1 with the parasitic transistor T2 respectively.
Claims (5)
1. A CMOS integrated circuit, including an adjacently disposed complementary pair of transistors, wherein one transistor is formed in an island of semiconductor material of opposite conductivity type to the substrate, and wherein the drain of each said transistor is coupled to a
Schottky barrier contact provided on said island.
2. An integrated circuit, including a pair of complementary insulated-gate field-effect transistors with the source region and the drain region of the one field-effect transistor being arranged superficially in an island-shaped area of the second conductivity type inserted into the surface side of a semiconducting substrate of the first conductivity type, with the source region as well as the drain region of the other field-effect transistor being inserted into the surface side of the substrate and a connection between the two drain electrodes of the two field-effect transistors to which the input signal is applied, wherein the island-shaped area has a Schottky barrier contact having a lower threshold voltage than the pnjunction between said island-shaped area and the drain region of the field-effect transistor arranged within said island-shaped area, and wherein said
Schottky barrier contact is in contact with the connection between the two drain regions.
3. An integrated circuit as claimed in claim 2, wherein the substrate has a further Schottky barrier contact having a lower threshold voltage than the junction between said drain region of the field-effect transistor arranged in the substrate, and said substrate, and that said further
Schottky barrier contact is in contact with the connection between said two drain regions.
4. An integrated circuit substantially as described herein with reference to Figs. 3 and 4 of the accompanying drawings.
5. A method of four layer thyristor suppression in a CMOS integrated circuit, which method is substantially as described herein with reference to the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE2929869A DE2929869C2 (en) | 1979-07-24 | 1979-07-24 | Monolithic integrated CMOS inverter circuitry |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2054955A true GB2054955A (en) | 1981-02-18 |
| GB2054955B GB2054955B (en) | 1983-05-11 |
Family
ID=6076567
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8020110A Expired GB2054955B (en) | 1979-07-24 | 1980-06-19 | Menolithic integrated cmos circuit |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS5618459A (en) |
| DE (1) | DE2929869C2 (en) |
| FR (1) | FR2462025A1 (en) |
| GB (1) | GB2054955B (en) |
| IE (1) | IE50350B1 (en) |
| IT (1) | IT1193544B (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0166386A2 (en) * | 1984-06-29 | 1986-01-02 | Siemens Aktiengesellschaft | Integrated circuit of the complementary circuit technique |
| EP0213425A2 (en) * | 1985-08-26 | 1987-03-11 | Siemens Aktiengesellschaft | Complementary integrated circuit with a substrate bias voltage generator and a Schottky diode |
| EP3216051A4 (en) * | 2014-10-10 | 2018-06-06 | Schottky Lsi, Inc. | SUPER CMOS (SCMOStm) DEVICES ON A MICROELECTRONIC SYSTEM |
| US10373950B2 (en) | 2008-12-23 | 2019-08-06 | Schottky Lsi, Inc. | Super CMOS devices on a microelectronics system |
| US10666260B2 (en) | 2008-12-23 | 2020-05-26 | Schottky Lsi, Inc. | Schottky-CMOS asynchronous logic cells |
| US11342916B2 (en) | 2008-12-23 | 2022-05-24 | Schottky Lsi, Inc. | Schottky-CMOS asynchronous logic cells |
| US11955476B2 (en) | 2008-12-23 | 2024-04-09 | Schottky Lsi, Inc. | Super CMOS devices on a microelectronics system |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57177554A (en) * | 1981-04-27 | 1982-11-01 | Hitachi Ltd | Semiconductor integrated circuit device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3673428A (en) * | 1970-09-18 | 1972-06-27 | Rca Corp | Input transient protection for complementary insulated gate field effect transistor integrated circuit device |
| JPS568501B2 (en) * | 1973-05-12 | 1981-02-24 | ||
| JPS5211885A (en) * | 1975-07-18 | 1977-01-29 | Toshiba Corp | Semiconductor integrated circuit device |
| JPS5211880A (en) * | 1975-07-18 | 1977-01-29 | Toshiba Corp | Semiconductor integrated circuit device |
| JPS6043666B2 (en) * | 1976-10-18 | 1985-09-30 | 株式会社日立製作所 | Complementary MIS semiconductor device |
| JPS53105985A (en) * | 1977-02-28 | 1978-09-14 | Nec Corp | Conmplementary-type insulating gate field effect transistor |
-
1979
- 1979-07-24 DE DE2929869A patent/DE2929869C2/en not_active Expired
-
1980
- 1980-06-19 GB GB8020110A patent/GB2054955B/en not_active Expired
- 1980-07-18 JP JP9860980A patent/JPS5618459A/en active Pending
- 1980-07-23 IT IT23632/80A patent/IT1193544B/en active
- 1980-07-23 FR FR8016206A patent/FR2462025A1/en active Granted
- 1980-07-23 IE IE1530/80A patent/IE50350B1/en unknown
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0166386A2 (en) * | 1984-06-29 | 1986-01-02 | Siemens Aktiengesellschaft | Integrated circuit of the complementary circuit technique |
| EP0166386A3 (en) * | 1984-06-29 | 1987-08-05 | Siemens Aktiengesellschaft | Integrated circuit of the complementary circuit technique |
| EP0213425A2 (en) * | 1985-08-26 | 1987-03-11 | Siemens Aktiengesellschaft | Complementary integrated circuit with a substrate bias voltage generator and a Schottky diode |
| EP0213425A3 (en) * | 1985-08-26 | 1988-09-21 | Siemens Aktiengesellschaft Berlin Und Munchen | Complementary integrated circuit with a substrate bias voltage generator and a schottky diode |
| US4807010A (en) * | 1985-08-26 | 1989-02-21 | Siemens Aktiengesellschaft | Integrated circuit in complementary circuit technology comprising a substrate bias voltage generator and a Schottky diode |
| US10373950B2 (en) | 2008-12-23 | 2019-08-06 | Schottky Lsi, Inc. | Super CMOS devices on a microelectronics system |
| US10666260B2 (en) | 2008-12-23 | 2020-05-26 | Schottky Lsi, Inc. | Schottky-CMOS asynchronous logic cells |
| US10991686B2 (en) | 2008-12-23 | 2021-04-27 | Schottky Lsi, Inc. | Super CMOS devices on a microelectronics system |
| US11342916B2 (en) | 2008-12-23 | 2022-05-24 | Schottky Lsi, Inc. | Schottky-CMOS asynchronous logic cells |
| US11658178B2 (en) | 2008-12-23 | 2023-05-23 | Schottky Lsi, Inc. | Super CMOS devices on a microelectronics system |
| US11870438B2 (en) | 2008-12-23 | 2024-01-09 | Schottky Lsi, Inc. | Schottky-CMOS asynchronous logic cells |
| US11955476B2 (en) | 2008-12-23 | 2024-04-09 | Schottky Lsi, Inc. | Super CMOS devices on a microelectronics system |
| EP3216051A4 (en) * | 2014-10-10 | 2018-06-06 | Schottky Lsi, Inc. | SUPER CMOS (SCMOStm) DEVICES ON A MICROELECTRONIC SYSTEM |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2462025B1 (en) | 1983-11-18 |
| DE2929869A1 (en) | 1981-02-19 |
| IT8023632A0 (en) | 1980-07-23 |
| DE2929869C2 (en) | 1986-04-30 |
| JPS5618459A (en) | 1981-02-21 |
| IE801530L (en) | 1981-01-24 |
| IE50350B1 (en) | 1986-04-02 |
| IT1193544B (en) | 1988-07-08 |
| FR2462025A1 (en) | 1981-02-06 |
| GB2054955B (en) | 1983-05-11 |
| IT8023632A1 (en) | 1982-01-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 727 | Application made for amendment of specification (sect. 27/1977) | ||
| 727A | Application for amendment of specification now open to opposition (sect. 27/1977) | ||
| 727B | Case decided by the comptroller ** specification amended (sect. 27/1977) | ||
| SP | Amendment (slips) printed | ||
| PCNP | Patent ceased through non-payment of renewal fee |